introduction to space microelectronic products october 2009
TRANSCRIPT
Introduction To Space Microelectronic ProductsOctober 2009
Take Home Messages
• Honeywell Is An Experienced, Fully Qualified Supplier Of Space Microelectronics, Ready To Work With You To Apply Our Capabilities To Your Programs
- Digital And Mixed Signal ASICs, SRAMs, NVRAM, SERDES And Multi-Chip Modules
- Obsolete IC Replacements, Including FPGA To ASIC Conversions
- Proprietary Technology Built In Our Own Trusted Foundry
- QML Certified Quality Systems In Place
- Semiconductor Industry Experienced Management Team
• Let’s Use This Meeting To Answer Your Questions And Deepen Your Understanding Of Our New Product Offerings
Experienced, Qualified And Ready
M&PS Product Lines
Rad Hard IC’s Pressure Sensors Magnetic Sensors Commercial IC’s
Microelectronics & Precision Sensors
“Best in Class Radiation
Performance”
“Most Precise Pressure Sensors In
The Industry”
“Miniature High Precision Integrated
Magnetic Sensor”
“RF ComponentsAnd Mixed Signal
Custom ICs”
Our Trusted Foundry Supports Multiple Product Lines For Balanced Growth
IC Emulations
“Replacement Of Obsolete IC’s For Life Extension Of Critical Systems”
Leading Source For Space Microelectronics
Expanded 150 nm Production • $100M Of Building & Equipment• 8 Inch 150nm, 10,000 SF Clean Room• Digital & Mixed Signal Process Flows• QML Qualified Processes• Committed To Maintain Thru 2015
Mature Production • 6 Inch 0.8/0.35um, 40,000 SF Clean Room• 0.8 Micron Production Since 1995• 0.35 Micron Production Since 2001• Capable Of Classified Design,
Fabrication And Assembly• Committed To Maintain Thru 2015
Qualified And Ready For More Demand
Trusted Foundry Accreditation
Leading Strategic Rad Hard IC Trusted Foundry!
Approaches To Achieving Hardness
Hardened By Process Is Most Efficient Approach
• Radiation Hardness Achieved By SOI CMOS Process And Numerous Other Techniques
1.Rad Hard By Process (RHBP)• SRAMs Built On SOI CMOS With Inherent
Radiation Hardness Compared To Bulk CMOS (Total Dose To 1M Rad)
• Hardened Dielectrics• Optimized Transistor Structures
2.Can Also Implement Rad Hard By Design (RHBD) Techniques When Beneficial
• Radiation Hardness Addressed At All Levels- Architectural: Floorplanning, Improve dynamic
SEU performance
- Unique Devices: Active Delay Elements
- Memory Cell Design: Transistor Quantity, Hardening Elements
- Layout: Alignment Of Critical Cells And Nodes, Power Bussing, Customized Design Rules
- Logic And Other Circuits: Hardened Logic Cells, Specialized Timing Techniques
- System Level EDAC – Done External If Required
Small area for SEE energy
Large area to capture SEE energy
No EDAC Or Refresh Required For SRAM SEU Performance
No EDAC Or Refresh Required For SRAM SEU Performance
Honeywell Products
SOI CMOS Wafer Processes
Buried SiO2 Layer Provides- Radiation Hardness
- Ultra High Reliability
- 30% To 40% Faster Circuits At Same Node
- 30% To 40% Lower Power At Same Node
- Excellent Isolation For Mixed Signal ASICs
- Continuous High Temp Operation At 225°C
QML Qualified Source For Space Microelectronics
SOI CMOS
Bulk CMOS
N+ P+ P+
S DG S DG
Silicon Substrate
N+
Silicon Substrate
SiO2
High Capacitance Region Substantially Reduced By Buried Oxide Layer
Bulk CMOS
N+ N+ P+ P+
S DG S DG
SiO2
Silicon Substrate
N+N+
Silicon Substrate
Transistor Cross SectionsSOI-4 SOI-5 S150
Production* Now Thru 2015+
Now Thru 2015+
Now Thru 2015+
Interconnect 4 Level CuAl
4 Level CuAl
8 Level CuAl
Gate Length .7 um .35 um 150 nm
Wafer Size 150 mm 150 mm 200 mm
Devices NCh, PCh, DMOS NCh, PCh NCh, PCh
Vdd (V) 3.3-20 3.3 3.3/2.5/1.8
Hardened By Process Process Process
ProcessOptions
CrSi, RF Discrete
CrSi, EEPROM
MIMCAP, Bump/FC
* Assured Source Of Supply To Major Space Programs
Rad Hard Digital ASIC Family
Platform HX2000 HX3000 HX5000 Structured Array
Process 0.8 um 0.35 um 150 nm 150 nm
# Base Arrays 5 4 6 1
Max # I/O 372 388 1330 824
Useable Gates 40-390K 235-1,200K 2-15M** 3M
Design IP Honeywell, Customer
Honeywell, Customer
Honeywell SERDES, Synopsys
Honeywell, Synopsys
Self Test JTAG JTAG JTAG, MBIST JTAG, MBIST
Design Flow Cadence Cadence Synopsys Synopsys
Qualification QML QML QML QML
Foundry Trusted Trusted Trusted Trusted
15 Digital ASIC Product Platforms
* (nW/gate/MHz) ** maximum number depends on mix of logic and memory
HX5000 & S150 QML Qualification Completed
• S150H and Technology QML Qualification Received – 4/22/08
• 16Mb SRAM and 4Mb SRAM QML Qualification Received – 4/22/08 & 7/08
• HX5000 QML Qualification Received – 11/18/08
• QML Qualification For The HX5000 ASIC Family Qualifies The Baseline Design Flow, Libraries, And All Manufacturing And Test Processes.
• Qualification Vehicle Size: 3.9M gates
• New HX5000 Designs
• Qualification does not put a limit on gate count. DSCC and Honeywell have agreed for each ASIC larger than previously qualified, the following will be performed:
• Ensure design and software tools are the same as used on the qual vehicle or are requalified
• Ensure all timing closes
• Complete standard QML V QCI life test on device that encompasses the complexity of the larger ASIC (the new ASIC)
16M SRAM (x8) 16M SRAM (x32) HX5000 4M SRAM
HX5000 / S150 Successes
• PDV 1.6M gates• Customer test chip 4.1M gates• QTV 3.9M gates• 4M SRAM Memory• 16M SRAM Memory• 1M MRAM NV Memory• Trivor (RT) SERDES• Trivor (RH) SERDES• Customer ASIC 1 6.9M gates• Customer ASIC 2 4.0M gates• Customer ASIC 3 12.4M gates
A record of successful 150nm designs – lowest risk for your programs
ASIC Trends
700 ASICs Designs Delivered to Space Customers Without a Mission Failure
Space Programs Require Long Production Technology Cycles
• RICMOS IV was 12 years• SOI IV is 14 years and counting• SOI V is 9 years and counting
Honeywell Will Support Your Long Life Program Needs
technology development preprod/valid/eval production obsolescenceRICMOS IV 10/2/1991 5/15/1992 5/15/1992 7/1/2003SOI IV 1/27/1995 4/23/1996 4/23/1996SOI V 8/21/2000 11/10/2000 11/27/2001S150 (CY) 3/1/2003 9/1/2005 na naS150 (HI) 6/22/2006 9/19/2006 7/12/2007
QML Qualified HX5000 ASIC Design Flow
Chip SpecificationDevelopment
Synthesis
RTL Design
RTL Refinementand Optimization
Verification
Floorplan
PhysicalSynthesis
ASIC Fabrication
PackageRequirements
TestRequirements
PackageDevelopment
TestDevelopment
Assembly
Test
Screening
Place and Route
SystemSpecificationDevelopment
Design FlowEntry DFT
Honeywell Design Flow
Typical Responsibilities
Customer Customer-Honeywell Honeywell
Phase 1 Trial Place and Route
Proven On Numerous Programs And Tapeouts
Rad Hard Mixed Signal ASIC Platforms
Platform HMX2000 HMX3000 HMX5000
Process 0.8 um 0.35 um 150 nm
# Base Arrays 5 4 6
Max # I/O 372 388 1000
Useable Gates 40-390K 235-1,200K 2-15M*
Design IP Honeywell, Customer
Honeywell, Customer
Honeywell SERDES, Synopsys
Device TypesNch,Pch, Lincap, DMOS, Inductor,
CrSi Resistor
Nch,Pch, Lincap, DMOS, Inductor,
CrSi Resistor
Nch, Pch, MIMCap
Design Flow Cadence Cadence Synopsys
Qualification QML QML QML
Available Now Now Now
15 Different Platforms Available Today* maximum number depends on mix of functions
HMX2000 Mixed-Signal Design IP
Technology
• 0.7µm, 3 or 4 Layer Metal, SOI-IV Wafer Process• 5V Operating Voltage• NMOS cutoff frequency (Ft) 15GHz• NMOS Vt Matching 1sigma ~1.0mV • PMOS Vt Matching 1sigma ~1.5mV • Inductors (Metal Spiral) Q~2-5, 2-5nH• Linear Capacitor 100ppm/Volt, 0.5fF/µm2• DMOS: NMOS and PMOS >20 Volts Breakdown• Lateral Bipolar : ß>20• CrSi Resistor: 300ppm/°C, 2.5KΩ/sq.
Realizable In Gate Array Family
Gate Array Core Gates Usable Gates Max I/O----------------- ---------------- ---------------- -----------
• HMX2040 40K 36K 132
• HMX2080 85K 71K 176
• HMX2160 160K 132K 240
• HMX2300 295K 226K 336
• HMX2400 390K 290K 372
Verified In Silicon Design IP Blocks • 8-Bit Successive Approx. ADC• 12-Bit Pipeline ADC• 12-Bit Current Steering DAC • Analog Cells• Op-amps• Current Bias Generators• Band-gap Voltage Reference• Power-Up Reset• Auto-zero Comparator • Dual Ramp Oscillator• Crystal Controlled Oscillator
Proven-In-Silicon Mixed Signal ASIC Design IP
Design IP Realized In HMX2000
Technology
• 0.35µm, 4 Layer Metal, SOI-V Wafer Process• 3.3V Operating Voltage• NMOS Cutoff Frequency (Ft) 25-45GHz• NMOS Vt Matching 1sigma ~1.0mV • PMOS Vt Matching 1sigma ~1.5mV • Inductors (Metal Spiral) Q~6-12, 2-5nH• Linear Capacitor 100ppm/Volt, 0.5fF/µm2• DMOS: NMOS And PMOS >20 Volts Breakdown• CrSi Resistor: 300ppm/°C, 2.5KΩ/sq.
Verified In Silicon Design IP Blocks
• Op Amps
• A/D Converters
• Voltage References
• CMOS, PCI And LVDS I/O
• Comparators
• Oscillators
• Single Port Embedded SRAMs
• Dual Port Embedded SRAMs
HMX3000 Mixed-Signal Design IP
Realizable In Gate Array Family
Gate Array Core Gates Usable Gates Max I/O----------------- ---------------- ---------------- -----------
• HMX303 249K 215K 176
• HMX306 473K 450K 240
• HMX311 880K 770K 336
• HMX314 1.17M 1.0M 388
Proven-In-Silicon Mixed Signal ASIC Design IP
Design IP Realized In HMX3000
Technology
Capability Features
• Up To 12M Gates
• Core Operating Speed > 500MHz
• I/O Speeds 750MHz – 1GHz
• Full Military Temp (-55C To 125C)
• Supports Rad Hard And Rad Tolerant Apps.
HMX5000 Mixed-Signal ASIC Capability
Verified In Silicon Design IP Blocks
• Comprehensive Library Of > 600 Standard Cells
• Family Of 4/8 Channel SERDES Hard/Soft Macros
• Family Of Delay Locked Loops (DLL)
• Family Of Phase Lock Loops (PLL)
• Vdd (Core Voltage) 1.8V
• I/O Voltage 3.3/2.5/1.8V
• Gate Dielectrics 30Å & 60Å
• Gate Length (drawn) 150 nm
• Gate Length (effective) 120 nm
• Metal Layers 4, 6, 8
• Gate Delay/Stage 26 ps (RO Inverter FO=1; T-25º)
• MIM Cap Option
Proven-In-Silicon Mixed Signal ASIC Design IP
Design IP Realized In HMX5000
Structured Array Product For 2011
• Uses Latest Synopsys Design Software Tools
• Replaces Actel AX2000 And Xilinx 2V8000 FPGAs To Provide Flight Qualified ASICs
• Available 2010
Product Features
• 3M Logic Gates
• 1.2M Bits SRAM
• 824 Signal I/O
• 8 PLLS
• 1.8V Core Vdd
• 1.5, 1.8, 2.5 3.3V
I/O Vdd
HX5000 Based SeaOf Transistors Cell
SERDES Communication I/O
• RADHARD/Tolerant Design Using Honeywell’s SOI Technology That Can Be Integrated Into An HX5000 ASIC
• Supports Multiple Standards- 10GE (4x3.125 Gbps XAUI)- 10G Fibre Channel (4x3.1875 Gbps XAUI)- 1G FC / 2G FC / 4G FC
• Low Power- 125 mW Per Channel @ 1.8V- 4–20 Channels With A Single VCO
• High Signal Integrity- Superior Distance
FR4 backplane > 1m @ 4.25 Gbps Infiniband cable > 15m @ 4.25 Gbps
- Margin Increases At Lower Data Rates- Low jitter
TX DJ = 0.20 UI, TX TJ = 0.33 UI RX DJ = 0.33 UI, RX TJ = 0.62 UI
- BER Of 1e-14
• Individual Channel Programmability- Selectable Data Rate- Selectable Signal Shaping For
Optimization Of Individual Channels
• Built In Self Test- At Speed Testing Of High-speed Circuitry
For Diagnostics And At-Speed Verification On An ATE Platform
Experienced, Qualified And Ready
SERDES Overview – Description From An ASIC Designers Viewpoint• Physical
- 1.8V macro includes IO & core logic
- 75-pads wide and 2300um deep
- Has placement constraints and most likely needs a custom package design
- 100-ohm resistor termination is internal, AC-Coupling caps are external. 150-ohm option being developed
- The only external parts needed are an external bias resistor and AC-Coupling Caps
• Functional- 8 Transmit Lanes and 8 Receive Lanes
- Multiple core-side interface points
- Protocol logic can be bypassed
- Verilog Model includes the analog and digital portions of SERDES8_TOP
- Includes loopback and BIST for at-speed test purposes
• Performance- Core runs at 1/10th or 1/20th the line rate
- All Core-Side handoffs on the VDD domain
Transmit Lanes (4)
ReceiveLanes (4)
PLL Transmit Lanes (4)
Receive Lanes (4)
Protocol Logic
8 Lane SERDES Macro
Quad Redundant SERDES Standard Product
Product Features• Production Units Available Now• Quad SERDES W/Redundant Serial IO• Parallel Interface Using SSTL2 IO• Programmable Input And Output Buffers• 468 LGA Package
Protocol Support• 1gbps To 4.25gbps For General
Backplane Applications• 1G/2G/4G & 10G (XAUI ) Fibre Channel• 1G And 10G (XAUI) Ethernet• Multiple Bypass Modes
JTAG MDC/MDIO CMU (PLL and Clocks)
Configuration and Control
Registers
4 Channels Port A
4 Channels Port B
RX 2:1 MUX
4 Channels Port A
4 Channels Port B
Parallel Interface 4 Channels
4 Channels
RX 8
8
8
8
RXD_0
RXD_1
RXD_2
RXD_3
TX 8
8
8
8
TXD_0
TXD_1
TXD_2
TXD_3
Port A RX Diff Pairs TX Diff Pairs
8
8
8
8
8
8
8
8
RX0_A
RX1_A
RX2_A
RX3_A
TX0_A
TX1_A
TX2_A
TX3_A
Port B RX Diff Pairs TX Diff Pairs
8
8
8
8
8
8
8
8
RX0_B
RX1_B
RX2_B
RX3_B
TX0_B
TX1_B
TX2_B
TX3_B
Ready To Delivering Units Today
SERDES Evaluation Kit
• Accepting Orders NOW ForImmediate Delivery!
• Enables Evaluating Both The SERDES Macro And The Standard Product
• Evaluation Kit Contains
- SERDES Evaluation Board
- Cables And Software
- Documentation
- Video Of Honeywell Demo
• Literature And Users Guide Available
• Sole Sourced Without Competition From
BAE, Aeroflex Or FPGA Suppliers
Let’s Customer Learn How To Use SERDES, Ready For Customer Orders Now
Static RAM Product Update
Organization Package Production Spec Sheet
HX6256 32K X 8 28 DIP, FP Now On web site
HX6228 128K X 8 32 And 40 FP Now On web site
HX6408 512K X 8 36 FP Now On web site
HXS6408 512K x 8 36 FP Now On web site
HXSR01608 2M X 8 40 FP Now On web site
HXSR01608 512K X 32 86 FP Now On web site
HXNV0100 64K X 16 64 CQFP Mid 09 On web siteAll SRAMs Are Radiation Hardened By Process And Optimized For Use In 1M Total Dose, High SEU Dose Environments.
QML Qualified With SMD Numbers,Ready For Immediate Design In
Sole Source Products!
Leadership Products!
HXSR01608 2M X 8 16Mbit SRAM Product
• Monolithic Silicon Die Designed For Use In Low Voltage Systems
• Measured Radiation Hardness Is
> 1MRad (Si) Total Dose
< 2X10e-12 Upsets/Bit-day SER
> 1X10e14 Neutrons/cm2 Neutron
> 1X10e10 Rads (Si)/s Dynamic
Transient Upset
> 1X10e12 Rads (Si)/s Dose Rate
> No Latch Up
• QML Qualified Process And Product
• Customized Memory Modules Available
40 Pin Flatpack PackageSMD Number 5962-08202
Now Shipping QML Qualified Flight Units
HXSR01632 512K X 32 16Mbit SRAM Product
86 Pin Flatpack PackageSMD Number 5962-08203
Now Shipping QML Qualified Flight Units
• Monolithic Silicon Die Designed For Use In Low Voltage Systems
• Measured Radiation Hardness Is > 1MRad (Si) Total Dose < 2X10e-12 Upsets/Bit-day SER > 1X10e14 Neutrons/cm2 Neutron > 1X10e10 Rads (Si)/s Dynamic
Transient Upset > 1X10e12 Rads (Si)/s Dose Rate > No Latch Up
• QML Qualified Process And Product
HXS6408 4M SRAM ProductRadiation Performance- Total Dose 1M Rad (Si)
- Latch Up None
- Dose Rate Upset 1e10 rad (Si)/sec- Dose Rate Survival 1e12 rad (Si)/sec
- SEU 1e-11 Upsets Per Bit-Day
- Neutron Fluence 1e14 N/cm Squared
Functional Diagram Target CustomersIn USA All In Rad Hard Segment
In Europe All In Rad Hard Segment
In Japan All In Rad Hard Segment
Product Quality & ReliabilityMade In Trusted Foundry In USAQML Manufacturing Process QML-V And QML-S Screening FlowsLife Test Data Available
524,288 x 8
Memory Array
Column DecoderData Input/Output
RowDriver
A<0-8>
A<9-18>
DQ<0-7>
NWE
NOE
NCS
NWE+CS+OE
WE+CS
Voltage Regulator
NVRENVDD
Key Selling Points
- Rad Hard By Process!- Low Power!- 512K X 8 Organization!
- < 20nS R/W Cycle Time!
- Lower Price Than HX6408!
- Exportable With License!
Now Shipping QML Qualified Flight Units
64M SRAM Memory Module Product
New Leadership Memory Product
• Uses Proven 512K X 32 SRAM Die
• Configured As 2M X 32
• 86 Lead Flatpack-1.23 X 0.96 X 0.19 Inches- (16M X32 SRAM: 1.13 X 0.85 X 0.16 Inches)
• Initial MCMs Have Been Built And Tested- Currently In Burn-in
• Production Upgrade Planned For End Of Q1 2010
• Future Plans For x40, 80Mb Module As Well
HXNV0100 1M Non Volatile MRAM Product
Production April 2010
• 64K X 16-bit Non-volatile Memory- No Data Loss On Power Down Or Power Interruption
• Radiation Hardened For Strategic Applications• No Wear Out - Unlimited Writes• Non-destructive Readout (NDRO)• Magneto-resistance (MRAM) Memory Bits• Magnetically-shielded 64-pin Ceramic Package• Error Correction Code (ECC)
- Single EDAC Per Address
• Performance- < 70 nS Read Cycle Time- < 100 nS Write Cycle Time- < 500 mW Active Power- < 100 mW Standby Power- 1.8V Core And 3.3v I/O
HMXADC9225 12-bit A/D Converter Product
• Radiation Hardened Monolithic 12-bit A/D Converter• 25 MSPS, 4 Stage Pipeline Architecture• On-chip Sample-and-hold Amplifier • Single +5volt Analog Supply• 5V Or 3.3V Digital Tri-state I/O• Requires External 1-2 Volts Vref • 28-lead Space Qualified Ceramic Package
• Performance- Rad Hard to >1M Rad(Si) TID- No Latchup - No Missing Codes Guaranteed- Differential Non-Linearity Error: 0.4 LSB- Straight Binary Output Data- Signal-to-Noise and Distortion Ratio: 69.6 db- Spurious-Free Dynamic Range: - 81 db- Typical Low Power: 345mW
HMXADC9225 Now Shipping,HMXADC9246 14 Bit Version In Development
Radiation Hard Analog and Digital SSI components
- RS422 Driver 16 lead ceramic package Pin-for-Pin compatible with commercial
version
- RS422 Receiver 16 lead ceramic package Pin-for-Pin compatible with commercial
version
- LVDS Driver Low power, low noise 16 lead ceramic package
- LVDS Receiver Low power, low noise 16 lead ceramic package
- Quad Nand Gate High current drive capability 14 lead ceramic package
- Analog Multiplexer 16 to 1 Mux 16 lead ceramic package
- Comparator Rail-to-Rail 8 lead ceramic package
- Dual Operational Amplifier Programmable voltage offset and
bandwidth 16 lead ceramic package
- Digital to Analog Converter 12 bit differential current steering
DAC 28 lead ceramic package
- Transceiver 18 bit transceiver 68 lead ceramic package
Honeywell is currently productizing the following SOI CMOS rad hard digital and analog SSI components.
Obsolete Replacement IC “Sweet Spot”
FPGA• Actel 1020, 1280• Actel 54SX32, 54SX72• Xilinx• Atmel
Processor• 1750a• 8 bit, 16 bit, 32 bit MPU• 4 bit, 8 bit, 16 bit, 32
bit MCU• DSP
Memory• SRAM
• 1Kx4• 4Kx1
• FIFOs• EEPROM• ROM• PLD• PAL
ASIC• Radio chipset• Encryption• Communications• Audio/video• Mass storage• Computer peripherals
Analog• Op Amps• Discretes• Ring Osc• Power
Transistors• Rectifiers• Thyristors• Optoelectronics• Sensors• PLL• Std. Linear
•Amplifiers• Application
Specific Analog
Interface Electronics• ECL • RS-232 Controller
Underlined Components Are InHoneywell’s Sweet Spot Today
FPGA Replacement Solutions
FPGA Migrates To Available K Gates Cycle TimeActel 1020 HX2000 Now 1 12 WeeksActel 1280 HX2000 Now 1 12 WeeksActel RTX2000 Structured Array Q409 1000 12-16 WeeksActel MX Series HX2000 Now 1 Call For QuoteActel eX Series HX2000/3000 Now 12 Call For QuoteActel SX Series HX3000 Now 108 Call For Quote
Altera Apex 20k HX3000 Now 500 Call For QuoteAltera Flex Series HX2000 Now 250 Call For QuoteAltera Stratix HX5000 Now 3000 Call For Quote
Atmel AT6002 HXFPGA6010 Now 6 12 WeeksAtmel AT6003 HXFPGA6010 Now 9 12 WeeksAtmel AT6005 HXFPGA6010 Now 15 12 WeeksAtmel AT6010 HXFPGA6010 Now 30 12 WeeksAT40 Series HX2000 Now 50 Call For Quote
Xilinx Spartan II HX2000 Now 250 Call For QuoteXilinx Vertex 2 Structured Array Q409 1000 12-16 WeeksXilinx Vertex 4 HX5000 Now 3000 24-32 Weeks
Experienced At Replacing Many FPGA Families With Flight Qualified ASICS
SOI4/4e/5/S150 Life Test Summary
Aerospace – Plymouth Life Test Summary
• Reliability – June 2009 Status- By product family and operating voltage
* - HX5000 ASIC elevated failure rate due to minimal Device-Hours (46,000).
Product Reliability Calculation and Assumptions
FIT rate calculation = 2 [60%, 2(n+1)] / (2 x DevHrs x AFthermal x AFvoltage)
Where: n = number of failures, AFthermal = Arrhenius, AFvoltage = eß(Vs - Vo)
• Assumptions:- Use temperature (Ave) 55 °C- Life test temperature 150 °C- Use Vdd (Ave) 5.0V, 3.3V or 2.5V- Life test Vdd 5.5V (or 3.6V or 2.5V for Low Voltage SOI technologies)
• Voltage Acceleration Constant (ß)- (SOI – IV/ Ve) ß = 1.25
Performed over 400,000 hrs of Dynamic burn-in on 256K SRAM (SOI-IV)- (SOI-V) ß = 1.7
Performed over 887,500 hrs of Static burn-in on SOI-V (4M SRAM and HX3000 TM)
- (S150) ß = 2.0
• Activation Energy - (SOI –IV/ IVe) Ea = 0.7 eV
Dynamic burn-in on 256K SRAM (SOI-IV) at 125 and 150C. Results on 2 studies totaling over 83,000 dev-hrs were 0.67 and 0.71eV.
- (SOI-V) Ea = 0.6 eV Performed over 887,500 hrs of Static burn-in on SOI-V (4M SRAM and HX3000 TM)
- (S150) Ea = 0.7eV
• Attached Capacitors (assumptions per supplier)
- AFThermal = (Life Temp/Use Temp)8 , AFVoltage =(Life Voltage/ Use Voltage)
Summary
Experienced, Qualified And Ready
• Honeywell Is An Experienced, Fully Qualified Supplier Of Space Microelectronics, Ready To Work With You To Apply Our Capabilities To Your Programs
- Digital And Mixed Signal ASICs, SRAMs, NVRAM, SERDES And Multi-Chip Modules
- Obsolete IC Replacements, Including FPGA To ASIC Conversions
- Proprietary Technology Built In Our Own Trusted Foundry
- QML Certified Quality Systems In Place
- Semiconductor Industry Experienced Management Team
• Let’s Use This Meeting To Answer Your Questions And Deepen Your Understanding Of Our New Product Offerings