introduction to fpga synthesis tools

FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved

Introduction to FPGA Synthesis Tools

Prepared by:Eng. Hossam Fadeel

National Telecommunication Institute2011

© 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 2 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 2 © 2009 Xilinx, Inc. All Rights Reserved

Design LanguagesFlow for FPGA ImplementationOverview of an FPGA DesignTools for synthesis and implementation of FPGAs

Agenda


FPGAadvantageVHDL Entry

ModelSimVHDL Simulation

Leonardo SpectrumFPGA/ASIC Synthesis

SDF File for Timing Simulation

FPGA Implementation Software

Download Design to FPGA

EDF

FPGA Vendor

Flow for FPGA Implementation


Design Languages


Design languages provide the means by which to describe the operation of both software programs and hardware. These descriptions, usually text based, are Developed within the computer on which the descriptions are being Developed. Over the years, a large number of languages have been developed. Some are still in use today, while others have become obsolete.

Design Languages


Software Programming Languages

Software programming languages (SPLs) allow a software designer to create executable software applications that will operate on a suitable processor. The target processor will be one of three types: microprocessor (mP), microcontroller (mC), or digital signal processor (DSP).

Hardware Description Languages

Hardware description language (HDL) design is based on the creation and use of textural based descriptions of a digital logic circuit or system. By using a particular HDL, the description of the circuit can be created at different levels of abstraction from the basic logic gate description according to the language syntax and semantics.

Design languages are of two types, software programming languages (SPL) and hardware description languages (HDL).

Design Languages


Design Languages FlowSoftware flow Hardware flow


Software Programming Languages

Common Software Programming LanguagesCommon Software Programming Languages

C

C++ Visual Basic TM

JAVA

Scripting Language

System C

JavaScript

PERL

Python

PHP

VBScript



Common Hardware Description LanguagesCommon Hardware Description Languages

VHDLSystem

C

Verilog-HDL


When designing with HDLs, the designer chooses what language to use and at what level of design abstraction to work. When choosing language, the following aspects must be considered:

the availability of suitable electronic design automation (EDA) tools to support the use of the language.previous knowledgepersonal preferencesavailability of simulation modelssynthesis capabilitiescommercial issuesdesign re-use




Two-input AND gate description in VHDL



Full-adder description in Verilog-HDL



Analogue voltage amplifier design with a voltage gain of

+2.0

Verilog-A amplifier description



Two modeling languages are emerging for mixed-signal (analogue and digital) electronic and mixed-technology system modeling, these being Verilog-AMS and VHDL-AMS.VHDL-AMS is the AMS extension to VHDL. This was adopted as a standard in 1999 as IEEE Standard 1076.1-1999. As with VHDL, designs are modeled using entities and architectures. Considering the analogue connections and signals, analogue ports are declared with a simple nature (e.g., electrical) and with any associated quantities (e.g., voltage across the port to a reference point and currents through the port).



Verilog-AMS is the AMS extension to Verilog-HDL. It provides the extensions to Verilog-HDL to model mixed-signal (mixed analogue and digital) electronics and mixed-technology (electrical/electronic and nonelectrical/electronic) systems. It encompasses the features of Verilog-D and Verilog-A.


Government Developed

Commercially Developed

Ada based C based

Strongly Type Cast Mildly Type Cast

Case-insensitive Case-sensitive

Difficult to learn Easier to Learn

More Powerful Less Powerful

VHDL vs. Verilog


VHDL vs. Verilog

Verilog VHDL

module gates(a, b, q, r);input a, b;output q, r;

assign q = a & b;assign r = a | b;

end module

library ieee;use ieee.std_logic_1164.all;entity gates is port( a,b: in std_logic; q,r: out std_logic);end;

architecture implement of gates isbegin q <= a and b; r <= a or b;end;


Overview of an FPGA Design

Digital CircuitRequirements

FixedFunctionality

Processor

PLD

Memory

StandardProduct IC

ASICFixed

Functionality

Processor

PLD

Memory

Microprocessor

Microcontroller

Digital SignalProcessor

Simple PLD

Complex PLD

FieldProgrammableGate Array

ROM

RAM

Technology choices for digital circuit design


To enter a design into an EDA tool, a suitable design entry method is required.Typically, tools will allow the following design entry methods:

Circuit schematics present a graphical view of the design using logic gate symbols and interconnect wiring.Boolean expressions can be entered as a text-based description in combinational logic designs.HDL design entry allows a description of the digital logic circuit or system operation to be entered in text form using a suitable language.State transition diagrams present a graphical view of state machines that identifies the design states and the transitions between states.

Design Entry Methods


Once the design has been entered, it must be synthesized. The process of synthesis involves converting the VHDL source files into a netlist. A netlist is simply a list of logical elements (things that combine, change, or store digital signals) and a list of connections describing how these elements are wired together. A netlist can be platform independent, that is, it can target any architecture from any vendor. (e.g. Mentor LS tool). Many development environments provide additional support tools such as Register Transfer Level (RTL) viewers (graphical representations of the source code) and/or netlist viewers (graphical representation of how the source code will be implemented in fabric). The Electronic Design Interchange Format (EDIF) is a more widely accepted format.

Synthesis


Basic synthesis processInitial HDL description

(technology independent)

RTL level

Logic level

Gate level

Final HDL description(technology dependent

netlist)

Optimization

Optimization

Optimization

ASIC

PLD

Synthesisdirectives


Available Synthesis Tools

FPGA Express:Advantages: None, Our rst LEON synthesized only with it -:)Disadvantaegs: Buggy, slow, runs only on WindowsVendor: SynopsysStatus: Synopsys has discontinued it, no longer bundled with Xilinx tools

Xilinx Synthesis Tool (XST):Advantages: Bundled with Xilinx ISE, Can automatically infer XilinxFPGA components, runs on UNIX (Solaris and GNU/Linux)Disadvantaegs: Still buggy, Only supports Xilinx devicesVendor: XilinxStatus: Active support from Xilinx


Available Synthesis Tools

Leonardo Spectrum:Advantages: Supports large family of FPGA devices, Reliable, Canautomatically infer FPGA componentsDisadvantages: Runs on Solaris, Replaced by Precision-RTLVendor: Mentor GraphicsStatus: To be replaced soon

Synplify:Advantages: Most trusted in industry, Support large family of FPGAdevices, Can automatically infer FPGA componentsDisadvantages: Some optimizers are still buggy (FPGA Compiler)Vendor: SynplicityStatus: Active support from Synplicity


Once the hardware design entry is completed (either using a schematic or HDL), you may want to simulate your design on a computer to gain confidence that it works correctly.Simulation requires a form of stimulus to provide to the inputs of the FPGA design, and then an FPGA simulator software can determine the corresponding FPGA outputs.There are 2 ways you can create the simulation stimulus:

Using an interactive waveform editor. Using a testbench.

A test bench is one or more modules that connect your design, the Unit-Under-Test (UUT), with internally generated stimulus or stimulus from a file to drive the inputs of the UUT and may collect and process the outputs of the UUT.

Simulation


Simulation

After each module is written, it should be simulated. Usually the low-level modes are relatively simple and the test benches quick and easy to write. Once simulated the designer has confidence to move to the next module so that when the lower-level modules are combined.As a general rule, design performance should NOT be determined using simulation.There are four primary locations for running simulation:

A. Behavioral Simulation – prior to synthesisB. Netlist Simulation – post-synthesisC. Post-Map SimulationD. Post-Implementation or Post-Place-and-Route Simulation


Simulation


Implementation is the process of converting one or more netlists into an FPGA-specific pattern. This process is broken down into three basic sub-steps: translation, mapping, and place-and-route.Translate: The job of the translator is to collect all of the netlists into one large netlist and verify that the constraints map to signals. Map: The traditional role of the mapper is to compare the resources specified in the single grand netlist produced by the translate stage against the resources in the targeted FPGA.Place and Route: Place-and-route (P&R) describes several processes where the netlist elements are physically places and mapped to the FPGA physical resources, to create a file that can be downloaded in the FPGA chip.

Implementation


Available Place and Route Tools

Xilinx ISE:Advantages: Vendor provided Place and Route tool, there is no other choiceDisadvantages: No point of comparisonVendor: XilinxStatus: Active support from Xilinx

Altera Quartus II:Advantages: Vendor provided Place and Route tool, there is no other choiceDisadvantages: No point of comparisonVendor: AlteraStatus: Active support from Altera


Bitstream Generation

The final step is converting the placed and routed design into a format that the FPGA will understand. Bit-streams can be generated so that they can be directly loaded into an FPGA (usually via JTAG8), or formatted for parallel or serial PROMs (Programmable Read-Only Memory).


Tools for synthesis and implementationof FPGAs


Synthesis Tool flow

HDL Designer

Synplify Pro Leonardo Spectrum

Design

Synthesis

ImplementationISE Project Navigator

VHDL code

Netlist

Bitstream

XST


Synthesis stages

High level synthesis

TechnologyTechnologyindependentindependent

TechnologyTechnologydependentdependent

Low level synthesis

CompileCompile MapMap Place & RoutePlace & Route ImplementImplement

- Code analysis- Derivation of main logic constructions- Technology independent optimization- Creation of “RTL View”

- Mapping of extracted logic structures to device primitives- Technology dependent optimization- Application of “synthesis constraints”-Netlist generation- Creation of “Technology View”

- Placement of generated netlist onto the device-Choosing best interconnect structure for the placed design-Application of “physical constraints”

- Bitstream generation- Burning device


Synthesis stages

High level synthesis High level synthesis Low level synthesis Low level synthesis

CompileCompile MapMap Place & RoutePlace & Route ImplementImplement

Synplify Pro

Leonardo Spectrum

Xilinx

Synthesis

Tools

TechnologyTechnologyindependentindependent

TechnologyTechnologydependentdependent

introduction to fpga synthesis tools

Engineering