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High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ. Ulm / Missing Link Electronics 2015-02-25 1 (c) MLEcorp.com We are a Silicon Valley based technology company with offices in Germany. We are partner of leading electronic device and solution providers and have been enabling key innovators in the automotive, industrial, test & measurement markets to build better Embedded Systems, faster. Our Mission is To develop and market technology solutions for Embedded Systems Realization via pre-validated IP and expert application support, and to combine off- the-shelf FPGA devices with Open-Source Software for dependable, configurable Embedded System platforms Our Expertise is I/O connectivity and acceleration of data communication protocols, additionally opening up FPGA technology for analog applications, and the integration and optimization of Open Source Linux and Android software stacks on modern extensible processing architectures.

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Page 1: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

High-Level-Synthesis for FPGA Implementation of Network Protocols

Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ. Ulm / Missing Link Electronics

2015-02-25 1 (c) MLEcorp.com

We are a Silicon Valley based technology company with offices in Germany. We are partner of leading electronic device and solution providers and have been enabling key innovators in the automotive, industrial, test & measurement markets to build better Embedded Systems, faster.

Our Mission is To develop and market technology solutions for Embedded Systems Realization via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open-Source Software for dependable, configurable Embedded System platforms

Our Expertise is I/O connectivity and acceleration of data communication protocols, additionally opening up FPGA technology for analog applications, and the integration and optimization of Open Source Linux and Android software stacks on modern extensible processing architectures.

Page 2: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Motivation: Network Processing for Embedded Systems

• 10 GigE will soon push from data center into embedded markets

Transporting 1 bit per second needs 1 Hz

• 1 GigE 1 CPU at 1 GHz

• 10 GigE 4 CPUs at 2.5 GHz

2015-02-25 2 (c) MLEcorp.com

Page 3: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Design Choices for Network Processing in SoC FPGAs

SoC FPGA as (yet) another computer

SOC FPGA has 4x more compute

With ¼ the power dissipation!

[http://www.xilinx.com/products/technology/dsp.html]

2015-02-25 3 (c) MLEcorp.com

Intel i7-4770

Xilinx Zynq 7045

Compute ~100 GFLOPS 5 GFLOPS (PS) 778 GFLOPS (PL)

TDP 84 W <20 W (typ)

Page 4: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Network Stack in RTL from Fraunhofer Heinrich-Hertz-Institute

• Brings full TCP/UDP/IP connectivity to FPGAs even when there is no CPU available. Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic.

2015-02-25 4 (c) MLEcorp.com

Page 5: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Network Protocol Acceleration Platform Architecture

Network protocol processing at application layer (ISO Layer 7) can more efficiently be implemented via a programming approach (in C or C++) than by digital circuit design (in VHDL or Verilog).

2015-02-25 5 (c) MLEcorp.com

Page 6: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

High-Level Synthesis Design Flow for SoC FPGA

• Input C/C++/SystemC into High-Level Synthesis to generate VHDL/Verilog code

2015-02-25 6 (c) MLEcorp.com

Page 7: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Working Principles of High-Level Synthesis

• Design automation runs scheduling and resource allocation to generate RTL code comprising data path plus state machines for control.

2015-02-25 7 (c) MLEcorp.com

Page 8: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Benefits of High-Level Synthesis

• Automatic performance optimization via parallelization at dataflow level

• Automatic interface synthesis and code generation for variety of real-life HW/SW connectivity

2015-02-25 8 (c) MLEcorp.com

Page 9: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Visualization and User Interaction in High-Level Synthesis Tool

2015-02-25 9 (c) MLEcorp.com

Page 10: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Design Example for Extending NPAP with High-Level Synthesis

• Network Time Protocol (NTP) Packet according to RFC5905

• Block diagram of the NTP Server implemented in Programmable Logic

2015-02-25 10 (c) MLEcorp.com

Page 11: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Implementation Example

• Implement the NTP server as an “IP core” using Vivado HLS

• The network processing stack, including the NTP server IP core, runs on Xilinx Zynq-7000 SoC

• Xilinx ZC706 evaluation kit connected via SFP+ with Intel 10GbE NIC inside PC

• PC runs NTP client application to query Zynq-implemented NTP server

2015-02-25 11 (c) MLEcorp.com

Page 12: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Conclusion and References

• Significant productivity increase for protocol oriented or dataflow based design blocks.

• Easy to adopt: Known languages C/C++ combined with known tool chain.

• Add this to your bag of tricks!

• UG998 - Introduction to FPGA Design Using High-Level Synthesis

• UG871 - Vivado Design Suite Tutorial: High-Level Synthesis

• XAPP1209 - Designing Protocol Processing Systems with Vivado High-Level Synthesis

• UG949 - UltraFast Design Methodology Guide for the Vivado Design Suite

2015-02-25 12 (c) MLEcorp.com

Page 13: High-Level-Synthesis for FPGA Implementation of Network ... · High-Level-Synthesis for FPGA Implementation of Network Protocols Simon Lever, Univ. Ulm Dr. Endric Schubert, Univ

Contact Information

Simon Lever

[email protected]

[email protected]

Dr. Endric Schubert

[email protected] [email protected] Phone US: +1 (408) 320-6139 Phone DE: +49 (731) 141149-66

2015-02-25 13 (c) MLEcorp.com

mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]
mailto:[email protected]

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