FPGA Two Day Advanced FPGA Workshop

Instructors

1

Craig KiefDeputy Director, COSMIAC

craig.kief@cosmiac.org

Karl HenryInstructor, JF Drake State

Karl.Henry@DrakeState.edu

Bassam MatarInstructor, Chandler-Gilbert

b.matar@cgcmail.maricopa.edu

Brian ZufeltEngineer, COSMIAC

Brian.zufelt@cosmiac.org

Ui LuuInstructor, Glendale

ui.luu@gcmail.maricopa.edu

Pete LomeliInstructor, Central ArizonaPete.Lomeli@centralaz.edu

Introductions

• Who are you?

• Where are you from?

• What do you want to learn from this?

• Where are the objectives?

Labs we will cover

Spin upCounterTestbenchFSMSeq DetIP Cores

Why we are here again

Method: Immersive hands-on design for every student

Students learn more, faster, and better with unrestricted access to design tools…

…overall learning improves when applied design skills taught early;

…overall performance improves when design skills used frequently;

…and they like it*

*results published in 2008 and 2009 ASEE proceedings

I never teach my pupils; I only attempt to provide the conditions in which they can learn. Albert Einstein

Technology keeps moving forward faster – get on the train or be left behind

In a meeting the first week in June, Xilinx announced the following:

• The new Virtex 7 devices use approximately 20 watts

• They are actually four chips on a single chip connected with an interposer

• The contain approximately 6.8 billion transistors

Low-cost kits and Free CAD toolsfor every engineering student

Terasic DE0Altera Cyclone III

$79

Terasic DE1Altera Cyclone II

$125

Digilent Basys2Xilinx Spartan 3E

$59

Digilent Nexys2Xilinx Spartan 3E

$99

No Lab Required! Students work on real designs at a time and place of their choosing

FPGA’s Across the Curriculum

Please interrupt and ask questions

OverviewAll Xilinx FPGAs contain the same basic resources

Logic Resources Slices (grouped into CLBs)

Contain combinatorial logic and register resources Memory Multipliers

Interconnect Resources Programmable interconnect IOBs

Interface between the FPGA and the outside worldOther resources

Global clock buffers Boundary scan logic

What makes up an FPGA?

Groups of Slices make up a Complex Logic Block (CLB)

Each slice has four outputsTwo registered outputs, two non-registered outputs

Slice 0

LUTLUT CarryCarry

LUTLUT CarryCarry D QCE

PRE

CLR

DQCE

PRE

CLR

Simplified Slice Structure

Spartan-3E Architecture

CLB

Slice

DESIGN

Hardware Descriptive Languages (HDL) VHDL VERILOG

C++SYSGENSchematic CaptureEDKIP Cores

Limitless Tools

SYNTHESIS

Many files in – one file out

One File = EDIF

Syntax Checking

Less Tool Choices

IMPLEMENTATION

PLACE AND ROUTE

Place Logic onto the CLBs

Route IOB CLB IOB

UCF EDIF .BIT

ONE TOOL

PROGRAM

JTAG

PROGRAM

FPGA

PROM

ADEPT vs JTAG Chain

BEHAVIORAL SIMULATION TIMING SIMULATION

Design

How are FPGA projects Designed?

There are many different methodolgies for programming (or designing) with FPGAsHardware Descriptive Language (HDL)

VHDL Verilog

Schematic CaptureC CodeEDKSystem Generator

VHDL Code

The title of the article is "Analysis of the programmable logic usage and assurace survey results“ revision 10.1, sept 25,2002Glenn research center, Cleveland, Ohio.

Quote:It is a serious mistake to equate VHDL programming to software. At best it is firmware, but for the most part there isn't a good name for programming FPGA logic. In a high performance design like ours, the minute you forget that you are designing hardware and think you are writing software, you fail.

VHDL Code

Forest Level View

Architecture Declaration

VHDL Recap and Objects

Variables

Not limitless Operators

Available Operators

Picking off bits

Data types, operators and conversion

CASE STATEMENT

SELECTED SIGNAL ASSIGNMENT

00011011

SELECT X WHEN “00”,Y WHEN “01”,Z WHEN “10”,Z WHEN “OTHERS”;

* USED WHEN NO PRIORITY EQUIVALENT TO CASE STATEMENT (get code)

IF STATEMENT

CONDITIONAL SIGNAL ASSIGNMENT PROCESS (X, Y, Z, A, B) SENSITIVITY LIST. ANYTHING READ MUST BE HERE NOTHING HERE IS EVER

ON LEFT SIDE OF ASSIGNMENT – Everything on Right hand side of assignment is read

01

IF B = ‘1’ THENOUT <= Z

ELSIF A = ‘1’OUT <= Y

ELSEOUT <= X

END IFEND

PROCESS* PRIORITY EXISTS

X

Y

01

OUT

ZA

B

Assignment Operators

<= Used to assign a value to a SIGNAL a <= ‘1’;

:= Used to assign an value to a VARIABLE, CONSTANT, or GENERIC. Used also for establishing initial values

constant N: integer:=18;

=> Used to assign values to individual vector elements or with OTHERS

display_out : display_controllerport map(clk => clk, reset => reset,

• q_reg <= (others=>'0');

RULES

DON’T USE PROCESS IF DON’T HAVE TO – Simple, concurrent and selected signal assignments can be done outside of a process. Danger of using a process is you might get a inferred latch (unwanted clock cycle)

MULTIPLE ASSIGNMENTS TO SAME SIGNAL, LAST ONE HOLDS

FOR EVERY OUTPUT SIGNAL THAT CAN BE ASSIGNED, ALL POSSIBLE CONDITIONS MUST BE ADDRESSED– Always assign default values at the top of the block before case and if statements

ALL INPUT SIGNALS READ MUST BE IN THE SENSITIVITY LIST FOR COMBINATIONAL LOGICFOR SEQUENTIAL USE CLK/RESET

I wish to help all of you to begin teaching FPGAs

Start the Learning

The key from this workshop is to learn what you need to know to successfully teach with FPGAs

Get Started!

Create a 2 input AND gate! Create the VHDL,

Testbench, UCF and download it

Steps:

1. Start ISE

2. New Source – VHDL Module

3. Use Wizard to do I/O

4. New Source – Create UCF for pin assignment

5. New Source – VHDL Testbench

6. Simulate

7. Program FPGA

Things to discuss before the labs

Slow clockUsing it, changing it for simulations

DebouncingAlex material

ISE 7 vs 14

Labs we will cover

Spin upCounterTestbenchFSMSeq DetIP Cores

Lab 6 - CountersDownload ISE 14.1 version of Lab 6 from

http://cosmiac.org/Projects_FPGA.htmlCreate New ProjectAdd Source Files:

counter.vhd display_controller.vhd counter_TB.vhd counter4.ucf

Download and Review FPGA Reference Manual Change clk pin assignment as needed Change UCF pin assignments as needed

Review vhd and ucf codeReview Testbench

We are using a Nexys 2, Spartan-3 for this class. We will need to change the pin assignments using the diagram.

Labs we will cover

Spin upCounterTestbenchFSMSeq DetIP Cores

Autogenerated Test Benches

Build a module test a module, …., build a system of modules and test the systemExcellent job for technician or junior engineerCreating the framework of the test bench is easy and painlessNeed to have directory of files and test benches and need to

be able to quickly pick them out and mate the source file to its test file

Labs we will cover

Spin upCounterTestbenchFSMSeq DetIP Cores

LAB 10Finite State Machine (FSM)

Ui Luu

Glendale Community CollegeBassam Matar

Chandler-Gilbert Community College

Moore vs. Mealy State Machines

Learning Objectives Create a top-level HDL structure

Write VHDL code to describe a Finite State Machine

Apply VHDL codes previously developed in workshop #1 (source codes are provided in this lab template):

(TIMER_DISPLAY.vhd, MEM16.vhd, SECURITY.ucf module) for timer display

Implement INDICATORS.vhd (to provide visual feedback for NEXYS2 on board switches & buttons)

Verify system operations using NEXYS2 evaluation board

Security Monitor System I/O

SECURITY

ARM

FRONT_DOOR

REAR_DOOR

WINDOW

SIREN

Figure 1. Security System I/O

ARM INDICATOR

FRONT_DOOR INDICATOR

REAR_DOOR INDICATOR

WINDOW INDICATOR

Security System State Diagram

DISARMED

SIREN = ‘0’

ARMED

SIREN = ‘0’

WAIT_DELAY (7 s)

SIREN = ‘0’

ALARM

SIREN = ‘1’

ARM = ‘1’

ARM = ‘0’

SENSORS /= “000”

ARM = ‘0’

COUNT_DONE = ‘1’

ARM = ‘0’

ARM = ‘0’

Figure 2. SECURITY SYSTEM STATE DIAGRAM

CLK ANODE_CONTROL(3:0)

ADDR(3:0)

CLK_DIVRUN_TIMER

TIMER_DISPLAY

CLK

FSM

CLK

CLK_DIV

ARM

FRONT_DOOR

REAR_DOOR

WINDOW

RUN_TIMER

SIREN

INDICATORS

ARM

FRONT_DOOR

REAR_DOOR

WINDOW

ARM (SW0)

FRONT_DOOR (Button 3)

REAR_DOOR (Button 2)

WINDOW (Button 1)

ARM_SIG

FRONT_DOOR_SIG

REAR_DOOR_SIG

WINDOW_SIG

ARM_IND

FRONT_DOOR_IND

REAR_DOOR_IND

WINDOW_IND

LED 0

LED3

LED2

LED1

ADDR_BUS(3:0)ADDR(3:0) DATA(7:0) CATHODE(7:0)

ANODE_CONTROL(3:0)

7-Segment LEDs

MEM16

Security State Machine / System Block Diagram

7/25/2011-REVAUi Luu

SIRENLED 7

CLK_DIV_SIG

RUN_SIG

Always start with a block diagram or dry erase board before you start to write your VHDL

TIMER_DISPLAY Module

TIMER_DISPLAY module objectives:

Provides 1 second CLK_DIV signal to Finite State Machine

Provides control signals to display timer using NEXYS2 onboard 7-segment LED display

CLK_DIV signal Functional Requirement:

Provides 1 second CLK_DIV signal to Finite State Machine

Code Implementation:

process (CLK,REG) beginif rising_edge(CLK) then

REG <= REG + 1; CLK_DIV_INT<='0';end if;

if REG = X"2FAF080" then -- For 1 Hz use X"2FAF080" = 50,000,000 (Decimal)-- 50 MHz / 50,000,000 = 1 HzCLK_DIV_INT<='1';REG<=X"0000000"; --would be cleaner with “others”

end if;

end process;

TIMER_DISPLAY Functional Description

When RUN_TIMER (from FSM) = 1: Timer counts up at 1 second rate Display the timer count at 7-Segment LED

When RUN_TIMER = 0: Timer resets to 0

TIMER_DISPLAY Implementation(Note: This implementation was covered in Workshop May,2011)

process (CLK,CLK_DIV_INT,RUN_TIMER)begin

if RUN_TIMER = '0' thenQ_INT <= (others => '0');

elsif rising_edge(CLK) thenif (CLK_DIV_INT='1') then -- Note: CLK_DIV_INT provides 1-second

clock

Q_INT <= Q_INT + '1';end if;

end if;end process;

-- Outputs:ADDR(3 downto 0) <= Q_INT (3 downto 0);ANODE_CONTROL <= "1110"; -- Enable 1st digit only, active LowCLK_DIV <=CLK_DIV_INT;

Review NEXYS2 I/O Device(Ref. Nexys2_m.pdf)

Note the difference

MEM16.vhd entity MEM16 is Port ( ADDR : in STD_LOGIC_VECTOR (3 downto 0); DATA : out STD_LOGIC_VECTOR (7 downto 0));end MEM16;

architecture Behavioral of MEM16 istype ROM_ARRAY is array (0 to 15) of std_logic_vector(7 downto 0);constant MY_ROM :ROM_ARRAY :=(

-- Cathode Control for 7-SEGMENT LED Digit (0-F):0 => X"03", --0 note: Cathode control is active Low1 => X"9F", --1 2 => X"25", --23 => X"0D", --34 => X"99", --45 => X"49", --56 => X"41", --67 => X"1F", --78 => X"01", --89 => X"09", --910 => X"11", --A11 => X"C1", --B12 => X"63", --C13 => X"85", --D14 => X"61", --E15 => X"71" --F

);begin

DATA <= MY_ROM(conv_integer(ADDR));end Behavioral;

b = 0

DP = 1

g = 0

a = 1

f = 0

d = 1

c = 0e = 1

4 = 10011001

FSM / IO port assignments

(Reference: System Block Diagram) entity FSM is

Port ( CLK : in STD_LOGIC; CLK_DIV:in STD_LOGIC; ARM : in STD_LOGIC; FRONT_DOOR : in STD_LOGIC; REAR_DOOR : in STD_LOGIC; WINDOW : in STD_LOGIC;

RUN_TIMER:out STD_LOGIC; SIREN : out STD_LOGIC);

end FSM;

Type & Signal names Declarations

type SECURITY_STATE is (ARMED,DISARMED,WAIT_DELAY, ALARM);

signal CURR_STATE,NEXT_STATE: SECURITY_STATE;

signal START_COUNT,COUNT_DONE: std_logic;

signal SENSORS:std_logic_vector (2 downto 0); --combine inputs

signal TIMER_CNTR: std_logic_vector (2 downto 0) := (others => '0');

FSM / Reading Sensors & SYNC Process

SENSORS <= FRONT_DOOR & REAR_DOOR & WINDOW;

SYNC: process (CLK,ARM) begin

if ARM = '0' thenCURR_STATE <= DISARMED;

elsif rising_edge (CLK) thenCURR_STATE <= NEXT_STATE;

end if;end process SYNC;

& = concatenation

New State each clock cycle

Implement Security System State Diagram

(Figure 2)

STATE_MACHINE: process (CURR_STATE,SENSORS,ARM,COUNT_DONE)begin

START_COUNT <= '0'; -- establish default

case (CURR_STATE) iswhen DISARMED =>

if ARM = '1' thenNEXT_STATE <= ARMED;else NEXT_STATE <= DISARMED;end if;-- Output:SIREN <= '0';RUN_TIMER <= '0';

when ARMED =>if (SENSORS /= "000") thenNEXT_STATE <= WAIT_DELAY;else NEXT_STATE <= ARMED;end if;-- Output:SIREN <= '0';RUN_TIMER <= '0';

when WAIT_DELAY =>START_COUNT <= '1';if (COUNT_DONE = '1') thenNEXT_STATE <= ALARM;elsif (ARM ='0') then

NEXT_STATE <= DISARMED;else NEXT_STATE <= WAIT_DELAY;end if;-- Output:SIREN <= '0';RUN_TIMER <= '1';

when ALARM =>if (ARM = '0') thenNEXT_STATE <= DISARMED;else NEXT_STATE <= ALARM;end if;-- Output:SIREN <= '1';RUN_TIMER <= '0';

end case;end process STATE_MACHINE;

Four States

DELAY_TIMER Process

DELAY_TIMER: process(CLK_DIV,CURR_STATE,START_COUNT,TIMER_CNTR)

beginCOUNT_DONE <= '0'; -- default valueif (rising_edge (CLK_DIV) and (START_COUNT = '1')) then TIMER_CNTR <= TIMER_CNTR + 1;end if;

-- *** Note: START_COUNT is set to 1 by the STATE_MACHINE when CURR_STATE = WAIT_DELAY

if (CURR_STATE/=WAIT_DELAY) then -- Note: /= means NOT equal toTIMER_CNTR <= "000";

end if;

if (TIMER_CNTR = "111") then -- Note: this timer times out at 7 seconds just for convenience

COUNT_DONE <= '1';end if;

end process DELAY_TIMER;

INDICATORS.vhd (provides visual feedback for NEXYS2 on board switches and buttons)

entity INDICATORS is Port ( ARM : in STD_LOGIC; FRONT_DOOR : in STD_LOGIC; REAR_DOOR : in STD_LOGIC; WINDOW : in STD_LOGIC;

ARM_SIG : out STD_LOGIC; FRONT_DOOR_SIG : out STD_LOGIC; REAR_DOOR_SIG : out STD_LOGIC; WINDOW_SIG : out STD_LOGIC);end INDICATORS;

architecture Behavioral of INDICATORS is

begin

ARM_SIG<=ARM;FRONT_DOOR_SIG <= FRONT_DOOR; REAR_DOOR_SIG <= REAR_DOOR; WINDOW_SIG <= WINDOW;

end Behavioral;

SECURITY.ucf (I/O assignments for NEXYS2-1200)

# SECURITY.ucf# 7/6/2011: Operation verified with NEXYS2-1200

NET "CLK" LOC = B8;NET "ARM" LOC = G18; # Switch 0

NET "FRONT_DOOR" LOC = H13; # Button 3NET "REAR_DOOR" LOC = E18; # Button 2NET "WINDOW" LOC = D18; # Button 1

NET "ARM_IND" LOC = J14; #LED 0

NET "FRONT_DOOR_IND" LOC = K14; #LED3NET "REAR_DOOR_IND" LOC = K15; #LED2NET "WINDOW_IND" LOC = J15; #LED1

NET "CATHODE[0]" LOC = C17; #DPNET "CATHODE[1]" LOC = H14; #CGNET "CATHODE[2]" LOC = J17; #CFNET "CATHODE[3]" LOC = G14; #CENET "CATHODE[4]" LOC = D16; #CDNET "CATHODE[5]" LOC = D17; #CCNET "CATHODE[6]" LOC = F18; #CBNET "CATHODE[7]" LOC = L18; #CA

NET "ANODE_CONTROL[0]" LOC = F17;NET "ANODE_CONTROL[1]" LOC = H17;NET "ANODE_CONTROL[2]" LOC = C18;NET "ANODE_CONTROL[3]" LOC = F15;

NET "SIREN" LOC = P4; #LED7 P4 for NEXYS2-1200 (R4 for NEXYS2-500 series)

Hands On Practice(Work in Team of 2)

Download / Copy

“VHDL-SecurityStateMachine-Starter(NEXYS2-1200)” project folder to your desktop

Follow Lab 10 Finite State Machine (FSM) Instructions

Verify the Security State Machine operates as prescribed

Demonstrate to your lab coordinator

Sample Solution

For reference, Sample solution is available at project Folder

“VHDL-SecurityStateMachine-SampleSolution(NEXYS2-1200)”

Labs we will cover

Spin upCounterTestbenchFSMSeq DetIP Cores

Sequence Detectors

Sequence Detectors

Practical applicationsFacial recognitionSearching for correct patternsDSP

Labs we will cover

Spin upCounterTestbenchFSMSeq DetIP Cores

IP CoresWhat are Cores?CoreGen Wizard

IP Cores

IP Cores Datasheets

IP Cores Lessons Learned

Don’t assume you know the way the core will workBuild a project with only the core in it and test it alone until

you are sure you know how it worksIf you can’t see any of the cores:

Setting environment variable XIL_CG_LOAD_ALL_FAMILIES=true Especially for 14.4.

Other “STUFF”

Obtaining, licensing and service contract with Xilinx

If you decide to go with Xilinx, we can help you the most (with currently available resources)Register with XUPGet softwarePay annual feePut one person in charge

Synthesizing Designs

Double-click to SynthesizeSynthesis Processes and Analysis

• Access report• View Schematics (RTL or Technology)• Check syntax• Generate Post-Synthesis Simulation Model

Generate a netlist file using XST (Xilinx Synthesis Technology) Highlight HDL

Sources

1

2

ImplementationConsists of three phases

Translate: Merge multiple design files into a single netlist

Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs)

Place & Route: Place components onto the chip, connect the components, and extract timing data into reports

Access Xilinx reports and tools at each phaseTiming Analyzer, Floorplanner, FPGA

Editor, XPower

Translate

Map

Place & Route

Implement

. . .

.

.

.

Netlist GeneratedFrom Synthesis

.

.

.

SynthesisSchematicCapture

Simulation0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1

Design Flow

libraries

netlist

HDL

test vectors

Translate

Fitting/Place & Route

Implementation

Specification

Verification

Gates of the design ...

... are placed ... ... and routed

Device Implementation Place & Route

Simulations

Configuring FPGAsConfigure FPGAs from computer

Use iMPACT to download bitstream from computer to FPGA via Xilinx download cable (ie. Platform USB)

Configure FPGAs from External Memory Xilinx Platform Flash

Use iMPACT to generate PROM file and download to PROM using Xilinx download cable

Generic Parallel PROM Use iMPACT (or in our case Adept) to generate

PROM file - no support for programming Compact Flash (Xilinx System ACE required)

Use iMPACT to generate SysACE file - no support for programming

Double-click to generate .bit

2

Highlight source file

1

Double-click to invoke iMPACT programming tools

3

JTAG – IEEE StandardSix Signals

TMS TCK TDI TDO Pwr Gnd

Demo Impact

Webpack

This is the really great benefit to students. Xilinx makes a free version of their ISE software. This means that students can do entire projects at home and only come to the lab to demo.

http://www.xilinx.com/ise/logic_design_prod/webpack.htm

Altera has a similar product

Webpack vs Full Version

Webpack

Plan AheadIn the near future Xilinx ISE will transition from the

traditional Project Navigator to Plan Ahead.Easier integration of various design types

PlanAheadVery similar to project navigator

EDKVery similar to project navigator

Default Locations for SW

When you are setting up the software, regardless of if it is at the lab or at home, only install the software at the default locations.

LicensingNode Lock (Ethernet versus Hard Drive Serial Number)Server LicensingStudent versus Lab

Digilent (cont.)

Clint’s boards

Educational Materials Available

Clint’s web site www.eecs.wsu.edu/~ee214Digilent website www.digilentinc.comOur XUP site www.ece.unm.edu/vhdlXUP sitewww.cosmiac.orgQuick start tutorials – launch within ISEWhat we are developing!

Educational Materials Availablehttp://www.digilentinc.com/classroom/realdigital/

Donated SW and HW

SoftwareRegister with XUPMention working with usDon’t chase releases

Hardware10 boards

Beginners and Advanced WorkshopsWe offer a series of free two-day workshops for instructors and professors to allow them to be able to learn the basics of establishing FPGA programs at their schools

Coming in the Fall of 2012 – Beginners Microcontroller workshops!

CollaborationWe do collaborations very well

ATE proposals due October 2013

Help with Writing Proposalswww.teachingtechnicians.org

Hi Craig,    By cc of this message, I am asking Charlotte Forrest (Mentor-Connect Project Manager) to provide you with information that can be shared at your next ATE workshop.  Thanks so much for asking!   We will start work with a new cohort of potential grantees in fall 2013.  We are currently working with a cohort of 20 colleges that were selected in fall 2012.   The cycle starts with an orientation webinar in September and is followed by an application process.  Those selected receive considerable help in preparing a successful proposal and are paired with an experience ATE mentor for all of the months leading up to their proposal submission.  The program serves those who have not previously received NSF ATE funding that was awarded directly to their institution within the past 10 years.  If they have been a partner on a grant awarded to another institution, they are eligible.  If their institution is a branch of a larger institution but there is a chief academic officer for their branch campus, they are eligible even if another branch of the organization has been a grantee (for example, the Ivy Tech system in Indiana where college locations within the system have their own administration).  Also, this opportunity is for associate degree granting institutions (primarily two-year technical and community colleges).   Again, many thanks for contacting me and for helping spread the word about this opportunity.Elaine

Deploying CurriculumWebsite: http://cosmiac.org/FPGA.html

Conclusions

Painful survey

We need your help in statistics. We will be contacting you!