fpga synthesis & prototyping
TRANSCRIPT
IP Deliverables (course topics)Write function spec.
Write technical spec.
IP Prototyping System
IP Deliverables DIP
Course Contents FPGA Device Altera, Xilinx (pp. 5~39)
FPGA Design Flow & Synthesis ISE, Quartus II (pp. 40~83)
DIP Rapid Prototyping Platform (pp. 84~104)
DIP Prototype System Measurement (pp.105~141)
Design Example (pp.142~167)
FPGA Device
FPGA Design Flow & SynthesisFPGA Design Flow & SynthesisFPGA Design Flow & Synthesis
DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform
DIP Prototype System Measurement DIP Prototype System Measurement DIP Prototype System Measurement
Design ExampleDesign ExampleDesign Example
PLD Complexity Drives Design Methodology Changes PLD Complexity Drives Design Methodology Changes
Increasing Time-to-Market Pressures Drive Change
SOPC Design SOPCSOPC DesignDesign
Altera Device FamiliesAltera Device Families Programmable Logic Families
High & Medium Density FPGAs Stratix, APEX II, APEX 20K, & FLEX 10K
Low-Cost FPGAs Cyclone & ACEX 1K
FPGAs With Clock Data Recovery Mercury & Stratix GX
CPLDs MAX 7000 & MAX 3000
Embedded Processor Solutions NiosTM, ExcaliburTM
Configuration Devices EPC
APEX 20K Family
Industry’s first MultiCore Architecture – Look-up table (LUT) logic – Product-term logic – Embedded memory
Fabricated on SRAM Process – 2.5-V, 0.25/0.22-Micron Process – 1.8-V, 0.18-Micron Process
DIP
APEX MultiCore Architecture
Facilitates Efficient IP Integration – Look-up Table Core – Product-Term Core – Memory Core
DIP
Enhanced FastTrack Interconnect
DIP
APEX 20K Device Features
The Stratix Device FamilyThe Stratix Device Family Feature
Process
Density
Performance
Clock Management
I/O Capabilities
Average 40% Increase
TriMatrix™ Memory Incorporating 3 Block Sizes for Maximum Bandwidth & Capacity
Embedded DSP Blocks for Complex Arithmetic Functions
Advanced System Clock Control for On- & Off-Chip Clock Needs
840-Mbps Differential I/O Signaling, High-Speed Interface Support, External Memory Interfaces & On-Chip Termination Technology
DIP
Stratix Architecture OverviewStratix Architecture Overview
DSP BlocksLogic Array Blocks (LABs)
MegaRAM™ Blocks
Advanced I/O CapabilitiesAdvanced I/O Capabilities High-Speed Interface Protocols − 10-Gigabit Ethernet XSBI − POS-PHY Level 4 − HyperTransport − RapidIO (Parallel)
High-Speed Interface Protocols − 10-Gigabit Ethernet XSBI − POS-PHY Level 4 − HyperTransport − RapidIO (Parallel)
Differential & Single- Ended I/O Standards − LVDS, LVPECL,
HyperTransport, PCML − HSTL, SSTL − PCI, PCI-X, Compact PCI
Differential & Single- Ended I/O Standards − LVDS, LVPECL,
HyperTransport, PCML − HSTL, SSTL − PCI, PCI-X, Compact PCI
Terminator Technology − On-Chip Differential
Termination − On-Chip Series & Parallel
Matching
External Memory Device Interfaces − DDR SDRAM & SRAM − SDR SDRAM − QDR & QDRII SRAM − ZBT SRAM − DDR FCRAM
External Memory Device Interfaces − DDR SDRAM & SRAM − SDR SDRAM − QDR & QDRII SRAM − ZBT SRAM − DDR FCRAM
DIP
TriMatrix Memory Structure
DirectDrive™ Technology
Each Interconnect Line Driven by Single Source – Consistent Access to Routing – Eliminates Congestion
Uniform Routing Resources Across Device – Ensures Blocks Can be Moved within or between Designs
DIP
DSP Block
DSP Block Modes
The Stratix Device FamilyThe Stratix Device Family
94
194
224
295
384
574
767
1,118
10,570
18,460
25,660
32,470
41,250
57,120
79,040
114,140
60
82
138
171
183
292
364
520
1
2
2
4
4
6
9
12
920,448
1,669,248
1,944,576
3,317,184
3,423,744
5,215,104
7,427,520
10,118,016
6
10
10
12
14
18
22
28
July
Q3
June
Q4
Q3
Q4
July
2003
Package Offerings & User I/OPackage Offerings & User I/O
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
EP1S120
341
422
469
Nios Flexibility & ScalabilityNios Flexibility & Scalability Network Processor
System
Nios System Architecture
On-Chip Debug Core
Off-Chip Software Trace
ARM-Based Excalibur Embedded Processor ARM-Based Excalibur Embedded Processor
PLD Area for Customer
ARM922T Core
Single-Port RAM
Dual-Port RAM
200-MHz ARM922T™ Processor Up to 3.3 Mbits of Memory Up to 1M Gates of Programmable Logic
DIP
Embedded Processor PLD ArchitectureEmbedded Processor PLD Architecture
PLL
Timer
UART
DPRAM
EPXA1
EPXA4
EPXA10
LEs 4,160 ESB (Bytes) 6.5K
LEs 16,400 ESB (Bytes) 26K
LEs 38,400 ESB (Bytes) 40K
Embedded Stripe
Introduction to Xilinx Product • FPGA : Spartan/XL, Spartan II,Spartan-IIE, • Virtex, VirtexE,Virtex II,Virtex-II Pro • CPLD : XC9500/XL, CoolRunner • Software :Foundation4.2i, ISE Alliance4.2i, • ISE 4.2 • Core : IP, LogiCore, Alliance Core •Technical Support : support.xilinx.com, FAEs
DIP
Density, Performance, Cores & Memory
DIP
Spartan-II Architecture Delay Lock Loop (DLL)
DLL
De-skew clock
Chip to Backplane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL+, AGP
Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT
Chip to Chip LVTTL, LVCMOS
SelectI/OTM
Technology
Block Memory
Simplified CLB Structure
3 Level Memory Hierarchy
Virtex-II Pro Platform FPGA
MGT
MGT
MGT
MGT
Fabric
• •
•
• IP-Immersion™ Fabric • ActiveInterconnect™ • 18Kb Dual-Port RAM • Xtreme™ Multipliers • 16 Global Clock Domains
•
•
PowerPC 405 I-Side On-Chip Memory (OCM) 5-stage data path pipeline
16KB D and I Caches Embedded Memory Management Unit Execution Unit
Multiply / divide unit 32 x 32-bit GPR
Dedicated on-chip memory interfaces Timers: PIT, FIT, Watchdog Debug and trace support Performance:
450 DMIPS at 300 MHz 0.9mW/MHz Typical Power
D-Side On-Chip Memory (OCM)
Fetch & Decode
Timers and
Debug Logic
Pr oc
es so
Virtex ®
-II Family 12 Devices, 10 Packages, 37 combinations
Virtex-II XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V Part Number 40 80 250 500 1000 1500 2000 3000 4000 6000 8000 10000 LUTs + FFs 512 1,024 3,072 6,144 10,240 15,360 21,504 28,672 46,080 67,584 93,184 122,880 BRAM (Kb) 72 144 432 576 720 864 1,008 1,728 2,160 2,592 1,024 3,456 Multipliers 4 8 24 32 40 48 56 96 120 144 168 192 DCM Units 4 4 8 8 8 8 8 12 12 12 12 12 CS144 88 92 92 FG256 88 120 172 172 172 FG456 200 264 324 FG676 392 456 484 FF896 432 528 624 FF1152 720 824 824 824 824 FF1517 912 1,104 1,108 1,108 BG575 328 392 408 BG728 456 516 BF957 624 684 684 684 684 684
DIP
XC9500XL Overview
compatible levels with 5.0/2.5V
High fMAX = 200 MHz Fast tPD = 4 nsec Best ISP/JTAG support Best pin-locking Advanced packaging
DIP
Technology
0.35um feature-size (0.25um Leff) 4 layers of metal
Superior reliability Reprogramming endurance = 10,000 Charge retention = 20 years
Fast programming characteristics
High Level Architecture
XC9500XL Family 9536XL 9572XL 95144XL 95288XL
Macrocells 36 72 144 288
Usable Gates 800 1600 3200 6400
tPD (ns) 4 5 5 6
fMAX (MHz) 200 178 178 151
Packages QFP
40K Spartan-XL
ATM ATM IMA IMA
Cable Modem Ethernet Ethernet
250k unit
DIP
Spartan-II Family Overview Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Logic Cells 432 972 1728 2700 3888 5292 Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344 Block RAM Qty. 4 6 8 10 12 14 Max. User I/Os 86 132 176 196 260 284 Package VQ100 VQ100
CS144 CS144 TQ144 TQ144 TQ144 TQ144
PQ208 PQ208 PQ208 PQ208 PQ208 FG256 FG256 FG256 FG256
FG456 FG456 FG456
FPGA DeviceFPGA DeviceFPGA Device
FPGA Design Flow & Synthesis
DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform
DIP Prototype System Measurement DIP Prototype System Measurement DIP Prototype System Measurement
Design ExampleDesign ExampleDesign Example
Function Sim
Design Entry
Programming & Debug
Placement & Routing
XilinxXilinx ISEISE
ISE Design Flows
Project Navigator
Creating New Projects
Adding Source Files
Creating HDL Source
HDL Wizard
HDL Wizard
Confirm information
Setting Implementation Option
Setting Synthesis Options
Accessing Advanced Options
Initiating a Design Flow
Accessing Reports
Static Timing Report
Proactive Timing Closure
Xilinx Synthesis Technology
HDL Bencher
Simulating with Testbench Waveforms
Simulating with Testbench Waveforms
ModelSim HDL Simulator
Using I/O Buffers
Configuration Download
Altera Quartus II
Design Methodologies
Quartus supports three common design methodologies: Top-down
Create a top-level of the design first, and then break down the design into lower-level design blocks.
Bottom-up Begin by creating the lower-level design blocks first and then stitch together the design at the top-level.
Middle-out Start in-between Top-down and Bottom-up design methodologies
DIP
PLD Design Flow(1)
PLD Design Flow(2)
Design Entry Multiple design entry methods
Quartus Block/Schematic Editor Text Editor
AHDL, VHDL, Verilog Memory Editor
Hex, Mif Third party EDA tools
EDIF HDL VQM
Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry
DIP
Design Entry Files Quartus
.bdf
.gdf
Top-level design files can be .bdf, .tdf, .vhd, .vhdl, .v, .vlg, .edif or .edf
.bsf .vhd
Block File
Symbol File
Text File
Text File
Exemplar, Synopsys, Synplicity, etc...
Main Toolbar and Modes
New Project Wizard
What is the name of this project
What is the name of the top-level design entitiy in your project
DIP
New Project Wizard
Set Chips & Devices
Set User Libraries
Compiler
Show the section of compiler
Compiler Message
summary
Timing Analysis Features
•Quartus II has built in static timing analysis Single
•clock timing analysis – fmax (maximum clock frequency) – Tsu, Th, Tco (setup time, hold time, clock-to-out
time) – Optional system fmax reporting
• Multi-clock analysis – Allows analysis of multiple synchronous clocks – Slack analysis is used
DIP
Timing Analysis
fmax
DIP
Locate Delay Path in Floorplan
DIP
Download
Make sure Type is “ByteBlasterMV”
Make sure is “JTAG”
Download
DIP
FPGA DeviceFPGA DeviceFPGA Device
FPGA Design Flow & SynthesisFPGA Design Flow & SynthesisFPGA Design Flow & Synthesis
DIP Rapid Prototyping Platform
DIP Prototype System Measurement DIP Prototype System Measurement DIP Prototype System Measurement
Design ExampleDesign ExampleDesign Example
IP Rapid Prototype Platform
SRAMFlashPIO_buttons
uart
seven_segment
EPXA10 Development Board (Altera)EPXA10 Development Board (Altera)
POWER BOOT_FLASH
EPXA10 Development Board FeaturesEPXA10 Development Board Features
Platform for Device Evaluation & Application Development Memory Support 1. SDR SDRAM: 256 Mbytes 2. Flash: 16 Mbytes
Flexible Clocking 50-MHz Embedded Stripe Clock
External Clock Generator Can Be Used Dedicated Stripe PLLs for Frequency Synthesis
PLD Clocks Dedicated Crystals for Each of Four PLD PLLs
Application Support Two UARTs ByteBlasterMV™ JTAG Connector Multi-ICE & Trace Port Connectors Ethernet PHY
DIP
EPXA10 Development Board FeaturesEPXA10 Development Board Features
PCI Two 3.3-V 33-MHz PCI Connectors Provided for Off-the-Shelf Applications
User Interface 1. Eight LEDs 2. Four Push-Buttons 3. Nine-Position DIP Switch
Power Supply 3.3-Volt DC Supply
1.8-V Generated 1.25-V Generated for VREF & VTT
ATX Power Supply Required for PCI Same Voltage Regulation as 3.3-V DC Supply
DIP
Altera IP Development Kits
APEX DSP Development Kit APLEX 20KE PCI Development Kit SOPC Development Board DIGILAB 10K*240 Development Board PROC20K Prototyping Board Bluetooth Prototype Board Constellation 20K Prototype Board PCISYS Data Acquistition and Processing PCI Board
Megalogic 2A15 Development Board XT1000 Device Emulation Kit
DIP
MicroBlaze Kits with Boards (Xilinx)
DIP
MicroBlaze IP Peripherals Development Kit • MicroBlaze CPU • OPB Arbiter • Watchdog Timer/Timebase • Timer/Counter Block • Interrupt Controller • SRAM Controller • Flash Memory Controller • ZBT Memory Controller • BRAM • UART Lite • GPIO • SPI Master and Slave
Future Peripherals ATM Utopia Level 2 SDRAM DDR
Additional Peripherals UART 16550 UART 16450 IIC Master & Slave Ethernet 10/100 MAC
DIP
The FPGA + µp Demo Board DRAM Module
µp 8051 or AVR
The Hardware Module of FPGA+µp Demo Board
8051 or AVR
Application Specific Demo Board (Natl. Yunlin Univ.)
Power
LED
ARM SoC Development Platform
ARM Integrator/AP
System controller (FPGA) Clock generator Flash Memory(32MB) Boot Rom SRAM(512k) System expansion(CM,LM) PCI Interface, EBI Interface
DIP
System Architecture
System controller FPGA
switch Interrupt controller
Arbiter
Flash,SSRAM and ROM
Peripheral bus (APB)
Core Module(CM720T)
M )
•256KB to 1MB Synchronous SRAM •SDRAM DIMM socket (up to 256MB) •AMBA system bus interface to platform board
•Clock generators •Reset controller •JTAG interface to Multi-ICE®
DIP
CM System Architecture SD
Logic Module(LM-XCV600E+)
Flash-1
Flash-0
XCV2000E
•1MB ZBT SRAM •9 General-purpose LEDs •8 General-purpose switches •Clock generators •Push button •FPGA programming via Multi-ICE (JTAG)
DIP
LM System Architecture
System Architecture
Simulating with Testbench Waveforms
Simulating with Testbench Waveforms
Download
Download
Write technical spec.
IP Prototyping System
IP Deliverables DIP
Course Contents FPGA Device Altera, Xilinx (pp. 5~39)
FPGA Design Flow & Synthesis ISE, Quartus II (pp. 40~83)
DIP Rapid Prototyping Platform (pp. 84~104)
DIP Prototype System Measurement (pp.105~141)
Design Example (pp.142~167)
FPGA Device
FPGA Design Flow & SynthesisFPGA Design Flow & SynthesisFPGA Design Flow & Synthesis
DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform
DIP Prototype System Measurement DIP Prototype System Measurement DIP Prototype System Measurement
Design ExampleDesign ExampleDesign Example
PLD Complexity Drives Design Methodology Changes PLD Complexity Drives Design Methodology Changes
Increasing Time-to-Market Pressures Drive Change
SOPC Design SOPCSOPC DesignDesign
Altera Device FamiliesAltera Device Families Programmable Logic Families
High & Medium Density FPGAs Stratix, APEX II, APEX 20K, & FLEX 10K
Low-Cost FPGAs Cyclone & ACEX 1K
FPGAs With Clock Data Recovery Mercury & Stratix GX
CPLDs MAX 7000 & MAX 3000
Embedded Processor Solutions NiosTM, ExcaliburTM
Configuration Devices EPC
APEX 20K Family
Industry’s first MultiCore Architecture – Look-up table (LUT) logic – Product-term logic – Embedded memory
Fabricated on SRAM Process – 2.5-V, 0.25/0.22-Micron Process – 1.8-V, 0.18-Micron Process
DIP
APEX MultiCore Architecture
Facilitates Efficient IP Integration – Look-up Table Core – Product-Term Core – Memory Core
DIP
Enhanced FastTrack Interconnect
DIP
APEX 20K Device Features
The Stratix Device FamilyThe Stratix Device Family Feature
Process
Density
Performance
Clock Management
I/O Capabilities
Average 40% Increase
TriMatrix™ Memory Incorporating 3 Block Sizes for Maximum Bandwidth & Capacity
Embedded DSP Blocks for Complex Arithmetic Functions
Advanced System Clock Control for On- & Off-Chip Clock Needs
840-Mbps Differential I/O Signaling, High-Speed Interface Support, External Memory Interfaces & On-Chip Termination Technology
DIP
Stratix Architecture OverviewStratix Architecture Overview
DSP BlocksLogic Array Blocks (LABs)
MegaRAM™ Blocks
Advanced I/O CapabilitiesAdvanced I/O Capabilities High-Speed Interface Protocols − 10-Gigabit Ethernet XSBI − POS-PHY Level 4 − HyperTransport − RapidIO (Parallel)
High-Speed Interface Protocols − 10-Gigabit Ethernet XSBI − POS-PHY Level 4 − HyperTransport − RapidIO (Parallel)
Differential & Single- Ended I/O Standards − LVDS, LVPECL,
HyperTransport, PCML − HSTL, SSTL − PCI, PCI-X, Compact PCI
Differential & Single- Ended I/O Standards − LVDS, LVPECL,
HyperTransport, PCML − HSTL, SSTL − PCI, PCI-X, Compact PCI
Terminator Technology − On-Chip Differential
Termination − On-Chip Series & Parallel
Matching
External Memory Device Interfaces − DDR SDRAM & SRAM − SDR SDRAM − QDR & QDRII SRAM − ZBT SRAM − DDR FCRAM
External Memory Device Interfaces − DDR SDRAM & SRAM − SDR SDRAM − QDR & QDRII SRAM − ZBT SRAM − DDR FCRAM
DIP
TriMatrix Memory Structure
DirectDrive™ Technology
Each Interconnect Line Driven by Single Source – Consistent Access to Routing – Eliminates Congestion
Uniform Routing Resources Across Device – Ensures Blocks Can be Moved within or between Designs
DIP
DSP Block
DSP Block Modes
The Stratix Device FamilyThe Stratix Device Family
94
194
224
295
384
574
767
1,118
10,570
18,460
25,660
32,470
41,250
57,120
79,040
114,140
60
82
138
171
183
292
364
520
1
2
2
4
4
6
9
12
920,448
1,669,248
1,944,576
3,317,184
3,423,744
5,215,104
7,427,520
10,118,016
6
10
10
12
14
18
22
28
July
Q3
June
Q4
Q3
Q4
July
2003
Package Offerings & User I/OPackage Offerings & User I/O
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
EP1S120
341
422
469
Nios Flexibility & ScalabilityNios Flexibility & Scalability Network Processor
System
Nios System Architecture
On-Chip Debug Core
Off-Chip Software Trace
ARM-Based Excalibur Embedded Processor ARM-Based Excalibur Embedded Processor
PLD Area for Customer
ARM922T Core
Single-Port RAM
Dual-Port RAM
200-MHz ARM922T™ Processor Up to 3.3 Mbits of Memory Up to 1M Gates of Programmable Logic
DIP
Embedded Processor PLD ArchitectureEmbedded Processor PLD Architecture
PLL
Timer
UART
DPRAM
EPXA1
EPXA4
EPXA10
LEs 4,160 ESB (Bytes) 6.5K
LEs 16,400 ESB (Bytes) 26K
LEs 38,400 ESB (Bytes) 40K
Embedded Stripe
Introduction to Xilinx Product • FPGA : Spartan/XL, Spartan II,Spartan-IIE, • Virtex, VirtexE,Virtex II,Virtex-II Pro • CPLD : XC9500/XL, CoolRunner • Software :Foundation4.2i, ISE Alliance4.2i, • ISE 4.2 • Core : IP, LogiCore, Alliance Core •Technical Support : support.xilinx.com, FAEs
DIP
Density, Performance, Cores & Memory
DIP
Spartan-II Architecture Delay Lock Loop (DLL)
DLL
De-skew clock
Chip to Backplane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL+, AGP
Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT
Chip to Chip LVTTL, LVCMOS
SelectI/OTM
Technology
Block Memory
Simplified CLB Structure
3 Level Memory Hierarchy
Virtex-II Pro Platform FPGA
MGT
MGT
MGT
MGT
Fabric
• •
•
• IP-Immersion™ Fabric • ActiveInterconnect™ • 18Kb Dual-Port RAM • Xtreme™ Multipliers • 16 Global Clock Domains
•
•
PowerPC 405 I-Side On-Chip Memory (OCM) 5-stage data path pipeline
16KB D and I Caches Embedded Memory Management Unit Execution Unit
Multiply / divide unit 32 x 32-bit GPR
Dedicated on-chip memory interfaces Timers: PIT, FIT, Watchdog Debug and trace support Performance:
450 DMIPS at 300 MHz 0.9mW/MHz Typical Power
D-Side On-Chip Memory (OCM)
Fetch & Decode
Timers and
Debug Logic
Pr oc
es so
Virtex ®
-II Family 12 Devices, 10 Packages, 37 combinations
Virtex-II XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V Part Number 40 80 250 500 1000 1500 2000 3000 4000 6000 8000 10000 LUTs + FFs 512 1,024 3,072 6,144 10,240 15,360 21,504 28,672 46,080 67,584 93,184 122,880 BRAM (Kb) 72 144 432 576 720 864 1,008 1,728 2,160 2,592 1,024 3,456 Multipliers 4 8 24 32 40 48 56 96 120 144 168 192 DCM Units 4 4 8 8 8 8 8 12 12 12 12 12 CS144 88 92 92 FG256 88 120 172 172 172 FG456 200 264 324 FG676 392 456 484 FF896 432 528 624 FF1152 720 824 824 824 824 FF1517 912 1,104 1,108 1,108 BG575 328 392 408 BG728 456 516 BF957 624 684 684 684 684 684
DIP
XC9500XL Overview
compatible levels with 5.0/2.5V
High fMAX = 200 MHz Fast tPD = 4 nsec Best ISP/JTAG support Best pin-locking Advanced packaging
DIP
Technology
0.35um feature-size (0.25um Leff) 4 layers of metal
Superior reliability Reprogramming endurance = 10,000 Charge retention = 20 years
Fast programming characteristics
High Level Architecture
XC9500XL Family 9536XL 9572XL 95144XL 95288XL
Macrocells 36 72 144 288
Usable Gates 800 1600 3200 6400
tPD (ns) 4 5 5 6
fMAX (MHz) 200 178 178 151
Packages QFP
40K Spartan-XL
ATM ATM IMA IMA
Cable Modem Ethernet Ethernet
250k unit
DIP
Spartan-II Family Overview Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Logic Cells 432 972 1728 2700 3888 5292 Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344 Block RAM Qty. 4 6 8 10 12 14 Max. User I/Os 86 132 176 196 260 284 Package VQ100 VQ100
CS144 CS144 TQ144 TQ144 TQ144 TQ144
PQ208 PQ208 PQ208 PQ208 PQ208 FG256 FG256 FG256 FG256
FG456 FG456 FG456
FPGA DeviceFPGA DeviceFPGA Device
FPGA Design Flow & Synthesis
DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform DIP Rapid Prototyping Platform
DIP Prototype System Measurement DIP Prototype System Measurement DIP Prototype System Measurement
Design ExampleDesign ExampleDesign Example
Function Sim
Design Entry
Programming & Debug
Placement & Routing
XilinxXilinx ISEISE
ISE Design Flows
Project Navigator
Creating New Projects
Adding Source Files
Creating HDL Source
HDL Wizard
HDL Wizard
Confirm information
Setting Implementation Option
Setting Synthesis Options
Accessing Advanced Options
Initiating a Design Flow
Accessing Reports
Static Timing Report
Proactive Timing Closure
Xilinx Synthesis Technology
HDL Bencher
Simulating with Testbench Waveforms
Simulating with Testbench Waveforms
ModelSim HDL Simulator
Using I/O Buffers
Configuration Download
Altera Quartus II
Design Methodologies
Quartus supports three common design methodologies: Top-down
Create a top-level of the design first, and then break down the design into lower-level design blocks.
Bottom-up Begin by creating the lower-level design blocks first and then stitch together the design at the top-level.
Middle-out Start in-between Top-down and Bottom-up design methodologies
DIP
PLD Design Flow(1)
PLD Design Flow(2)
Design Entry Multiple design entry methods
Quartus Block/Schematic Editor Text Editor
AHDL, VHDL, Verilog Memory Editor
Hex, Mif Third party EDA tools
EDIF HDL VQM
Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry
DIP
Design Entry Files Quartus
.bdf
.gdf
Top-level design files can be .bdf, .tdf, .vhd, .vhdl, .v, .vlg, .edif or .edf
.bsf .vhd
Block File
Symbol File
Text File
Text File
Exemplar, Synopsys, Synplicity, etc...
Main Toolbar and Modes
New Project Wizard
What is the name of this project
What is the name of the top-level design entitiy in your project
DIP
New Project Wizard
Set Chips & Devices
Set User Libraries
Compiler
Show the section of compiler
Compiler Message
summary
Timing Analysis Features
•Quartus II has built in static timing analysis Single
•clock timing analysis – fmax (maximum clock frequency) – Tsu, Th, Tco (setup time, hold time, clock-to-out
time) – Optional system fmax reporting
• Multi-clock analysis – Allows analysis of multiple synchronous clocks – Slack analysis is used
DIP
Timing Analysis
fmax
DIP
Locate Delay Path in Floorplan
DIP
Download
Make sure Type is “ByteBlasterMV”
Make sure is “JTAG”
Download
DIP
FPGA DeviceFPGA DeviceFPGA Device
FPGA Design Flow & SynthesisFPGA Design Flow & SynthesisFPGA Design Flow & Synthesis
DIP Rapid Prototyping Platform
DIP Prototype System Measurement DIP Prototype System Measurement DIP Prototype System Measurement
Design ExampleDesign ExampleDesign Example
IP Rapid Prototype Platform
SRAMFlashPIO_buttons
uart
seven_segment
EPXA10 Development Board (Altera)EPXA10 Development Board (Altera)
POWER BOOT_FLASH
EPXA10 Development Board FeaturesEPXA10 Development Board Features
Platform for Device Evaluation & Application Development Memory Support 1. SDR SDRAM: 256 Mbytes 2. Flash: 16 Mbytes
Flexible Clocking 50-MHz Embedded Stripe Clock
External Clock Generator Can Be Used Dedicated Stripe PLLs for Frequency Synthesis
PLD Clocks Dedicated Crystals for Each of Four PLD PLLs
Application Support Two UARTs ByteBlasterMV™ JTAG Connector Multi-ICE & Trace Port Connectors Ethernet PHY
DIP
EPXA10 Development Board FeaturesEPXA10 Development Board Features
PCI Two 3.3-V 33-MHz PCI Connectors Provided for Off-the-Shelf Applications
User Interface 1. Eight LEDs 2. Four Push-Buttons 3. Nine-Position DIP Switch
Power Supply 3.3-Volt DC Supply
1.8-V Generated 1.25-V Generated for VREF & VTT
ATX Power Supply Required for PCI Same Voltage Regulation as 3.3-V DC Supply
DIP
Altera IP Development Kits
APEX DSP Development Kit APLEX 20KE PCI Development Kit SOPC Development Board DIGILAB 10K*240 Development Board PROC20K Prototyping Board Bluetooth Prototype Board Constellation 20K Prototype Board PCISYS Data Acquistition and Processing PCI Board
Megalogic 2A15 Development Board XT1000 Device Emulation Kit
DIP
MicroBlaze Kits with Boards (Xilinx)
DIP
MicroBlaze IP Peripherals Development Kit • MicroBlaze CPU • OPB Arbiter • Watchdog Timer/Timebase • Timer/Counter Block • Interrupt Controller • SRAM Controller • Flash Memory Controller • ZBT Memory Controller • BRAM • UART Lite • GPIO • SPI Master and Slave
Future Peripherals ATM Utopia Level 2 SDRAM DDR
Additional Peripherals UART 16550 UART 16450 IIC Master & Slave Ethernet 10/100 MAC
DIP
The FPGA + µp Demo Board DRAM Module
µp 8051 or AVR
The Hardware Module of FPGA+µp Demo Board
8051 or AVR
Application Specific Demo Board (Natl. Yunlin Univ.)
Power
LED
ARM SoC Development Platform
ARM Integrator/AP
System controller (FPGA) Clock generator Flash Memory(32MB) Boot Rom SRAM(512k) System expansion(CM,LM) PCI Interface, EBI Interface
DIP
System Architecture
System controller FPGA
switch Interrupt controller
Arbiter
Flash,SSRAM and ROM
Peripheral bus (APB)
Core Module(CM720T)
M )
•256KB to 1MB Synchronous SRAM •SDRAM DIMM socket (up to 256MB) •AMBA system bus interface to platform board
•Clock generators •Reset controller •JTAG interface to Multi-ICE®
DIP
CM System Architecture SD
Logic Module(LM-XCV600E+)
Flash-1
Flash-0
XCV2000E
•1MB ZBT SRAM •9 General-purpose LEDs •8 General-purpose switches •Clock generators •Push button •FPGA programming via Multi-ICE (JTAG)
DIP
LM System Architecture
System Architecture
Simulating with Testbench Waveforms
Simulating with Testbench Waveforms
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