introduction to combinational logic...
TRANSCRIPT
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Introduction to Combinational Logic Circuits (Class 2.1 – 1/22/2013)
CSE 2441 – Introduction to Digital Logic
Spring 2013
Instructor – Bill Carroll, Professor of CSE
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Today’s Topics
• Reminder – check course website regularly http://crystal.uta.edu/~carroll/
• Digital logic circuit taxonomy
• Basic logic gates – AND, OR, NOT, NAND, NOR, XOR
• Truth tables, logic equations
• Half adders and full adders
• Basic Verilog statements and modules
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Digital Logic Circuit Taxonomy
• Combinational Circuits – Primary characteristic -- memoryless
– Primary building blocks -- logic gates
• Sequential circuits – Primary characteristic -- memory
– Primary building blocks -- logic gates, flip-flops
– Types • Synchronous (clocked)
• Asynchronous (unclocked)
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Combinational Logic Circuits and Truth Tables
a b c z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Circuit Diagram Block Diagram
Truth Table Logic Equation
z = ab + ac + bc
Verilog HDL Code
module LogicCircuit (a,b,c,z); input a,b,c; output z; wire j,k,l; and (j,a,b); and (k,b,c); and (l,a,c); or (z,j,k,l); endmodule
j
k
l
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Basic Logic Gates – AND, OR, NOT
AND gate OR Gate NOT Gate
a b f a
b f a f
a b f
0 0 0
0 1 0
1 0 0
1 1 1
a b f
0 0 0
0 1 1
1 0 1
1 1 1
a f
0 1
1 0
f = a·b f = a + b
f = a’
and(f,a,b) or(f,a,b)
not(f,a)
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Basic Logic Gates – NAND, NOR
a b f
0 0 1
0 1 1
1 0 1
1 1 0
a b f
0 0 1
0 1 0
1 0 0
1 1 0
a b f a
b f
NAND gate NOR gate
f = (a·b)’ f = (a + b)’
nand(f,a,b) nor(f,a,b)
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Test Your Understanding
NAND3 gate a b c f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Logic equation f = ?
Verilog code
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Test Your Understanding – Self-Check
NAND3 gate a b c abc f=(abc)’
0 0 0 0 1
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
Logic equation f = ?
Verilog code
f = (a·b·c)’
nand(f,a,b,c)
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Exclusive-OR (XOR)
a b f
0 0 0
0 1 1
1 0 1
1 1 0
f = a b
xor(f,a,b)
ab’ b’
a’ a’b
f = ab’ + a’b
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XOR3 Realizations
g = f c = (a b) c = a b c
= a’b’c + a’bc’ + ab’c’ + abc
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Half Adder
a b cout s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Output logic equations
s = a b
cout = a·b
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Full Adder Realization
Output logic equations
s = a b cin
= a’b’cin + a’bcin’
+ ab’cin’ + abc
cout = a’bcin + ab’cin
+ abcin’ + abcin
= ab + acin + bcin
= majority (a,b,cin)
Logic Circuit Diagram
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FA = HA + HA + OR2
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HA and FA Verilog Code
module halfadder (s, cout, a, b);
input a, b;
output s, cout;
and (cout, a, b);
xor (s, a, b);
endmodule
module fulladder (s, cout, a, b, cin);
input a, b, cin;
output s, cout;
wire d, e, f, g;
xor (d, a, b);
xor (s, d, cin);
and (e, a, b);
and (f, a, cin);
and (g, b, cin);
or (cout, e, f, g);
endmodule
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Summary of Basic Logic Gates
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Chapter 2 16
Dual In-line Packages (DIP) – 1
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GND
7400: Y = ABQuadruple two-input NAND gates
1A
Vcc 4Y 4B 4A 3Y 3B 3A
1Y 1B 2A2Y 2B
14 13 12 11 10 9 8
7654321
GND
7402: Y = A + BQuadruple two-input NOR gates
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GND1Y
Vcc 6A 6Y 5A 5Y 4A 4Y
1A 2A 3A2Y 3Y
14 13 12 11 10 9 8
7654321
GND
7404: Y = AHex inverters
7408: Y = ABQuadruple two-input AND gates
Power signals 4.75 ≤ Vcc ≤ 5.25 volts GND = 0 volts
Inputs signals 0 ≤ L ≤ 0.8 volts 2.0 ≤ H ≤ 5.25 volts
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Chapter 2 17
Dual In-line Packages (DIP) – 2
1B
Vcc 1C 1Y 3C 3B 3A 3Y
1A 2A 2C2B 2Y
14 13 12 11 10 9 8
7654321
GND
7410: Y = ABCTriple three-input NAND gates
1B
Vcc 2D 2C NC 2B 2A 2Y
1A NC 1D1C 1Y
14 13 12 11 10 9 8
7654321
GND
7420: Y = ABCDDual four-input NAND gates
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Chapter 2 18
Dual In-line Packages (DIP) – 3
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GNDB
Vcc NC H G NC NC Y
A C ED F
14 13 12 11 10 9 8
7654321
GND
7430: Y = ABCDEFGH8-input NAND gate
7432: Y = A + BQuadruple two-input OR gates
1B
Vcc 4B 4A 4Y 3B 3A 3Y
1A 1Y 2B2A 2Y
14 13 12 11 10 9 8
7654321
GND
7486: Y = A Å BQuadruple two-input exclusive-OR gates
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Chapter 2 19
Positive and Negative Logic (1)
Electrical Signals and Logic Values
– A signal that is set to logic 1 is said to be asserted, active, or true. – An active-high signal is asserted when it is high (positive logic). – An active-low signal is asserted when it is low (negative logic). – For TTL devices, 0 ≤ L ≤ 0.8 volts, 2 ≤ H ≤ 5.25 Volts
Electric Signal Logic Value
Positive Logic Negative Logic
High Voltage (H) 1 0
Low Voltage (L) 0 1
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Positive and Negative Logic (2)
Voltage Levels Positive Logic Negative Logic
VX VY VZ X Y Z X Y Z
0 0 0 0 0 0 1 1 1
0 4.9 4.9 0 1 1 1 0 0
4.9 0 4.9 1 0 1 0 1 0
4.9 4.9 4.9 1 1 1 0 0 0