A.SANYASI RAOA.SANYASI RAOAssoc. Prof. & HoDAssoc. Prof. & HoD

Dept. of ECEDept. of ECEBalaji Institute of Engineering & SciencesBalaji Institute of Engineering & Sciences

Narsampet, WarangalNarsampet, Warangal

What is a Combinational circuit?

At instant, the output of the logic circuit depends on present inputs.

Design procedure:Design procedure:

1.Identify the number of inputs and outputs required for the design of the circuit.

2.Derive the truth table.3.Write the expression for the output either in SOP or POS form.

4.Simplify the expression for the output.

5.Draw the logic circuit for the simplified expression.

ADDERSADDERS

Logic circuit which performs the addition of binary numbers

Adders of two types:

1. Half Adder (H.A)2. Full Adder (F.A)

Half AdderHalf Adder

It is a combinational logic circuit which performs addition of two binary bits.

A B Sum(S) Carry(C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1 ABC

BABAS

Full AdderFull AdderIt is a combinational logic circuit which performs addition of three binary inputs.

ABBAC

CCABBABAC

ABCCABCBABCAC

CBA

CBACBA

BCCBACBCBA

ABCCBACBACBAS

in

ininin

ininininout

in

inin

inininin

inininin

)(

)()(

)()(

)()(

Realizing Full Adder with two Half Adders and one OR gateRealizing Full Adder with two Half Adders and one OR gate

SUBTRACTORSSUBTRACTORSLogic circuit which performs subtraction of binary numbers.

Subtractors are of two types:1. Half Subtractor (H.S)2. Full Subtractor (F.S)

Half Subtractor

Half Subtra

ctor

A

B

D

BOUT

A B Difference(D) Borrow(B0)

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

BAB

BABAD

0

Full SubtractorCombinational circuit which performs subtraction on three binary digits.

Half Subtra

ctor

A

Bin

D

BOUT

B

A B Bin D BOUT

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1BABAB

BBBAABBAB

ABBBBABBABBAB

BBA

BBABBA

BBBBABBBBA

ABCBBABBABBAD

in

ininin

ininininout

in

inin

inininin

inininin

)(

)()(

)()(

)()(

Half Subtractor

Half Subtractor

A

B

D

Bin

Bout

Realizing Full Subtractor using two Half Subtractors & one OR gateRealizing Full Subtractor using two Half Subtractors & one OR gate

4-Bit Binary Parallel Adder4-Bit Binary Parallel Adder

Each stage in the parallel adder depends on the previous stage carry.

Delay time is additive.

1’s Complement Subtractor1’s Complement Subtractor

It requires two stages of addition. When the end carry is

1, it has to be added with the LSB adder. If the end carry is

zero, single stage of addition produces the result but the

answer is negative.

2’s Complement Adder/Subtractor2’s Complement Adder/Subtractor

Adder if M=0

Subtractor if M=1

When the control input, M is 0 the output of XOR

gates are B3B2B1B0 and the circuit functions as a 2’s

complement adder.

When the control input is 1 the output of XOR

gates are B3’ B2

’ B1’ B0

’ which is the 1’s complement of the

subtrahend. Since the control input is 1, the binary 1 is

added with the LSB added with B3’ B2

’ B1’ B0

’ which

produces 2’s complement of the subtrahend. Therefore

the circuit behaves as an 2’s complement subtractor.

BCD AdderBCD Adder

The BCD adder requires two stages of addition when the result is greater

than 9. the result will be greater than 9, if C4 = 1 or S3S2 = 1 or S3S1 = 1. Therefore

the logic expression for these conditions are Y= C4 + S3S2 + S3S1 . if Y=1, binary 6

must be added with S3S2 S1S0 which is performed by the lower stage adders.

A0 B0A1 B1A2 B2A3 B3

H.AF.A F.A F.A

F.A H.A

COUT S’3 S’2 S’1 S’0

C4

S2S3 S1

Carry Look Ahead AdderCarry Look Ahead Adder

The parallel adder is ripple carry type in which the carry output of each full adder stage is connected to the carry input of the next higher-order stage . Therefore, the sum and carry occurs; this leads to a time delay in the addition process. This delay is known as propagation delay.

One method of speeding up this process by eliminating inter stage carry delay is called look ahead carry addition.

The Carry Look Ahead Adder is able to generate carries before the sum is produced using the propagate and generate logic to make addition much faster.

It uses two functions: Carry Generate & Carry Propagate.

Consider full adder circuit. Here we define the above two functions

Ai

Bi

Ci

Pi

Gi

Si

Ci+1

iiii

iii

iii

iii

CPGC

CPS

aswrittenbecancarryandsumoutputThe

BAG

BAP

1

Gi is called a carry generate and it produces on carry when both Ai and Bi are 1, regardless of the input carry. Pi is called a carry propagate because it is the term associated with the propagation of the carry from Ci to Ci+1

C1 = G0 + P0.C0 C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0 C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0 C4 = G3 + P3.G2 + P3.P2.G1 + P3P2.P1.G0 + P3P2.P1.P0.C0 Si = Ai Bi Ci = Pi Ci

Gi = Ai.Bi Pi = (Ai Bi)

Since all carries' are dependent on C0 , they can be generated simultaneously and the addition process becomes faster. The hardware required is more. Hence the carry-look ahead adder is expensive compared to parallel adder.

A0 B0

A1 B1

A2 B2

A3 B3

P1

P2

P3

S0

S1

S2

S3

C4

C0

G3

G2

P3

P2

G1

P1

G0

P0

P0

C1

C2

C3

C4

C0

CARRY

LOOK

AHEAD

GENERATOR

COMPARATORSCOMPARATORS

A comparator is a logic circuit use to compare the magnitudes of two binary numbers. It provide an output that is active when the two numbers are equal, or additionally provide outputs that signify which of the numbers is greater when equality does not hold.

The XNOR gate (coincide gate) is a basic comparator, because its output is a 1 only if its two input bits are equal.

Two binary numbers are equal, if and only if all their corresponding bits coincide. For instance, two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 are equal. To implement this logic

))()()(( 00112233 BABABABAEquality

1-Bit Magnitude Comparator1-Bit Magnitude Comparator

The logic for a 1-bit comparator: let the 1-bit numbers be A=A0 and B=B0

00

00

00

00

00

00

E:BA therefore,

,

AL:BA therefore,

B A then 1, B and 0 A If

AG:BA therefore,

B A then 0, B and 1 A If

BA

BAthencoincideBandAIf

B

B

A0 B0 L E G

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

A0

B0

2-bit Magnitude Comparator2-bit Magnitude Comparator

The logic for a 2-bit magnitude comparator:

1.If A1 = 1 and B1 = 0, then A > B or2.If A1 and B1 coincide and A0 = 1 and B1 = 0, then A > B. So the logic for A > B is

00111 )(: 1 BABABAGBA

1. If A1 = 0 and B1 = 1, then A < B or2. If AJ1 and B1 coincide and A0 = 0 and B0 = 1, then A < B.

So the logic for A < B is

00111 )(:1

BABABALBA

If A1 and B1 coincide and if A0 and B0 coincide then A = B. So the logic for A = B is

))((: 0011 BABAEBA

A1

A1 B1

A0 B0

B’1

A0

B’0

A’0

A’1

B0

B1

A > B

A = B

A < B

4-Bit Magnitude Comparator4-Bit Magnitude Comparator

The logic for a 4-bit magnitude comparator:

1.If A3 = 1 and B3 = 0, then A > B or2.If A3 and B3 coincide, and if A2 = 1 and B2 = 0, then A > B or 3.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=1 and B2 = 0, then A > B or 4.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1 and B1 coincide, A0=1 and B1 = 0, then A > B or

So the logic for A > B is

00112233112233

22333

))()(())((

)(: 3

BABABABABABABA

BABABAGBA

The logic for A < B is:

1.If A3 = 0 and B3 = 1, then A < B or2.If A3 and B3 coincide, and if A2 = 0 and B2 = 1, then A < B or 3.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=0 and B2 = 1, then A < B or 4.If A3 and B3 coincide, and if A2 and B2 coincide, and if A1 and B1 coincide, A0=0 and B1 = 1, then A < B or

So the logic for A < B is

00112233112233

22333

))()(())((

)(:3

BABABABABABABA

BABABALBA

2-Bit Binary Multiplier2-Bit Binary Multiplier

A1 A0 B1 B0

A1 B0 A0 B0 A1 B1 A0 B1

P4 P3 P2 P1

A0

A1

B0

B1

B1

B0

P4 P3 P2 P0

H. A H. A

MULTIPLEXERSMULTIPLEXERS

A Multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output.

The routing of the desired data input to the output is controlled by SELECT lines.

A MUX selects 1-out-of-N input data sources and transmits the selected data to a single output channel. This is called Multiplexing.

MUX is also known as Many to One device.

2n X n

MUX

2n i/p s o/p

n select lines

4 X 1 MUX4 X 1 MUX

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

301201101001 ISSISSISSISSY

I0

I3

S0S1

Y

I1

I2

Applications of MultiplexersApplications of Multiplexers

1.Data selection

2.Data routing

3.Operation sequencing

4.Waveform generation

5.Parallel to serial conversion

6.Logic function generation

Logic Function GeneratorLogic Function Generator

•A multiplexer can be used in place of logic gates to implement a logic expression. •It can generate any Boolean algebraic function of a set of input variables.•A single IC can perform a function.•It is very easy to change the logic function implemented, if and when redesign of a system becomes necessary.

Multiplexers can be used to implement a logic function

directly from the function table without the need for

simplification. The select inputs of the multiplexer are used

as the function variables. The inputs of the multiplexer are

connected to logic 1 and 0 to represent the missing and

available terms.

Ex: Implementation of F(A,B,C) = Σm(1,3,5,6) using 8 : 1 MUX

0

1

2

3

4

5

6

7

1 0

S2 S1 S0

A B C

8 : 1MUX

Y

Ex: Implementation of F(A,B,C) = Σm(1,3,5,6) using 8 : 1 MUX

Step 1: Select the MSB variable as input and the remaining as selector lines variables to the MUX. If the function has n variables, then the size of the required MUX is 2n-1 – to – 1.

Step 2: Draw the truth table for the given function.

Step 3: Complete the function table.a) if both the minterms are circled, apply 1 to the

corresponding MUX input.b) if both are not circled, apply 0 to the corresponding

MUX input.c) if the top is circled and bottom is not circled, apply A1

to the corresponding MUX input.d) if the top is not circled and bottom is circled, apply A

to the corresponding MUX input.

I0

I1

I2

I3 S1 S0

B C

4 : 1MUX Y

0

1

A

A1

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

I0 I1 I2 I3

0 1 2 3

4 5 6 7

A1 A

0 1 A A1

DEMULTIPLEXERDEMULTIPLEXER

1 X 2n

DEMUX

2n o/p s i/p

n select lines

Demultiplexer, DEMUX does the reverse

operation of a MUX. It receives the message over

one input line and directs the message to of the many

output lines. Hence it known as One to Many device.

S1 S0 D Y0 Y1 Y2 Y3

0 0 1 1 0 0 0

0 1 1 0 1 0 0

1 0 1 0 0 1 0

1 1 1 0 0 0 1

DSSY

DSSY

DSSY

DSSY

013

012

011

010

Y0

Y1

Y2

Y3

S0 S1

D AND

AND

AND

AND