10-1

100

101

102

103

-45

0

45

90

135

180

Ph

ase (

deg

)

Bode Diagram

Frequency (Hz)

-100

-80

-60

-40

-20

0

20 System: GLLR_N_F

Frequency (Hz): 60

Magnitude (dB): 0.00522

Mag

nit

ud

e (

dB

)

GLRNF

GLLRNF

Design Consideration of Converter Based

Transmission Line Emulation

Bo Liu, Shuoting Zhang, Sheng Zheng, Yiwei Ma, Fred Wang, Leon M. Tolbert

The University of Tennessee, Knoxville

INTRODUCTION

Space for

QR Code

• Ac transmission line emulator is the bridge to interconnect ac systems to fulfill grid emulation functions

• All the emulator elements such as generators, loads and lines are implemented by universal three-phase voltage source converters

• In addition to the basic emulation scheme, practical design issues and emulation stability should be addressed

VOLTAGE SAMPLING

STABILITY CRITERIA

)]2()1([2

)1()(

kvkvL

kiki

emuemu

emu

12

emu

g

L

L

Feasible emulation range in a weak ac grid

0 2 4 6 8 10 120

0.5

1

1.5

2

X: 1.1

Y: 0.996

Lemu

(mH)

Mo

du

lus o

f e

igen

valu

e

Line emulator stability zone

-2 -1.5 -1 -0.5 0 0.5-1

-0.5

0

0.5

1

Real Axis

Imag

ina

ry A

xis

Root Locus

Physical inductors

G3

L filters

G4

DC Bus Short Distance

Transmission Line

Area 1

Long Distance Transmission

Line Emulator based on BTB

DC Bus

L filters

DC BusShort Distance

Transmission Line

Area 2

L9

2.5 mH 2.5 mH

G1

G2

L7

Line currents at two ends

Line voltage

L

R

Ls Rs

LLRL

RLs

22

2

)(

0.05 0.1 0.15 0.2 0.25 0.3 0.35-10

-8

-6

-4

-2

0

2

4

(A)

ia

Time (s)

( ) ( )( ) S R

SR

emu

v t v ti t dt

L

Notch

filter 1stL model

idci

PI

+

-

vdc_bias

vac +

vdc

LR

model

i+-

vdc_bias

vac +

vdc

+

+

Sampling instants

Internal PWM

carrier

Internal PWM

voltage

External PWM

voltage source

asynchronized

Half line cycle, always bigger,

Another half, always smaller

reference

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035-100

-50

0

50

100

(V)

Vab

Time (s)

Vbc

Vab

20 25 30 35 40 45 50 5545

50

55

(V)

Vd

20 25 30 35 40 45 50 55-0.5

0

0.5

(V)

Vq

Time (s)

)sin(

))sin((

)sin(

2

0

0

tVVv

tV

tVv

mmd

dqabc

m

m

5 10 15 20 25

34

35

36

(V)

Vmaster

5 10 15 20 2532

34

36

(V)

Vslave

5 10 15 20 25

56

58

60

62

(Hz)

fmaster

5 10 15 20 2556

58

60

62

(Hz)

fslave

Time (s)

External PWM

voltage source

asynchronized

Internal PWM

carrier

Four sampling

driving clock

(b) four times frequency sampling

|d|>0.75|d|<0.75

Sampling instants

Conclusion

Double

sampling

driving clock

Internal PWM

carrier

Internal PWM

voltage

(a) doubling frequency sampling

External PWM

voltage source

asynchronized

|d|>0.750.5<|d|<0.75|d|<0.5

Sampling instants

DC BIAS REMOVAL

0 0.005 0.01 0.015 0.02 0.025 0.03-100

-50

0

50

100

(V)

Vab

Time (s)

0 0.2 0.4 0.6 0.8 1-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Normalized Frequency ( rad/sample)

Mag

nit

ud

e (

dB

)

N=4 moving average

(2fsw)(fsw)

Zero error at line frequency: an adaptive solution

An equivalent high pass filter:

with zero angle delay and 0 dB

gain at interested grid

frequency range

• Time domain based transmission line emulator is

sensitive to the switching harmonics of the

interface terminal voltage and dc bias from a trivial

ADC sampling error or sensor bias

• Without a proper sampling scheme, line emulator

will introduce low frequency oscillation into line

power flow

• A dc bias removal is essential in the time domain

based transmission line emulator to eliminate the

dc current in the line flow

• Digitized line emulator has its own stability region,

related to its emulation scheme, grid topology and

emulation impedance. Feasible emulation ranges

are derived for the selected systems in this work

Grid emulation on HTB platform

L reduced to 2.5 mH: stable.5

35.6

2

emu

g

L

L

L reduced to 1 mH: unstable.2

35.6

2

emu

g

L

L

Line emulator interfaces

with other VSC based

emulators, presenting

pulsed terminal voltage

Only limited low pass

filter can be applied, to

avoid emulation latency

Scheme I Scheme II Scheme III

Low voltage and

frequency ripple can still

be observed in phasor

domain

Lg2Lg1 Lemu

i

Lg=Lg1+Lg2 Lemu

i

vS vR

vS vR

Case I

Case II

Active load helps to

stabilize the emulation

system