interfacing with i/o devices. ceg 320/520interfacing with i/o devices2 overview memory mapped vs...

Interfacing with I/O Devices

CEG 320/520 Interfacing with I/O devices 2

Overview

• Memory mapped vs programmatic I/O

• Organization of a memory mapped I/O device

• Polled I/O

• Interrupt-driven I/O– ISR’s– Shared IRQ’s– Vectored interrupts


I/O Device Models

• Programmed I/O– Special instructions to read and write from I/O

devices

• Memory-mapped I/O– I/O devices live at memory addresses– For example: MOVE.B $8000,D0 might get a

byte from an I/O device and not memory.

CPU Memory I/O


I/O Models for Common Processors

• MC68000 – Memory mapped.

• Intel CPUs – Programmed I/O– Separate instructions for I/O read/writes– Can also memory-map some devices

• PowerPC – Memory mapped, but uses a separate address space– A special control register controls which address

space is being accessed.


Organization of an I/O device• Base memory

location– Jumpers, PnP, etc.

• Status register– Sin – A word is

waiting in the input register

– Sout – The device is ready for output

• The device knows when a register is written to or read from

$8002

$8000

Sout

$8004

Sin

Input register

Output register

Status register1 0

Device

Device ControllerDevice Controller


Polled I/O• New instruction: BTST.L #bit,Dn

– Set Z according to bit of register Dn

– BEQ will branch if bit = 0, BNE if bit = 1

GETCH LEA BUFFER,A0POLLI MOVE.B $8004,D0

BTST.B #0,D0BEQ POLLIMOVE.B $8000,(A0)+

PUTCH MOVE.B $8004,D1BTST.B #1,D1BEQ PUTCHMOVE.B D0,$8002

$8002

$8000

Sout

$8004

Sin

Input register

Output register

Status reg. 1 0

Device



Drawbacks of Polled I/O

• The CPU can’t do anything else while it is polling.

• You must explicitly check every device in the system.– How often should you check the modem to see if

there is a ring?

• No way for devices to get the attention of the CPU until it is their “turn”.– No way to assure fast response to external events.


Interrupt-driven I/O

• When IRQ goes active, jump to a special memory location: the ISR, or interrupt service routine.

• Activate IACK to tell the device that the interrupt is being serviced, and it can stop activating the IRQ line.

CPU Memory I/O

IRQIACK


An ISR for a keyboard driver

CPU MEM I/O

IRQIACK

KBINIT MOVE.L #KBUF,KBPTRRTS

KBISR MOVEM.L D0/A0-A1,-(SP)MOVEA.L KBPTR,A0MOVE.B $8000,D0CMPI.B #$0D,D0 ; CR?BEQ PROC_INPUTMOVEA.L A0,A1SUBA.L #KBUF,A1CMPA.L #KBSIZE,A1BGE KB_OVERFLOWMOVE.B D0,(A0)+MOVEA.L A0,KBPTR

DONE MOVEM.L (SP)+,D0/A0-A1RTE ; a new instr

KBSIZE EQU 132KBUF DS.B KBSIZEKBPTR DS.L 1

$8002

$8000

Sout

$8004

Sin

Input register

Output registerStatus reg 1 0



ISR’s: Even more transparent• May be called at any time.• Must be completely invisible to the current running

program.• Must save all register values & restore them.• Some systems do this in hardware, some rely on the

ISR to take care of it. The 68000 splits up the work…– The SR and the PC are saved when an INTR is triggered

– The ISR must save and restore any other registers used

– The RTE instruction restores the SR and the PC


What happens on an interrupt

• SR:

• When an interrupt is activated, the CPU:1. Pushes the PC (L) and the SR (W) on the stack

2. Switches to supervisor mode (S=1)

3. Jumps to the ISR

• In supervisor mode, we can write to the status register and use the supervisor stack!

T S I I I Z V CX N

Interruptpriority

ConditioncodesSupervisor

Trace


The RTE instruction

• When the ISR is done servicing the interrupt, it returns using the RTE (return from exception) instruction.

• This instruction is similar to RTS, but it does more. RTE does the following:

1. SR [[SP]]

2. SP [SP] + 2

3. PC [[SP]]

4. SP [SP] + 4

This will restore the S bit along with the rest of the SR.

If we were in user mode, before the interrupt, we are back in user mode when we

return from the ISR.


Interrupts from multiple devices

• When IRQ is activated, the CPU checks bit I in the status register of each device to see which one (or more) need an IRQ serviced.– The order is fixed, so the first

device polled has higher de facto priority

CPU Memory I/O 1 I/O 2 I/O 3 I/O 4

IRQ

Sout Sin

Input register

Output register

1 0


1

I

Bus


Vectored Interrupts

• If we have multiple devices, we need a very large ISR that knows how to deal with all of them!

• Using vectored interrupts, we can have a different ISR for each device.

• Each I/O device has a special register where it keeps a special number called the interrupt vector.– The vector tells the CPU where to look for the

ISR.


A vectored-interrupt device

$8002

$8000

$8004

Input register

Output register


Status register

$8006 Interrupt VectorRegister

67

• When I trigger an interrupt, look up address When I trigger an interrupt, look up address number 67 in the vector table, and jump to that number 67 in the vector table, and jump to that address.address.

… Sin Sout

IESIN IESOUT


Getting the interrupt vector

• INTA tells a device to put the interrupt vector on the bus

• INTA is daisy chained so only one device will respond

CPUMemory I/O 1 I/O 2 I/O 3 I/O 4

IRQ

INTA


The Vector Table

• The interrupt vector table is stored in memory addresses $0000 through $03FC.

• The contents of the vector table are addresses to jump to when each vectored interrupt occurs. (Absolute long)

…$0100

…$0014$0010$000C$0008$0004$0000

$03FC

64 – 255

…

5 – Div by zero4 – Illegal Instr

3 – Address Err

2 – Access Fault

1 – Reset PC

0 – Reset SP

user defined…


The 68000 Vector table

When we do TRAP #14we jump to the address stored here!

• Each entry in the vector table is the address of an ISR.

• Each entry takes 2 words, so the location of vector n is address(n × 4)


Installing a vectored interrupt device• Step 1: Write an ISR

and store it in memory.– The ISR must know the

addresses of the registers in the device

• Step 2: Put the address of the ISR somewhere in the vector table

• Step 3: Put the vector number in the Vector Register of the device

KBISR LEA BUFFER,A0MOVE.B $8000,D0CMPI.B #0D,D0 ; CR?BEQ PROCESSMOVE.B D0,(A0)+…RTE

MOVE.L #KBISR, $100 ;$100 = 256 = 64 * 4

MOVE.L #64, $8006 ;$8006 = Vect. Reg.


Memory map for a vectored interrupt device

$1000

…

(256) $0100

$8000

ISR code… RTE

$8002$8004

Output registerStatus register

$8006 64

$0000 1000

Input register


A simple keyboard driver

$8002

$8000

$8004

Input register

Ouptut register

Status register

$8006 Ivec = 26

DATAIN EQU $8000DATAOUT EQU $8002STATUS EQU $8004VECTOR EQU $8006LINE DS.B 81PNTR DS.L 1

MOVE.L #26, VECTOR ; 26 x 4 = 104 = $68


Priority Interrupts Only!• What do we do if we are processing an interrupt and

another device signals an interrupt?– We can disable (mask) all interrupts while processing an

interrupt (IE bit in the SR)

• Some devices require very low interrupt latency (e.g. system clock) while some can tolerate long latency (e.g. keyboard).

• The 68000 has 8 interrupt priorities.– While processing an interrupt of level n, interrupts from

other devices of level n and lower are ignored. Only higher priority interrupts are allowed.


Interrupt Priorities

T S I I I Z V CX N

Interruptpriority

ConditioncodesSupervisor

Trace

• An ISR can set the interrupt mask (or interrupt priority bits) by directly changing the contents of the status register.

• MOVE.W xx,SR is a privileged instruction. Which means it is only allowed in supervisor mode.

• 68000: An interrupt at level 7 is always accepted• A level 7 interrupt is a nonmaskable interrupt.


Software interrupts

• Interrupts can be triggered by more than just I/O devices:– Program errors, like division by zero, can trigger

interrupts.– The OS uses interrupts for multitasking and other

purposes.

• 68000: The TRAP instruction triggers a software interrupt– You can assign any ISR you wish to the vector

entries for TRAP #0 through TRAP #15


Direct Memory Access (DMA)

• Even with interrupts, a lot of CPU effort is expended just moving bytes around from I/O devices to/from memory– Modem – interrupt every time a byte arrives?

• DMA allows devices to access memory directly– A large amount of data can be stored to a memory

location, and then an interrupt can be triggered to process all the data at once.


A DMA Controller• A DMA controller can

transfer a large amount of data between a device and memory– Example – send a stream of

print data to a printer, and notify the CPU when done

• The controller needs to know:– Where in memory should the

data be found/put?– How many bytes of data

should be transferred?

Starting address

Byte count

Status and control register:

IRQ IE DoneR/W

CPU Memory

DiskPrinter

Bus


Bus Arbitration

• Both the CPU and the DMA controller can use the bus

• There are often multiple DMA controllers

• No two devices can use the bus at the same time

Memory

DiskPrinter

Bus

DMA Controller

CPU


Bus Arbitration Details

• Signal Bus Request (BR) to request the bus

• CPU asserts Bus Granted (BG)– If DMA controller didn’t request the bus, pass it on to

BG2, BG3, etc.

• Controller asserts Bus Busy (BBSY) until done

CPUDMA

Controller1

DMAController

2

BBSY

BR

BG1 BG2


Bus Arbitration Policies

• No one can use the bus (not even the CPU) while BBSY is asserted, except for the DMA controller that is the current “bus master”.

• Cycle stealing – When you get the bus, perform a few transfers and then release it– High-speed peripherals, like disks, get bus priority

• Block mode – Perform an entire transfer before releasing the bus.


You should know…• General concepts for I/O devices:

– Programmatic vs. memory-mapped I/O– Polling vs. Interrupt-driven I/O– Vectored interrupts, interrupt priorities– DMA, Bus Arbitration

• Details for the 68000– Exactly what happens in the CPU on an interrupt

• What does the RTE instruction do?

– How to write a simple ISR– How to initialize the I/O device and the vector

table


68000 Pinouts

interfacing with i/o devices. ceg 320/520interfacing with i/o devices2 overview memory mapped vs...

Documents

io devices4 io models

io devices9

io readwrites

io devices3 io device

cpu memory io slide

io special instructions

io separate instructions

io devices5 organization