igct training

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IGCT TrainingRené Ernst

Sales Engineer

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Contents

Principle of operation Basic Topologies Design criteria for VSI VSI clamp circuit design Applying IGCT gate unit Series connection

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Introduction to IGCTs

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Electronic Switches

Thyristor Can be turned on by gate signal but can only be turned off by

reversal of the anode current

Gate Turn-Off Thyristor (GTO) Can be turned on and off by the gate signal but requires large

capacitor (snubber) across device to limit dv/dt

Transistors (transitional resistor)

Can be turned on and off by the gate (or base) signal but has high conduction losses (its an amplifier, not a switch)

Integrated Gate Commutated Thyristor (IGCT) Can be turned on and off by the gate signal, has low conduction

loss and requires no dv/dt snubber

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IGCT model

Two-transistor “Regenerative Switch” model of a GTO

KCATHODE

GATE

ANODE A A

K

GG

Ia

Ik

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Principle of IGCT Operation

P

N

P

N

Anode

Cathode

Gate

IAK

IGK

P

N

P

N

Anode

Cathode

Gate

- VGK

VAK

Conducting Thyristor Blocking Transistor

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Hard Turn-off mode

anode current

gate current

UGK

tcomm

tdesat

UAK

UAK, IA, IG

t

UGK

t

Snubber less operation => tdsat > 0

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IGCT Turn-off

4

1

Ia (kA)

Vdm

Tj = 90°C

Itgq

4

3

2

1

0

-10

-20

Vg (V)

2

3

0

anode voltage Vd

anode current Ia

gate voltage Vg

thyristor transistorx

starts to block

Vd (kV)

2015 3025 35 ts)

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Thermal distribution

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IGCT = GTO + IGBT?

GTO’s low cost device

high reliability

IGBT’s low cost circuit

fast switching

IGCT’s lowest cost device

lowest cost circuit

highest reliability

fastest switching

IGCT’s lowest cost device

lowest cost circuit

highest reliability

fastest switching

highest efficiency highest efficiency

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Turn off capability GTO <=> IGCT

7

0

12

34

56

0 1 2 3 4 5 6Snubber Capacitance (uF)

Tur

n-of

f C

apab

il ity

(k A

) IGCT (5SHY

35L4512)

GTO (5SGF

40L4502)

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Basic Topologies

VR

S3

S4

S5

S6

S1

S2

Ls

L

Cclamp

Dclamp

R

FWD

6

Clamp Network

S5S3S1

S6S2 S4

VDC

FWD1

IGCT Inverter

IGBT Inverter

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GTO, IGBT and IGCT phase-legs

IGBT

GTO

IGCTSchematics

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Application Specific Asymmertric IGCT

10

12

14

16

18

20

22

24

26

28

30

1.50 1.70 1.90 2.10 2.30 2.50 2.70 2.90 3.10 3.30 3.50

VT @ 3.3kA, 125°C [V]

Eo

ff @

2.8

kV, 3

.3kA

, 125

°C [W

s] homogeneous lifetime engineering

local lifetime engineering12

10

11

Technology curves of asymmetric 4 kA / 4.5 kV IGCT's

Type 12: Low on-state lossesType 10: Low total lossesType 11: Low switching losses

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Overview 4.5 kV asymmetric IGCT

Type low on-statelosses

(Type 12)

low total losses(Type 10)

low switching losses(Type 11)

Part N° 5SHY 35L4512 5SHY 35L4510 5SHY 35L4511

Junction temp.range

-40°C – 125°C -40°C – 125°C 10°C – 125°C

VTM @ 4 kA, 125°C 2V 2.7 V 3.5 V

EOFF @ 4 kA, 2.8 kV,125°C

37 Ws 22 Ws 17 Ws

Typical application AC/DC breakers(SSB)

Traction,Energy Management

High FrequencyMVDs

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-3000

-2000

-1000

0

1000

2000

3000

4000

5000

-0.5 0 0.5 1 1.5 2 2.5 3

t [s]

UA

K, I

A [V

, A]

-3.00E+01

-2.00E+01

-1.00E+01

0.00E+00

1.00E+01

2.00E+01

3.00E+01

4.00E+01

5.00E+01

UG

K [a

.u.]

Tj= 25°C

Tj = 125°C

UAK (25°C) UAK (125°C)

UGK

n

n

p

p

n

n

p

p

n

n

p

pn

n

p

p

t(25°C)

t(125°C)

Snubberless Operation

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Turn-off waferforms at different temperatures

0

1000

2000

3000

4000

8 9 10 11

t [s]

UA

K,

I A,

[V,

A]

Tj = 125°C

Tj = 75°C

Tj = 25°C

UAK

IA

IGCT type 5SHY 35L4511

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Turn-off waferforms @ Tj = 125°C

0

1000

2000

3000

4000

6 8 10 12 14

t [s]

I A,

UA

K,

[A,

V]

4510

4511

4512

IA

UAK

Signifficant reduction of tail current

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Turn-off waveforms = f(Tj)

0

1

2

3

4

5

kV

0

1

2

3

4

5

kA

40 60 80 100µs

ITGQ = 3200 A

VDM = 3470 V

VDC = 2800 V

0

1

2

3

4

5

kV

0

1

2

3

4

5

kA

40 60 80 100µs

VDM = 4280 V

ITG Q = 3250 A

VDC = 2800 V

5SHY 35L4510 @ Tj = -40°C

5SHY 35L4510 @ Tj = 125°C

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Simple GCT Construction

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VSI Test Circuit

LCLL i

RsDUT

LLoad

CCLVLC

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VSI test circuit waveforms

CS CS

IT

VDSP

VDM

VD

VG

tdon

IT

ITM

di/dt

0.9 VD

0.1 VD

VD

Turn-on Turn-off

VG

tr

tdoff

tdon1

SF

SF

0.4 ITGQ

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VSI test circuit parameters

Design these parameters to IGCT and diode capability: Stray inductance, LCL

di/dt limiting inductor, LI

Clamping capacitor, CCL

Clamping resistor, RS

These parameters are normally given by converter system design and does not normally influence IGCT performance or design: DC link capacitor, CDC

Load inductor, LLOAD

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Design criterions for di/dt limiting inductor

Component di/dt capability (SOA) IGCT Diode

Maximum surge current capability determined by LI and CDC

Diode switching losses Losses increase when LI value reduce

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Component di/dt capability

GCT di/dt capability: very high (compared to GTO) due to hard driven principle. very high turn-on pulse di/dt ( >500A/us) ensures

homogeneous, robust and “lossless” turn-on. More than 3000A/us has been applied in application.

Diode di/dt capability: Mostly the limiting part in IGCT VSI design This is especially true for snubberless applications which has

become standard in the market. Typical values are between 200 and 1000 A/us dependent on

wafer size and maximum required switching voltage.

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di/dt limiting inductor value

In VSI topologies, the diode turn-off di/dt capability mostly determines the size of the di/dt choke.

Li > (Vdc/(di/dtmax))

A bigger inductor value might be chosen in order to limit switching losses of the diode or to limit the surge current stress during shoot-through in a phase leg.

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Stray inductance design

The stray inductance, LCL, significantly influence

IGCT turn-off SOA and losses

Diode turn-off SOA and losses

Diode snap behaviour at low turn-off currents

Snap overvoltage

Noise emission due to high frequency oscillations

If LCL data sheet values are exceeded, SOA and specified turn-off losses are not valid.

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Turn-off losses versus stray inductance

V300 V800 V1500 I_300 I_800 I_1500

0

1

2

3

4

kV

0

1

2

3

kA

2 4 6 8 10 12 14

µs

Variation der Clampinduktivität: 300nH / 800nH / 1500nH

Testbedingungen:

Tj= 125°CITGQ= 3000AEl. Typ= 5SGY35L 4510 allg. Bedingungen: Vzk = 2kV

Ls = 3.7µHLs2 = 1.5µHRs = 0.5 OhmCcl = 7.6 µFDcl, Df = 5SDF10H4502

V300 V800 V1500 I_300 I_800 I_1500P300 P800 P1500 e300 e800 e1500

0.00

0.75

1.50

2.25

3.00

3.75

4.50kV

0.0

0.5

1.0

1.5

2.0

2.5

3.0kA

0

2

4

6

8

10

12MW

0

4

8

12

16

20

24J

5 10 15

µs

Eoff = f(Ls) Clampinduktivität: 300nH / 800nH / 1500nH

Testbedingungen:

Tj= 125°CITGQ= 3000AEl. Typ= 5SGY35L 4510 allg. Bedingungen: Vzk = 2kV

Ls = 3.7µHLs2 = 1.5µHRs = 0.5 OhmCcl = 7.6 µFDcl, Df = 5SDF10H4502

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The RLC clamp circuit

Analysis of damped parallel resonance circuit comprising LI, CCL and RS allows for an initial determination of CDC and RS values.

This analysis yield a reasonably good result when

CDC >> CCL

Stray inductances are small (LS1, LS2)

LLOAD >> LI

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VSI test circuit again - more details

Czk

Ls

Ls2

Uzk

Dcl

PrüflingRs

Ls1

Ccl

GCT

DQ

Last

Prüfling

Diode

I

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RLC circuit - 2. Order differential equation

Differential equation: LI CCL * (diL/dt)2 + (LI / RS) * (diL/dt) + iL = 0 (1)

Damping factor:

D = ( LI / CCL)/(2RS) ½ D 0.8 (2)

Clamping capacitor:

CCL > (LI *D4*IL)/(K1*ΔVCL) K1 0.9 (3)

Damping resistor:

Rs = ( Li / Ccl)/(2D) ½ (4)

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RLC circuit - why damping resistor?

To allow clamping capacitor to discharge before next switching transition (switching overvoltages does not add up to exceed component ratings).

Limit switching voltage overshoot VDM

Prevent current flowing in clamping diode after switching transition due to additional oscillations in RLC circuit (slightly undercritical damping - see formula 2)

Value obtianed with formula (4)

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RLC circuit - the clamping capacitor

Value obtained through formula (3) where

CCL > (LI *D4*IL)/(K1*ΔVCL) K1 0.9 (3)

D is damping factor (formula (2))

IL < ITGQM - maximum turn-off current of the application which has to be lower than maximum controllable turn-off current of the device according to specification

ΔVCL = VDM - VDCMAX which is the difference between the maximum allowed peak voltage and the maximum required dc link voltage of the application

K1 - this factors accounts for the influence of the stray inductance, LS2, which is never zero although kept as low as possible

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Block diagram - AC input

Tx

LogicMonitoring

Turn-Off

Circuit

Turn-On

Circuit

20VDC

Status Feedback(Light)

Gate

Kathode

24 ... 40VAC

or24 ... 40VDC

Rx

Command Signal(Light)

Internal Supply

LEDs

Stabilizer

Supply

AnodeMonitoring

Anode

For IGCT part numbers:

AS-IGCT: 5SHY 35L451x

RB-IGCT: 5SHZ 08F6000

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Power up - AC input AC input: Inrush current of about 9 A flows during about 150 ms.

Gate drive has current limiter on the board.

DC input: Gate drive does not provide inrush current limitation

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Isolation interface

The isolation requirements appears as a function of the maximum applied voltage of the specific application

Also the supplied power to the gate drive varies from project to project

Consequently isolation transformer is difficult to standardize

Gate drive has no onboard isolation transformer!

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Optical interface - receiver

Receiver for command signal Agilent, Type HFBR-2528

Pon CS Optical input power > -21 dBm Valid for 1mm plastic optical fibre (POF)

Poff CS Optical noise power < -40 dBm

tGLITCH Pulse width threshold 400 ns Max. pulse width without response

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Optical interface - transmitter

Transmitter for status feedback Agilent, Type HFBR-1528

Pon SF Optical output power > -19 dBm

Poff SF Optical noise power < -50 dBm

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Turn-on circuitry

V1

V2

D 1L1

D 3

K

G

C

20V

0V

V 3

D 2

L2

Turn on delay time: 2.75 - 2.85 us Less than 100 ns spread of delay

time

CH4: Command signal (HIGH: light)CH2: Turn-on currentCH1: VGK

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Turn-off circuit

V6

K

G

C

20V

0V

O FF

Turn off delay time: 2.75 - 2.85 us

Less than 100 ns spread of delay time

CH4: Command signal (HIGH: light)

CH1: VGK

CH2: On-state current [20 A/Div]

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On-state: Back-porch current circuit

V4

C

20V

0V

K

G

L3

L4C 1 V5

G H K


CH2: Back porch current [5 A/Div]

Chopper in current control mode

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On-state: Re-triggering (external)


CH1: VGK

CH2: Turn-on current 50 A/Div

Re-firing of turn-on pulse can be commanded via command input

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On-state: Re-triggering (internal)

CH1: VGK

CH2: Turn-on current [50 A/Div]

Gate voltage detection also controls re-triggering of turn-on pulse

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Power consumption (1): transferred power

Ptransfer = Vgint* Qgq(Itgq)*fs

Vgin : internal regulated voltage

Qgq(Itgq) : charge transferred to the power circuit

fs : switching frequency

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0 200 400 600 800 1'000 1'200 1'400

Itgq [A]

Pg

q [

W]

50Hz

500 Hz

1000 Hz

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Power consumption (2): dissipated power

05

101520253035

0 200 400 600 800 1000

Switching frequency [Hz]

po

wer

[W

]

0.1

0.5

1

duty cycle:

Standby

Turn-on pulse

Back porch current

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Thermal management

Calculated lifetime of on-board capacitors 20 years. With slightly forced air cooling (air velocity > 0.5 m/s). Strong air cooling allows for increased ambient temperature.

0

500

1000

1500

2000

2500

3000

250 350 450 550 650 750 850 950

FS [Hz]

ITGQ(AVG) [A]

Tamb(max) = 40 °C

Tamb(max) = 50 °CLimits for full lifetime operation for 5SHY 35L4510

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Diagnostics: Status feedbackO

pti

cal

Co

mm

and

Sig

nal

Inp

ut

Gat

e to

cath

od

evo

ltag

e

Su

pp

lyvo

ltag

e

Op

tica

lS

tatu

sF

eed

bac

ko

utp

ut

Gat

e d

rive

stat

us

LE

Ds

CS Status GK Status VGint SF

HIGH ON OK Inverse input signalCS

OK Power OK, Gate ON

HIGH OFF

(toff <10us)

OK Inverse input signalCS

OK Power OK, Gate ON

HIGH OFF

(toff >10us)

Don’t care CS FAIL Power OK, Fault

HIGH Don’t care FAIL CS FAIL Fault

LOW OFF OK Inverse input signalCS

OK Power OK, Gate OFF

LOW ON Don’t care CS FAIL Power OK, Gate ON, Fault

LOW Don’t care FAIL CS FAIL Gate OFF, Fault

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Diagnistics: Fault conditions

Loss of power supply On state hold-up time (no switching): >300 ms Off state hold-up time (no switching): >500 ms

Open circuit gate Supply overvoltage Short circuit gate

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Diagnostics: LED display

Pow

er O

K (

Gre

en)

Fau

lt (R

ed)

Gat

e O

N (

Yel

low

)

Gat

e O

ff (G

reen

)

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Series Connection with RC-snubber (2)

Design Trade-offs for RC-snubber

Dynamic turn-off voltage deviation: doffTGQ tICs

V 1

igct training

Documents

igcts abb switzerland

itgq abb switzerland

lload abb switzerland

shy 35l4511 abb switzerland

dvdt snubber abb switzerland

t s abb switzerland

igct turnoff

capability gto igct