ieee std 1581 vts 2011 slides

Download IEEE Std 1581   VTS 2011 slides

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  • 1. IEEE P1581Simplifying Connectivity Tests for Complex Memoriesand other Non-Boundary Scan Devices Heiko Ehrenberg, GOEPEL ElectronicsChair of IEEE P1581 working grouph.ehrenberg@ieee.org

2. IEEE P1581 - Introduction Scope: method for testing the interconnection of discrete,Low-cost complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1) is not feasible; Purpose:Improve interconnect test for discrete memory devices by specifying implementationrules for test logic and test mode entry/exit methods included in memory ICs; 2 3. Basic conceptPCB IEEE 1581 deviceOptional Test Pin Memory Test(if no TTM)Controller ControlTTM(optional)InputMemory Cells BusxIEEE 1149.1 Combinationaldevice(s) yTest Logic Output Bus 3 4. Key features Simple test logic implementation for memorydevices (and possibly other complex, slave-type components) No extra pins required Not relying on complex memory access cycles Fast test execution, small test vector set Usable with any access methodology(Boundary scan, functional, ICT) 4 5. Test mode control Dedicated test pin (TPN), or One of seven transparent test mode (TTM)control methods: Non-functional stimulus (NFS) Test entry or exit is triggeredby a condition on the pins Designated command codes (DCC)that would otherwise neverexist under normal Simultaneous input/output (SIO) functional conditions Clock frequency (CKF)These methods require Analog level (ANL)additional board-level Conditional power-up initiation (CPI) and/or controlling deviceDFT to be implemented Default power-up initiation (DPI)5 6. Test mode control - NFSTo TDOWE WE CSCSFrom TDIControlIEEE 1581Device Device 6 7. Test mode control - DCCTo TDO CD2 CD2 CD1 CD1 STB STB FromTDI ControlIEEE 1581 Device Device7 8. Test mode control - CPI ToTDOORWE WE CSCSORFrom TDI PCB DFT Non-VolatileControl ControlIEEE 1581Device DeviceTest mode is entered if a predetermined set of logical input states exist at a predetermined periodafter device power-up. 8 9. Test logic One of three dened test logic architectures: XOR (3-input XOR or XNOR gates) IAX (XOR, Inverters, and AND gates) XOR-2 (2-input XOR or XNOR gates) Or a custom test logic that satises rules in IEEEP15819 10. Test logic example - XORIEEE 1581 Memory DeviceXOR O1 Inputs 1-6XOR O2XOR O3XOR O4 10 11. Optional test functions Optional test functions accessible via testpattern partitioning Examples include: Reading a device identication (ID) Control line continuity test Built-in self test (BIST) access Other public or private commands 11 12. Status of IEEE P1581 Balloting completed Ballot group voted to accept IEEE P1581 IEEE needs to review and nalizeacceptance Ofcial adoption as IEEE Std 1581 expectedfor mid 201012