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C. BrandoleseC. Brandolese

IC TechnologiesIC Technologies

Programmable technologiesProgrammable technologies

ASIC technologiesASIC technologies



Classification

Programming

Connections

Cells



Hardware devices providing

Logic components

Gates, Flip-flops, Buffers

Connection lines

Such devices are said to be programmable since the

ready-made components can be connected

according to the design needs

There are several classes of programmable devices

PAL, PLA, ROM, GAL

CPLD

FPGA



Classification ca be made based on:

Programming

One-Time Programmable, OTP: Fuse, Antifuse

Reprogrammable: E2PROM, SRAM

Reconfigurable: SRAM

Connections

Global, local, hierarchical, programmable matrix

based

Cells

Simple, complex


ProgrammingProgramming

Programming technologies influence

Area

Minimum: Fuse/Antifuse

Maximum: SRAM

Programming time

Minimum : SRAM

Maximum : Fuse/Antifuse

Cost

Minimum : SRAM/Flash

Maximum : Fuse/Antifuse


Fuse (OTP)Fuse (OTP)

Lines are initially fully connected

Programming

Consists in burning (fuse) some of the connections

points and leave connected only the necessary ones

Is performed by means of a voltage higher than the

operating voltage

LINE1

LINE2

PROGRAM

FUSE

LINE1 LINE2

LINE1

LINE2

PROGRAM

FUSE

LINE1 LINE2


Antifuse (OTP)Antifuse (OTP)

Lines are initially fully disconnected

Programming

Consists in creating only the necessary connections

Is performed by means of a voltage higher than the

operating voltage

LINE1

LINE2ANTIFUSE

LINE1 LINE2LINE1 LINE2

LINE1

LINE2ANTIFUSE

SiO2

SiO2

METAL1

METAL2

SiO2

SiO2

METAL1

METAL2


EE22PROM (Reprogrammable)PROM (Reprogrammable)


Programming

Consists in depositing a charge on the floating gate so

that the transistors maintains a conducting channel

LINE1 LINE2

PROGRAM

SOURCE DRAIN

GATE

FLOATINGGATE

LINE1 LINE2

PROGRAM

SOURCE DRAIN

GATE

FLOATINGGATE

+ + + + +

CHANNEL

LINE1 LINE2 LINE1 LINE2


SRAM (Reprogrammable)SRAM (Reprogrammable)


Programming

Consists is storing a logical value (0 or 1) in a static

RAM cell

R/W

1


LINE1

LINE2

SRAM

CELL

R/W

1

LINE1

LINE2

SRAM

CELL


SRAM CellSRAM Cell

LINE1

Word

B' B

Vdd

GND


FLASH (Reprogrammable)FLASH (Reprogrammable)


Programming

Consists is storing a logical value (0 or 1) in a FLASH

cell

R/W

1


LINE1

LINE2

FLASH

CELL

R/W

1

LINE1

LINE2

FLASH

CELL


FLASH CellFLASH Cell

LINE1

LINE2

Word

B' B

Floaring Gate


ConnectionsConnections

Connections influence:

Area

Global connections require more area

Delays

Local connections very efficient for neighboring cells

Global connections very efficient for distant cells

Routability

Local connections peovide more flexibility and thus a

better routability

Complexity of routing algorithms increases when the

locality of connections increases


Global connectionsGlobal connections

Connections spanning a large portion of the die

Advantages

Distant cells are connected easily

Propagation delay easily predictable

Propagation delay relatively low for distant cells

Simpler architecture of the device

Disadvantages

Propagation delay high for neighboring cells

Each line is shared among several cells

Can be drived by a single cell and thus offers limited

flexibility


Global connectionsGlobal connections

The capacitance is that of the entire line

Almost fixed delay constant

The capacitance is acceptable for long wirings

No active elements

The laine resides on a single metal layer (no vias)

The capacitance is unacceptable for short wirings

AA

B B


Local connectionsLocal connections

Connections much shorter than the die size

Advantages

Very low delays for short connections

Neighboring elements are easily connected

Each line is shared among few cells

High flexibility

Disadvantages

Propagation delay is hard to predict

Propagation delay between distant cells is higher

compared to global connections due to vias and active

elements

More complex architecture of the device



Connection of neighboring cells

Capacintance depends on distance and is thus limited

No active elements

The line lays on two metal layers at most

Few or no vias

Only the necessary routing resources are used

No waste and higher routability

A

A B

B



Connection of distant cells

Capacintance depends on distance and is thus high

No active elements


Several vias are needed to span long distances

Parasitic capacitance is higher

Several local wiring resources are needed

A

A


Hierarchical connectionsHierarchical connections

Combines advantages of local and global schemes

Advantages

Uses local and fast lines for neighboring cells

Uses global and efficient lines for distant cells

Good flexibility

Disadvantages

Global resources are limited due to size constraints

Complexity of routing algorithms is higher

Propagation delays are harder to predict



Connection of neighboring cells

Capacintance depends on distance and is thus limited

No active elements


Few or no vias

Only the necessary routing resources are used

A

A



Connection of distant cells

Capacintance does not depend on distance and is thus limited and predictable

No active elements


Few or no vias

No local resources are wasted

A

B

B

A


Programmable Switch MatrixProgrammable Switch Matrix

PSMs have input/output ports connected to the

wiring resources of the device

Allow connecting an input port to several (possibly

all) output ports in a selective and programmable

way



Several connection schemes can be implemented

using PSMs

The local scheme is the simplest



A hierarchical scheme offers higher efficiency

PSMs are connected through linse of different length

1-length lines connect adjacents PSMs

N-lengthlines connects PSMs at a disstance equal to N

1-length lines

2-length lines

4-length lines


Simple cellsSimple cells

Limited number of I/Os

Sequential and combinatorial cells are distinct

Complex functions require several cells

Easier technology mapping algorithms

Complex and less efficient routing

Better optimization opportunities

LC LC LC LC

LC LC LC LC


Complex cellsComplex cells

High number of I/Os

Sequential and combinatorial elements in a cell

Complex functions require a sigle (or few) cell

Complex technology mapping algorithms

Simpler and more efficient routing

Less optimization opportunities

LC

LC


Programmable devicesProgrammable devices

Families

PAL, PLA, GAL

PLD, CPLD

FPGA


22--level programmable deviceslevel programmable devices

Used for functions in SoP/PoS two-levels forms

Provide

Fized number of I/Os

An AND-plane to construct implicants

An OR-plane, to sum implicant into functions

For electical reasons they also provide

Input and output buffers

InputBuffers

ANDPlane

ORPlane

OutputBuffersInput Output


22--level programmable deviceslevel programmable devices

Three major families

Programmable Logic Array (PLA)

AND- and OR-planes programmable

Only necessary implicants are built

Programmable Array Logic (PAL)

AND-plane only is programmable

Only necessary implicants are built

Read-Only Memory (ROM)

AND-plane pre-programmed with a decoder

All minterms are available


Programmable Logic ArrayProgrammable Logic Array

a

b

c

I1

I2

I3

I4

I5

I6

P1 P2 P3 P4

f1

f2

O1

O2

Input buffersInverters

AND Plane

OR Plane

Output buffers


Programmable Array Logic Programmable Array Logic

a

b

c

I1

I2

I3

I4

I5

I6

P1 P2 P3 P4

f1

f2

O1

O2

Input buffersInverters

AND Plane

OR Plane

Output buffers


ReadRead--Only MemoryOnly Memory

A ROM associates a word (output) to each address

(input)

Usually several functions are needed:

fi = fi(x1,x2,...,xn) i={1,2,...,t}

Using a different notation:

(x1,x2,...,xn) => (f1,f2,...,ft)

This form shows a transformation going from ann-tuple of inputs xi to a t-tuple of outputs fj

The address decoder generates all 2n minterms from the n input variables xi



Address decoder

The variables xi are the inputs

Outputs are all the minterms built on the input

variables

x1x2x3

000 = x1’x2’x3’

001 = x1’x2’x3

111 = x1x2x3



ROM

Output BuffersAddressDecoder

x1

x2

x3

000

001

010

111

f1 f2 f3 f4


Programmable Logic DevicesProgrammable Logic Devices

An extension of PLA-PAL devices

Provides an internal feedback network

Provides sequential elements

FeedbackClock

Outputselect

fiD Q

Q’

Outputenable

PrimaryInputs

FeedbackInput

fi


Generic Array LogicGeneric Array Logic

Further extension over PAL, PLA, PLD

Provides possibly several AND/OR planes

Provides complex cells for I/O and feedback routing

AND-ORPlanes

I/CLK

I

I

OLMC

OLMC

OLMC

I

I/O

I/O

I/O


Generic Array Logic Generic Array Logic

OLMCs (Output Logic Macro Cells) make the

architecture significantly flexible

Simple output

Input

OLMC O

OLMC I


Generic Array Logic Generic Array Logic

Output with internal feedback

Output with external feedback

OLMC O

OLMC I/O

OLMC O


Complex PLD Complex PLD

Evolution of PLDs and GALs

Characterized by

Global Connections

Lumped logic

With respect to PLDs and GALs

Are much larger (up to ~1M equivalent gates)

Available cells are much more complex

Several advantages

High density

High speed

Regular and easily programmable structure


Complex PLDComplex PLD

Input Interconnect Logic Flip-Flop Ouput


Field Programmable Gate ArrayField Programmable Gate Array

Field Programmable Gate Arrays (FPGAs) are the

most complex and powerful prorammable devices

currently available

Characterized by

Distributed connections

Distributed logic

With respect to PALs, PLAs, GALs and CPLDs

Are much larger (up to ~10-20M equivalent gates)

Cells have different complexity

Extremely flexible

Since few years provide fused components as well

Multipliers, memories, microprocessor cores, ...



LC

I/O

I/O

LC

LC

LC

LC

I/O

I/O

LC

LC

LC

LC

I/O

I/O

LC

LC

LC

LC

I/O

I/O

LC

LC

LC

LC

I/O

I/O

LC

LC

LC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O



Structured according to different philosopies

Simple cells

Better exploitation of the logic resources

Higher complexity of the interconnections structure

Routability problems

Complex cells

Complex functions use one or few cells

Poorer exploitation of logic resources

Simpler interconnections structure

Improved routability


Programmable devicesProgrammable devices

Commercial devices

Altera

Actel

Xilinx


Altera MAX3000A: DeviceAltera MAX3000A: Device


Altera MAX3000A: MacrocellAltera MAX3000A: Macrocell


Altera EP312: DeviceAltera EP312: Device


Altera EP312: MacrocellAltera EP312: Macrocell


Altera EP910: DeviceAltera EP910: Device


Altera EP910: MacrocellAltera EP910: Macrocell


Altera Flex10K: DeviceAltera Flex10K: Device


Altera Flex10K: EABAltera Flex10K: EAB


Altera Flex10K: LABAltera Flex10K: LAB


Altera Flex10K: LEAltera Flex10K: LE


Altera Apex20K: DeviceAltera Apex20K: Device


Altera Apex20K: MegaLABAltera Apex20K: MegaLAB


Altera Apex20K: LABAltera Apex20K: LAB


Altera Apex20K: DeviceAltera Apex20K: Device


Altera Apex20K: Product TermAltera Apex20K: Product Term


Altera Apex20K: ESB LogicAltera Apex20K: ESB Logic


Altera Apex20K: ESB MemoryAltera Apex20K: ESB Memory


Actel ACT3: DeviceActel ACT3: Device


Actel ACT3: I/O & Clock ModulesActel ACT3: I/O & Clock Modules


Actel ACT3: C & S ModulesActel ACT3: C & S Modules


Actel 40MX: DeviceActel 40MX: Device


Actel 40MX: D & I/O ModuleActel 40MX: D & I/O Module


Actel 40MX: S ModulesActel 40MX: S Modules


Actel 40MX: Memory ModuleActel 40MX: Memory Module


Actel ProASIC: DeviceActel ProASIC: Device


Actel ProASIC: CellActel ProASIC: Cell


Actel ProASIC: Local RoutingActel ProASIC: Local Routing


Actel ProASIC: Long RoutingActel ProASIC: Long Routing


Actel ProASIC: Very Long RoutingActel ProASIC: Very Long Routing


Xilinx XC3000: ConnectionsXilinx XC3000: Connections


Xilinx XC3000: Switch MatrixXilinx XC3000: Switch Matrix


Xilinx XC3000: IOBXilinx XC3000: IOB


Xilinx XC3000: CLBXilinx XC3000: CLB


Xilinx XC5200: DeviceXilinx XC5200: Device


Xilinx XC5200: Connections Xilinx XC5200: Connections


Xilinx XC5200: VersaBlockXilinx XC5200: VersaBlock


Xilinx XC5200: LC & IOBXilinx XC5200: LC & IOB


Xilinx XC9500: DeviceXilinx XC9500: Device


Xilinx XC9500: MacrocellXilinx XC9500: Macrocell


Xilinx Spartan: DeviceXilinx Spartan: Device


Xilinx Spartan: ConnectionsXilinx Spartan: Connections


Xilinx Spartan: CLBXilinx Spartan: CLB


Xilinx Spartan: IOBXilinx Spartan: IOB


Xilinx VirtexXilinx Virtex--II: Device II: Device


Xilinx VirtexXilinx Virtex--II: CLB II: CLB


Xilinx VirtexXilinx Virtex--II: Slice II: Slice


Xilinx VirtexXilinx Virtex--II: IOB II: IOB


ASICASIC

Standard Cell

Layout

Cells

Placement & Routing

Tecnology


Standard CellStandard Cell

Is the most used ASIC technology

More flexible than a gate array

Simpler that a full custom

Cells

Huge number (several hundreds) of commonly used

cells are available and are precharacterized

Layout

Regural structure organized into rows

Cells have a fixed height

Masks

A design requires a full set of masks


LayoutLayout

I/O cells

Core cells

Routing channels


Power supplyPower supply

Power supply and ground lines run adjacent to the

upper and lower side of cells rows

Cells provide axial symmetry that allows packing

rows and sharing VDD/VSS rails

VDD Rail

VSS Rail

VDD Rail

Common VSS Rail

VDD Rail


Cell structureCell structure

Five areas

VDD Rail: power supply

p-tub: pMOS, pull-up

Local wiring: I/O pins, local connections

n-tub: nMOS, pull-down

VSS Rail: groung

Local wiring

p-tub

n-tub

VDD Rail

VSS Rail


Cell geometryCell geometry

Fixed height

All rows have the same height

The two-dimensional layout process is decomposed into several almost one-dimensional placement problems

Variable width

Dpending on the cells complexity and MOS size

Symmetry

Cells are often symmetric w.r.t both x and y axes

No flip Flip y Flip X Flip xy


NAND3 GateNAND3 Gate

VDD rail

p-tub

Local wiring

n-tub

VSS rail

Pin


Each row is (logically) divided into adjacent sites

A cells always occupies an integral number of sites

Special cells called fillers create empty spaces into

the rows without beaking VDD/VSS rails

PlacementPlacement

site cell

site cell filler


RoutingRouting

Routing is constrained to predefined areas

Local wiring

Routing channels

Feedthrough over-the-cell routing

Local

wiring

Routing

channel

Routing

channel

Feedthrough


Routing gridRouting grid

The routing area is logically organized as a grid

Horizontal grid (corresponds to one layer)

Veritical grid (corresponds to a different layer)

The grid defines

Positions of the nets

Position of the cell pins


Routing layerRouting layer

Routing involves several dedicated metal layers

Horizontal nets

Vertical nets

Power supply and ground

Clock trees

...

This constraint

Significantly simplifies routing algorithms

Allows obtaining satisfactory routing density

Requires one via hole at each corner of a wire made

of several nets


Routing layerRouting layer

Verially aligned pins

Horizontally aligned pins

Unaligned pins

Unaligned constrained pins

1 layers

0 via

2 layers

2 vias

2 layers

2 vias

2 layers

4 vias


Clock treeClock tree

Distributes the clock(s) to flip-flops

The distance between flip-flops introduces a skew

Clock tree generation has the goals of:

Distributing the clock signal to all flip-flops

Maintain the skew below a given threshold (few ps)

In the simple case is a two-step process

Generation of an (sub)optimal geometry of the tree

H-tree, Steiner tree

Introduction of non-inverting buffers where necessary

To add a delay

To satisfy the constraints on maximum load and fan-out


Unbalanced clock tree: maximum skew 20ps

Balanced clock tree: maximum skew 0ps (ideal)

Clock treeClock tree

FF FF FF

10 10 105 5 5

delay = 15 delay = 25 delay = 35

FF FF FF

10 10 105 5 5

delay = 35 delay = 35 delay = 35

skew = 10 skew = 10

skew = 0 skew = 0

10

10

10

skew = 20

skew = 0


Standard cell librariesStandard cell libraries

A library is composed of tree main files

LEF: Library Exchange Format

Technology

Routing: layer description

Cells: size, type, placement, symmetries, pins

CTLF: Compiled Timing Library Format

Cell types and pins

Timing characterization of single cells

GCF: General Constraint Format

System-level (chip) timing constraints


Tecnology: Metal LayerTecnology: Metal Layer

LAYER METAL1

TYPE ROUTING;

DIRECTION HORIZONTAL;

WIDTH 0.80;

SPACING 0.60; SPACING 3.20 RANGE 20 200;

PITCH 1.80; OFFSET 0.0;

HEIGHT 1.195; THICKNESS 0.480;

RESISTANCE RPERSQ 0.07000000;

CAPACITANCE CPERSQDIST 0.0000289;

EDGECAPACITANCE 0.0000039000;

END METAL1

PITCH

WIDTH

SQUARE

SPACINGCLOSEST SEPARATION

VIA

METAL1


Tecnology: SitesTecnology: Sites

SITE xlite_core_site

SYMMETRY y;

CLASS core;

SIZE 1.80 BY 7.20;

END xlite_core_site

SYMMETRY Y

7.20

1.80

CLASS core

CLASS pad


Tecnology: CellsTecnology: Cells

MACRO AND2X1_TAX0

CLASS core;

ORIGIN 0.00 3.60 ;

SIZE 3.60 BY 7.20 ;

SYMMETRY x y ;

SITE xlite_core_site ;

PIN A

DIRECTION INPUT;

PORT

LAYER METAL11;

RECT 2.10 –1.50 2.70 -0.90;

END

END A

...

PIN B

...

END B

...

END AND2X1_TAX0

0 1.80 3.60

1.80

-1.80

3.60

0.00

5.40

1.80

7.20

3.60

ORIGIN

SIZE

(2.10,–1.50)

(2.70,–0.90)


Place & RoutePlace & Route


ASICASIC

Gate Array

Layout

Cells

Routing


Gate ArrayGate Array

Progressively less used technology

OTP devices offer competitive alternative

Cells

Are transistors, transistor pairs or NAND gates

Already fused on the partly manufactured die

Layout

Cells have fixed positions

Routing is extremely complex

Masks

A design requires only the the masks for wiring


Layout: Channeled (gate array)Layout: Channeled (gate array)

I/O cells

Logic cells

(transistors)

Routing channels


Layout: Channelless (sea of gates) Layout: Channelless (sea of gates)

I/O cells

Logic cells

(transistors)

I/O routing only


LayoutLayout

Channeled

Routing is constrained to channels only: easy

Limited cell/net density

No standard cells can be exploited

Channelless

Over-the-cell routing: complex

High cell/net density

Supports standard cells and RAM/ROM arrays

Today’s trend is to use almos only channelles gate

array


CellsCells

VDD rail

VSS rail

pMOS (small)

pMOS (small)

pMOS (large)

nMOS (small)

nMOS (small)

nMOS (large)

pins

vericaltracks


OverOver--thethe--cell routing cell routing

Horizontal

Grid

Vertical

Grid


ASICASIC

Full custom

Layout

Floorplanning

Macrocell


Full CustomFull Custom

Used only for very critical applications

Extremely complex and costly

Offers maximum flexibility and performance

Cells

No predefined cells

The physical design describes the complete geometry

Layout

Free

Placement and routing are extremely complex

Masks



LayoutLayout

I/O cells

Routing area

Macrocells


FloorplanningFloorplanning

The floorplan defines the position of macro blocks

Goals

Area minimization

Rotuing simplification (global and detailed phases)

Minimization of the average length of critical nets

Each macro block

Contains complex custom logic

Contains dedicated areas for routing

Estimated: Logic area is expanded by a factor

depending on the connection density

Exact: Logic elements are already placed


FloorplanningFloorplanning

A block is defined by

Dimensions: (x,y)

Area: A=xy

Aspect ratio: r=x/y

Can exploit

Rotation

Multiples of 90°

Reshaping

Fixed area

Constraints on the

aspect ratio

x

y A

Rotation Reshaping


MacrocellMacrocell

Combines

Flexibility and performance of full custom

Simplicity of standard cell

Cells

Standard cells

Full custom macrocells

Layout

Floorplan

Standard cell areas are organized into rows

Masks



MacrocellMacrocell

I/O cells

Routing channels

Standard cell area

Macrocells

(full custom)


ConclusioniConclusioni

Tecnologie a confonto


Tecnologie a confrontoTecnologie a confronto

Programmable

Programmable

Fixed

Variable

Variable

Tipo

celle

Fixed

Fixed

Fixed

Fixed height

Variable

Dimensione

celle

0.5

0.5

3-6

2-4

6-9

Sviluppo

months/Mgate

Posizione

celle

Frequenza

MHz

Densità

Mgates/cm2

Fixed5000.4FPGA

Fixed7501OTP PLD

Fixed10005Gate array

Fixed rows150010Standard cell

Variable400025Full custom


Tecnologie a confrontoTecnologie a confronto

1 10 100 1K 10K 100K 1M 10M 100M1 d

1 w

2 m

1 y

6 y

SSI

SSI

CPLD FPGA

Standard

Cell

Full

Custom

Design time / Complexity (gates)

1971: Intel 4004

2.2 Kgates

2000: Intel Pentium 4

42 Mgates


Intel 4004 Intel 4004 –– 2.2 Kgates2.2 Kgates

Intel Pentium 4 Intel Pentium 4 –– 42 Mgates42 Mgates

Intel 4004

Intel Pentium 4


Further readingFurther reading

1. Integrated circuit products

EBook

2. Basic Integrate Circuit Manufacturing

EBook

3. Xilinx Virtex 6 Family Overview

Xilinx Inc.

4. Xilinx Virtex 6 CLB Usage

Xilinx Inc.

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