hx8352-a t an v01 0803020 - openhacks · 2016. 5. 12. · hx8352-a(t) 240rgb x 480 dot, 262k color,...

HX8352-A(T) 240RGB x 480 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Preliminary version 01 February, 2008

( DOC No. HX8352-A(T)-AN )

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1. Introduction ............................................................................................................................................ 4 2. HX8352-A Chip Block Diagram .............................................................................................................. 5 3. HX8352-A PAD Assignment ................................................................................................................... 6

3.1 Alignment mark ............................................................................................................................ 7 3.2 Bump size..................................................................................................................................... 8

4. Pin Description..................................................................................................................................... 10 5. HX8352-A Reference FPC circuit (For CMO 3.0” LCD Panel) ............................................................. 14

5.1 Register-content interface mode............................................................................................... 14 5.1.1 MPU interface................................................................................................................... 14 5.1.2 RGB with Serial interface.................................................................................................. 15 5.1.3 MDDI interface.................................................................................................................. 16

6. LCD Power Generation......................................................................................................................... 18 6.1 LCD Power Generation Scheme................................................................................................ 18 6.2 Various Boosting Steps ............................................................................................................. 19

7. Software Configuration ........................................................................................................................ 20 7.1 Features...................................................................................................................................... 20

7.1.1 Display ............................................................................................................................. 20 7.1.2 Display module................................................................................................................. 20 7.1.3 Display/Control interface................................................................................................... 20 7.1.4 Others .............................................................................................................................. 21

7.2 GRAM mapping .......................................................................................................................... 22 7.3 Scan Function ............................................................................................................................ 23 7.4 Interface Mode............................................................................................................................ 24

7.4.1 Interface Mode Selection .................................................................................................. 24 7.4.2 Register-Content Interface Mode ...................................................................................... 24 7.4.3 Serial Data Transfer interface............................................................................................ 33 7.4.5 RGB Interface................................................................................................................... 34 7.4.6 MDDI Interface ................................................................................................................. 37

7.5 Initial Procedure......................................................................................................................... 61 7.5.1 Power Supply Setting Flow ............................................................................................... 61 7.5.2 Display on/off Setting Flow................................................................................................ 62 7.5.3 Standby Mode Setting Flow............................................................................................... 63

7.6 Initial code for reference............................................................................................................ 64 7.6.1 The reference setting of Normal Display for Register-Content Interface Mode ................... 64 7.6.2 The reference setting of into Standby mode for Register-Content Interface Mode .............. 70 7.6.3 The reference setting of exit Standby mode for Register-Content Interface Mode .............. 71

8. Revision History................................................................................................................................... 73

HX8352-A(T) 240RGB x 480 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver

List of Contents February, 2008



-P.1- Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. February, 2008

Figure 2. 1 HX8352-A block diagram.................................................................................................... 5 Figure 3. 1 HX8352-A pad assignment................................................................................................. 6 Figure 5. 2 Reference FPC circuit of Register-content interface mode’s MPU interface....................... 14 Figure 5. 3 Reference FPC circuit of Register-content interface mode’s RGB interface....................... 15 Figure 5. 4 Reference FPC circuit of Register-content interface mode’s MDDI interface ..................... 16 Figure 6. 1 LCD power generation scheme ........................................................................................ 18 Figure 6. 2 Various boosting steps ..................................................................................................... 19 Figure 7. 1 Memory Map. (240RGBx320)........................................................................................... 22 Figure 7. 2 MY, MX, MV Setting of 240RGB x 432 Dot ....................................................................... 23 Figure 7. 3 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 18( 6 + 6 + 6 ) Bit-Data Input (“BS2, BS1, BS0”=”011”).............................................................................................. 25 Figure 7. 4 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 16(5 + 6 + 5) Bit-Data Input (“BS2, BS1, BS0”=”100”) ............................................................................................. 25 Figure 7. 5 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 16 Bit-Data Input (“BS2, BS1, BS0”=”000”)........................................................................................................... 26 Figure 7. 6 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(16+2) Bit-Data Input (“BS2, BS1, BS0”=”001”) ............................................................................................. 26 Figure 7. 7 Input Data Bus and GRAM Data Mapping in 18-Bit Bus System Interface......................... 26 Figure 7. 8 Register read/write Timing in Parallel Bus System Interface (for I80 series MPU).............. 27 Figure 7. 9 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for I80 series MPU). 28 Figure 7. 10 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for I80 series MPU)....... 29 Figure 7. 11 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU) .......... 30 Figure 7. 12 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for M68 series MPU).......................................................................................................................................................... 31 Figure 7. 13 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for M68 series MPU)..... 32 Figure 7. 14 Data Write Timing in Serial Bus System Interface ........................................................... 33 Figure 7. 15 Data Read Timing in Serial Bus System Interface........................................................... 33 Figure 7. 16 RGB Interface Circuit Input Timing.................................................................................. 34 Figure 7. 17 18 bit / pixel Data Input of RGB Interface........................................................................ 35 Figure 7. 18 16 bit / pixel Data Input of RGB Interface........................................................................ 36 Figure 7. 19 Physical Connection of MDDI Host and Client ................................................................ 37 Figure 7. 20 MDDI Terminology.......................................................................................................... 37 Figure 7. 21 Example of Bi-Directional MDDI Communication ............................................................ 37 Figure 7. 22 MDDI Packet Structure................................................................................................... 38 Figure 7. 23 List of Supported MDDI Packet....................................................................................... 38 Figure 7. 24 MDDI Transceiver / Receiver State in Hibernation........................................................... 41 Figure 7. 25 Host-initiated Link Wakeup Sequence............................................................................. 42 Figure 7. 26 Client-initiated Link Wake-up Sequence.......................................................................... 43 Figure 7. 27 Sub Panel Interface........................................................................................................ 47 Figure 7. 28 Main/Sub Panel Selection Procedure.............................................................................. 48 Figure 7. 29 18-/16-Bit Sub Panel Interface Register Access Data Timing for i80 Series TFT Sub Panel.......................................................................................................................................................... 49 Figure 7. 30 9-/8-Bit Sub Panel Interface Register Access Data Timing for i80 Series TFT Sub Panel. 49 Figure 7. 31 18-/16-Bit Sub Panel Interface Register Access Data Timing for i80 Series TFT Sub Panel.......................................................................................................................................................... 50 Figure 7. 32 9-/8-Bit Sub Panel Interface Register Access Data Timing for m68 Series TFT Sub Panel.......................................................................................................................................................... 50 Figure 7. 33 18-Bit Sub Panel Interface Video Data Timing for i80 Series TFT Sub Panel ................... 51 Figure 7. 34 18-Bit Sub Panel Interface Video Data Timing for M68 Series TFT Sub Panel................. 51 Figure 7. 35 16-Bit Sub Panel Interface Video Data Timing for I80 Series TFT Sub Panel................... 52

HX8352-A(T) 240RGB x 480 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Figures

February, 2008




Figure 7. 36 16-Bit Sub Panel Interface Video Data Timing for m68 Series TFT Sub Panel................. 52 Figure 7. 37 9-Bit Sub Panel Interface Video Data Timing for i80 Series TFT Sub Panel..................... 53 Figure 7. 38 9-Bit Sub Panel Interface Video Data Timing for m68 Series TFT Sub Panel................... 53 Figure 7. 39 8-Bit Sub Panel Interface Video Data Timing for i80 Series TFT Sub Panel..................... 54 Figure 7. 40 8-Bit Sub Panel Interface Video Data Timing for m68 Series TFT Sub Panel................... 54 Figure 7. 41 18-/16-Bit Sub Panel Interface Register Access Data Timing for i80 Series STN Sub Panel.......................................................................................................................................................... 55 Figure 7. 42 9-/8-Bit Sub Panel Interface Register Access Data Timing for i80 Series STN Sub Panel 55 Figure 7. 43 18-/16-Bit Sub Panel Interface Register Access Data Timing for m68 Series STN Sub Panel.......................................................................................................................................................... 56 Figure 7. 44 9-/8-Bit Sub Panel Interface Register Access Data Timing for m68 Series STN Sub Panel.......................................................................................................................................................... 56 Figure 7. 45 18-Bit Sub Panel Interface Video Data Timing for i80 Series STN Sub Panel .................. 57 Figure 7. 46 18-Bit Sub Panel Interface Video Data Timing for m68 Series STN Sub Panel ................ 57 Figure 7. 47 16-Bit Sub Panel Interface Video Data Timing for i80 Series STN Sub Panel .................. 58 Figure 7. 48 16-Bit Sub Panel Interface Video Data Timing for m68 Series STN Sub Panel ................ 58 Figure 7. 49 9-Bit Sub Panel Interface Video Data Timing for i80 Series STN Sub Panel .................... 59 Figure 7. 50 9-Bit Sub Panel Interface Video Data Timing for m68 Series STN Sub Panel .................. 59 Figure 7. 51 8-Bit Sub Panel Interface Video Data Timing for i80 Series STN Sub Panel .................... 60 Figure 7. 52 8-Bit Sub Panel Interface Video Data Timing for m68 Series STN Sub Panel .................. 60 Figure 7. 53 Power Supply Setting Flow............................................................................................. 61 Figure 7. 54 Display On/Off Setting Flow............................................................................................ 62 Figure 7. 55 Standby Mode Setting Flow............................................................................................ 63

HX8352-A(T) 240RGB x 480 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Figures

February, 2008




Table 5. 1 Connected Capacitor ......................................................................................................... 17 Table 5. 2 Connected Schottkey diode ............................................................................................... 17 Table 7. 1 MY, MX, MV Setting of 240RGB x 432 Dot......................................................................... 23 Table 7. 2 Interface Mode Selection ................................................................................................... 24 Table 7. 3 MPU selection in Register-content Interface Circuit ............................................................ 24 Table 7. 4 Interface Selection in Register-content Interface Mode....................................................... 24 Table 7. 5 Data Pin Function for I80 Series CPU ................................................................................ 25 Table 7. 6 Data Pin Function for M68 Series CPU .............................................................................. 25 Table 7. 7 The Function of RS and R/W Bit bus.................................................................................. 33 Table 7. 8 EPL bit Setting and Valid ENABLE Signal .......................................................................... 34

HX8352-A(T) 240RGB x 480 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Table

February, 2008




1. Introduction

This document describes Himax’s HX8352-A is supports four types resolution driving controller. The HX8352-A is designed to provide a single-chip solution that combines a gate driver, a source driver, power supply circuit for 262,144 colors to drive a TFT panel with 240RGBx480 dots at maximum. The HX8352-A can be operated in low-voltage (1.65V) condition for the interface and integrated internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage follower circuit for liquid crystal driver. In addition, the HX8352-A also supports various functions to reduce the power consumption of a LCD system via software control. The HX8352-A is suitable for any small portable battery-driven and long-term driving products, such as small PDAs, digital cellular phones and bi-directional pagers. The HX8352-A supports three interface modes, include Command-Parameter interface mode, Register-Content interface mode and MDDI (Mobile Display Digital Interface) interface mode. The interface mode is selected by the external pins IFSEL0, P68, BS2~0 setting.

February, 2008

HX8352-A(T) 240RGB x 480 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Preliminary Version 01



-P.5-

HX8352-A(T) 240RGB x 480 dot, 262K-Color TFT Controller Driver

APPLICATION NOTE V01

Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. February, 2008

2. HX8352-A Chip Block Diagram

Figure 2. 1 HX8352-A block diagram



-P.6-

HX8352-A(T) 240RGB x 480 dot, 262K color, TFT Mobile Single Chip Driver



3. HX8352-A PAD Assignment

DU

MM

Y

DU

MM

Y

DU

MM

YG

48

0

G4

78

DU

MM

Y

DU

MM

YD

UM

MY

DU

MM

Y

G4

34

G4

36

DU

MM

Y

DU

MM

Y

DU

MM

Y

DU

MM

Y

G4

33

G4

35

G4

77

G4

79

DU

MM

YD

UM

MY

DU

MM

Y

Figure 3. 1 HX8352-A pad assignment



-P.7-




3.1 Alignment mark A_MARK (A1)

30um 30um 40um 30um 30um

30um

30um

40um

10um

20um

30um

30um

30um

40um

30um

30um

30um 20um10um

A1 (-9200,+370)

A_MARK (A2)

(+9200,+370)A2

30um30um40um30um30um

30um

30um

40um

10um

20um

30um

30um

30um

40um

30um

30um

30um20um10um



-P.8-




3.2 Bump size

Input PAD

Output PAD



-P.9-






-P.10-




4. Pin Description

Input Parts

Signals I/O Pin Number

Connected with Description

Select the MPU interface mode as listed below Use with IFSEL0=1 Register-content interface mode or MDDI interface mode. P68 BS2 BS1 BS0 Interface mode DB pins

0 0 0 0 16-bit bus interface, 80-system, 65K-Color

D17-D16: Unused, D15-D0: Data

0 0 0 1 16-bit bus interface, 80-system, 262K-color


0 0 1 0 18-bit bus interface, 80-system, 262K-color D17-D0: Data


D17-D8: Unused D7-D0: Data


D17-D8: Unused D7-D0: Data





1 0 1 0 18-bit bus interface, 68-system, 262K-Color D17-D0: Data


D17-D8:Unused D7-D0: Data


D17-D8:Unused D7-D0: Data

X 1 0 1 MDDI interface. STB+, STB-, DATA+, DATA-

P68, BS2,BS1,BS0 I 4 VSSD/ IOVCC

X 1 1 ID Serial bus IF + RGB interface

DNC_SCL, SDO,SDI, VSYNC, HSYNC, ENABLE, DOTCLK, DB17-0

IFSEL0 I 1 MPU

Interface format select pin IFSEL0 Interface Format Selection

0 Command-Parameter interface mode

1 Register-content interface mode or MDDI interface mode

EXTC I 1 MPU

Extended command set enable. (Only support Command-Parameter Interface mode à IFSEL0=0) Low: extended command set is discarded High: extended command set is accepted If operate in Register-content interface mode, the EXTC can be connected to IOVCC or VSSD.

RES_SEL1~0 I 2 MPU

Panel Resolution select pin. RES_SEL1 RES_SEL0 Panel Resolution

0 0 240RGB x 320 dot 0 1 240RGB x 400 dot 1 0 240RGB x 432 dot 1 1 240RGB x 480 dot

NCS I 1 MPU Chip select signal. Low: chip can be accessed; High: chip cannot be accessed. Must be connected to VSSD if not in use.

NWR_RNW I 1 MPU I80 system: Serves as a write signal and writes data at the rising edge. M68 system: 0: Write, 1: Read. Fix it to IOVCC or VSSD level when using serial buss interface.

NRD_E I 1 MPU I80 system: Serves as a read signal and read data at the low level. M68 system: 0: Read/Write disable, 1: Read/Write enable. Fix it to IOVCC or VSSD level when using serial buss interface.



-P.11-




Input Parts



DNC_SCL I 1 MPU

The signal for command or parameter select under parallel mode(i.e. Not serial interface): Low: command. High: parameter. When under serial interface, it servers as SCL.

BURN I 1 MPU Free Running mode If BURN=Hi, this can enable free running mode for burn in test. The display data alternates between full black and full white independent of input data in free running mode.

SDI I 1 MPU Serial data input. If not used, please let it connected to IOVCC or VSSD.

VSYNC I 1 MPU Frame synchronizing signal. Has to be fixed to IOVCC level if is not used.

HSYNC I 1 MPU Frame synchronizing signal. Has to be fixed to IOVCC level if is not used.

ENABLE I 1 MPU A data ENABLE signal in RGB I/F mode. Has to be fixed to VSSD level if unused (High active, if EPL=0).

DOTCLK I 1 MPU Dot clock signal. Has to be fixed to VSSD level if is not used.

NRESET I 1 MPU or reset circuit

Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied.

OSC I 1 Oscillation Resistor

Oscillator input for test purpose. If not used, please let it open or connected to VSSD.

VCOMR I 1 Resistor or open

A VcomH reference voltage. When adjusting VcomH externally, set registers to halt the VcomH internal adjusting circuit and place a variable resistor between VREG1 and VSSD. Otherwise, leave this pin open and adjust VcomH by setting the internal register of the HX8352-A.

VGS I 1 VSSD or external resistor

Connect to a variable resistor to adjusting internal gamma reference voltage for matching the characteristic of different panel used.

Output Part



S1~S720 O 720 LCD Output voltages applied to the liquid crystal.

G1~G480 O 480 LCD Gate driver output pins. These pins output VGH, VGL.(If not used, should be open)

VCOM O 1 TFT

common electrode

The power supply of common voltage in TFT driving. The voltage amplitude between VCOMH and VCOML is output. Connect this pin to the common electrode in TFT panel.

TE O 1 MPU Tearing effect output. If not used, please open this pin. SDO O 1 MPU Serial data output. If not use, let it to open.

NISD O 1 Open Image Sticking Discharge signal. This pin is used for monitoring image sticking discharge phenomena. When the NISD goes low, the VGL, Source and VCOM would be discharged to VSSA. When the NISD goes high, the VGL, Source and VCOM are normal operation.

PWM_OUT O 1 - Backlight On/Off control pin. If use ABC function, the pin can connect to external LED driver IC. The output voltage rage = 0~ IOVCC.

NWR2 O 1 Sub Panel 80-interface NWR signal output pin for Sub Panel E2 O 1 Sub Panel 68-interface Enable signal output pin for Sub Panel

NCS2 O 1 Sub Panel The signal is Chip select for Sub Panel. RS2 O 1 Sub Panel The signal is register index or register parameter select for Sub Panel



-P.12-




MDDI Interface Parts



STB+ STB- - 2 MDDI Host

MDDI Strobe differential signal input pins. STB+ pin for Strobe+, STB- pin for Strobe-. Connect to a terminal resistance (100Ω) between STB+ and STB-.

DATA+ DATA- - 2 MDDI Host

MDDI Data differential signal input pins. DATA+ pin for Data+, DATA- pin for Data-. Connect to a terminal resistance (100Ω) between DATA+ and DATA-.

MDDI_VCC P 1 Power Supply MDDI I/O power supply pin, 2.5V~3.3V.

MDDI_VSS P 1 Ground MDDI I/O ground pin.

MDDI_LDO O 1 Capacitor MDDI regulator output pin. Connect to a stabilizing capacitor between MDDI_VSS and MDDI_LDO

Input/Output Part



C11A,C11B C12A,C12B I/O 4 Step-up

Capacitor Connect to the step-up capacitors according to the step-up factor. Leave this pin open if the internal step-up circuit is not used.

CX11A, CX11B I/O 2 Step-up Capacitor

Connect to the step-up capacitors for step up circuit 1 operation. Leave this pin open if the internal step-up circuit is not used.

C21A,C21B C22A,C22B I/O 4 Step-up

Capacitor Connect these pins to the capacitors for the step-up circuit 2. According to the step-up rate. When not using the step-up circuit2, disconnect them.

DB17~0/ PD17~0

(DBS17~0) I/O 18 MPU

When Operates in system interface mode, it is used liked an 18-bit bi-directional data bus. 8-bit bus: use DB7-DB0 16-bit bus: use DB15-DB0 18-bit bus: use DB17-DB0 When Operation in RGB interface mode, it is an 18-bit bus RGB data bus. 16-bit bus: use PD15-PD0 18-bit bus: use PD17-PD0 If no used, please open the pins. If use MDDI interface, these pins are sub panel data bus (DBS17~DBS0). If no used, please open these pins.

GPIO7~0 I/O 8 - Standard Input/Output pin As for GPIO7 to 0 terminal, setting of an input and output direction is possible. If no used, please open these pins.

Power Part



IOVCC P 1 Power Supply Digital IO Pad power supply, 1.65V~3.3V

VCC P 1 Power Supply Digital power supply, 2.3V~3.3V

VCI P 1 Power Supply Analog power supply, 2.3V~3.3V

VSSD P 1 Ground Digital ground VSSA P 1 Ground Analog ground

VDDD O 1 Stabilizing Capacitor

Output from internal logic voltage (1.6V). Connect to a stabilizing capacitor



-P.13-




Power Part



REGVDD I 1 MPU

If REGVDD = high, the internal VDDD regulator will be turned on. If REGVDD = low, the internal VDDD regulator will be turned off, VDDD should connect to external power supply, the voltage range 1.65~1.95V. Must be connected to IOVCC or VSSD.

VBGP - 1 Open Band Gap Voltage. Let it to be open.

VREG1 P 1 Stabilizing Capacitor Internal generated stable power for source driver unit.

VREG3 P 1 Stabilizing Capacitor A reference voltage for VGH&VGL.

VCOMH P 1 Stabilizing capacitor

Connect this pin to the capacitor for stabilization. This pin indicates a high level of VCOM amplitude generated in driving the VCOM alternation.

VCOML P 1 Stabilizing capacitor

When the VCOM alternation is driven, this pin indicates a low level of VCOM amplitude. Connect this pin to a capacitor for stabilization.

VCL P 1 Stabilizing capacitor A negative voltage for VCOML circuit, VCL=-VCI

VLCD P 1 Stabilizing capacitor

An output from the step-up circuit1. Connect to a stabilizing capacitor between VSSA and VLCD. Place a schotkey barrier diode (see “configuration of the power supply”).

VGH P 1 Stabilizing capacitor

An output from the step-up circuit2.or 4 ~ 6 time the VCI level. The step-up rate is determined with BT2-0 bits. Connect to a stabilizing capacitor between VSSD and VGH. Place a schottkey barrier diode between VCI and VGH. Place a schottkey barrier diode (see “configuration of the power supply”).

VGL P 1 Stabilizing capacitor

An output from the step-up circuit2.or –3~ -5 time the VCI level. The step-up rate is determined with BT2-0 bits. Connect to a stabilizing capacitor between VSSD and VGL. Place a schottkey barrier diode between VSSD and VGL. Place a schottkey barrier diode (see “configuration of the power supply”).

Test Pin and Others



TEST3-1 I 3 GND Test pin input (Internal pull low) TS8~0 O 9 Open A test pin. Disconnect it. VTEST O 1 Open A test pin. Disconnect it.

TEST_MODE I 1 Open MDDI test pin. Must be left open. TEST_PAD_DRV I 1 Open MDDI test pin. Must be left open.

TEST_MODE_CLK I 1 Open MDDI test pin. Must be left open.

DUMMYR1-2 - 2 Open Dummy pads. Available for measuring the COG contact resistance. DUMMYR1 and DUMMYR2 are short-circuited within the chip.

DUMMYR3-4 - 2 Open Dummy pads. Available for measuring the COG contact resistance. DUMMYR3 and DUMMYR4 are short-circuited within the chip.

DUMMY - 112 Open Dummy pads IOGNDDUM1-10 O 10 Open Dummy pin between MDDI pin, Leave them open.

PADA0,PADB0 I 2 MPU Test pin for display glass break detection. If not used, please open these pins.

PADA1~ PADA4, PADB1~ PADB4 I 8 MPU Test pin for chip attachment detection.

If not used, please open these pins.

DMY_IOVCC O 10 - Dummy IOVCC output pads, Internal connected to IOVCC and only for external Hardware setting pin use. If not used, please open these pins.

DMY_GND O 8 - Dummy GND output pads, Internal connected to VSSD and only for external Hardware setting pin use. If not used, please open these pins.




HX8352-A(T) 240RGB x 480 dot, 16,777,216-Color TFT Controller Driver


5. HX8352-A Reference FPC circuit (For CMO 3.0” LCD Panel) 5.1 Register-content interface mode

5.1.1 MPU interface

VC

OM

NIS

D

IOV

CC

NC

SD

NC

_SC

LIO

VC

C

BUR

N

BURNBURN

DB

13

DB

11

NR

D_E

GN

D

DN

C_S

CL

NW

R_R

NW

NR

ES

ET3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description".

NC

S

2. SDO pin is output pin. SDO pin must be left floating when no use.

VLC

D

VG

H

VC

LVC

I

VR

EG

1

VG

LIOV

CC

VR

EG

3

VC

OM

R

VC

OM

VB

GP

VC

OM

H

VD

DD

VC

OM

L

BS2

TE

P68

BS0

BS1

OS

C

VBGPVBGP

BS

2

DNC_SCLDNC_SCL

TE

VCOMVCOM

NR

ES

ET

NR

D_E

NW

R_R

NW

P68

DB

9

DB

11

DB

8

DB

14

NCSNCS

DB

13

DB

15

DB

7

P68P68

DB

10

DB

16

R30603/0R

DB

5

DB

17

DB

6

DB

12

DB

3

DB

1

VDDDVDDD

BS

0

DB

2

DB

4

DB0

BS

1

NWR_RNWNWR_RNW

4. When VCI=VCC=IOVCC, thne MDDI_VCC can connect with them together.

VLCDVLCD

BS1BS1

VCIVCI

BS2BS2

VCOMHVCOMH

P68 BS1

16-bit bus interface, 80-system, 65K-Color

BS2

00

BS0

IOVCCIOVCC

Interface mode0

TETE

00

0

VCOMLVCOML

10

18-bit bus interface, 80-system, 262K-Color16-bit bus interface, 80-system, 262K-Color

VCOMRVCOMR

VCLVCL

00

MD

DI_

VCC

0

1 0

0

NRESETNRESET

VSSD

11

VC

C

0 8-bit bus interface, 80-system, 65K-Color8-bit bus interface, 80-system, 262K-Color

1

VSSA

00

1

1 00 0

VGLVGL

01

1000

1

1

VREG3VREG3

10 1

1 001


8-bit bus interface, 68-system, 262K-Color18-bit bus interface, 68-system, 262K-Color16-bit bus interface, 68-system, 262K-Color


IOV

CC

NC

S

DB

15

VC

I

NR

ES

ET

NRD_ENRD_E

VC

OM

R

DB

9D

B8

VREG1VREG1

DB

12

DB

5D

B4

DB

10

DB

14

VGHVGH

DB

6D

B7

NW

R_R

NW

DB

3

R20603/0R

DB

2D

B1

NR

D_E

DB

0

GN

D

GN

D

DN

C_S

CL

OSCOSC

BS0BS0

VC

C

VCCVCC

DB

16D

B17

TE

VD

DD

VCI

D1RB521S-30

12

VR210K(OPEN)

21

3

C70603/1u/10V

C110603/1u/10V

C11AB0603/2.2u/10V

C90805/1u/25V

C130603/1u/10V

D2RB521S-30

1 2

C21AB0603/1u/10V

IOVCC

C100805/1u/25V

TR

206

03/1

00R

C50603/1u/10V

TR

106

03/1

00R

OS

C

C60603/1u/10V

C20603/1u/10V

VR

EG1

PW

M_O

UT

C120603/1u/10V

C40603/1u/10V

C10603/1u/10V

C30603/1u/10V

C22AB0603/1u/10V

CX11AB0603/2.2u/10V

NIS

D

C80805/1u/25V

VLC

D

NISDNISD

C12AB0603/1u/10V

VC

OM

LV

CO

MH

VCI

D3RB521S-30

12

VG

H

VC

OM V

CL

VG

LV

REG

3

VCC

R10603/0R

5. If FPC's size is very smaller, then user can remove Diode of VGH and VLCD.

VG

S

VR1

10K(OPEN)

21

3

MD

DI_

VC

C

PW

M_O

UT

BS

0

P68

BS

2B

S1

VCI

U1

CMO F03001

VS

SA

4

VS

SA

5

VS

SA

6

IOV

CC

10

VS

SD

7

IOV

CC

11

BS

013

BS

215

NR

ES

ET

17

VS

YN

C18

HS

YN

C19

DO

TC

LK20

EN

AB

LE21

DB

1722

DB

1623

DB

1524

DB

1425

DB

1326

DB

1227

DB

1128

DB

1029

DB

930

DB

831

DB

732

DB

633

DB

534

DB

435

DB

336

DB

237

DB

138

DB

039

SD

O40

SD

I41

NW

R_R

NW

43

DN

C_S

CL

45

NR

D_E

42

E2

52

NW

R2

53

PW

M_O

UT

54

P68

16

VG

S78

GP

IO0

55

GP

IO1

56

GP

IO2

57

GP

IO3

58

GP

IO4

59

GP

IO5

60

GP

IO6

61

GP

IO7

62

MD

DI_

VCC

65

MD

DI_

VSS

67

IOG

ND

DU

M3

69

ST

B+

70

IOG

ND

DU

M4

71

ST

B-

72

IOG

ND

DU

M5

73

BS

114

RS

250

NC

S46

NIS

D47

BU

RN

48

TE

49

NC

S2

51

OS

C63

DA

TA

+74

IOG

ND

DU

M6

75

DA

TA

-76

IOG

ND

DU

M7

77

VC

OM

79

VC

OM

H83

VC

OM

L81

VR

EG

184

VC

OM

R85

VC

L87

VG

H88

VG

L90

VR

EG

392

VLC

D93

CX

11B

95

CX

11A

97

C11

B10

0

C11

A10

2

VC

C10

3

VC

I10

4

C12

B10

6

C12

A10

8

C21

B11

0

C21

A11

3

C22

B11

6

C22

A11

9

EX

TC

12

IFS

EL0

44

MD

DI_

LDO

66

VD

DD

3V

DD

D2

VC

OM

1

VS

SD

8

VS

SD

9

MD

DI_

VCC

64

MD

DI_

VSS

68

VC

OM

80

VC

OM

L82

VC

L86

VG

H89

VG

L91

VLC

D94

CX

11B

96

CX

11A

98

C11

B99

C11

A10

1

VC

I10

5

C12

B10

7

C12

A10

9

C21

B11

1

C21

B11

2

C21

A11

4

C21

A11

5

C22

A12

0

C22

A12

1

C22

B11

7

C22

B11

8

VC

OM

122

VS

SD

VS

SA

GND1GND

GND2GND

BU

RN

J1

FPC56-0.5-4.0L

VC

I1

VC

I2

GN

D3

VCC

4

IOVC

C5

nRE

SET

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB

915

DB

816

DB

717

DB

618

DB

519

DB

420

DB

321

DB

222

DB

123

DB

024

nRD

_E25

NW

R_R

NW

26

DN

C_S

CL

27

nCS

28

FLM

29

GN

D30

NC

31

VS

YNC

32

HS

YNC

33

DO

TC

LK34

EN

ABL

E35

SDO

36

SD

I37

NC

38

MD

DI_

VCC

39

MD

DI_

VSS

40

STB

+41

STB

-42

MD

DI_

VSS

43

DA

TA+

44

DAT

A-

45

MD

DI_

VSS

46

RE

S_S

EL1

47

RE

S_S

EL0

48

EXT

C49

P68

50

BS

251

BS

152

BS

053

GN

D54

BL+

/NC

55

BL_

GN

D/N

C56

1. VCI, IOVCC, VCC are separated from different power source to get better display quality.

VC

OM

Figure 5. 1 Reference FPC circuit of Register-content interface mode’s MPU interface





APPLICATION NOTE V015.1.2 RGB with Serial interface

BUR

N

BURNBURN

VCO

M

NIS

DN

CS

DN

C_S

CL

IOVC

C

DB

13

DB

11

ENA

BLE

GN

D

NR

ESE

T

VSYN

C

SDO

HSY

NC3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description".

DO

TC

LK

2. SDO pin is output pin. SDO pin must be left floating when no use.

VCL

VLC

D

VREG

1

VGL

VGH

VCO

MR

VCI

VBG

P

IOV

CC

VREG

3

VDD

D

VCO

ML

VCO

M

VCO

MH

TE

OSC

SDI

HSYNCHSYNC

VBGPVBGP

TE

SD

I

VCOMVCOM

NR

ESE

T

IOVCC

DB

9

DB

11

DB

8

DB

13D

B14

DB

15

DB

7

DB

10

DB

16

R30603/0R

DB

5

DB

17

DB

6

DB

12

DB

3

BS0

DB

1

VDDDVDDD

DB

2

DB

4

DB0

ENABLEENABLE

VLCDVLCD

VCIVCI VCOMH

VCOMH

NC

S

DN

C_S

CL

IOVCCIOVCC

NCSNCS

DNC_SCLDNC_SCL

TETE

VCOMLVCOML

SDISDI

VCOMRVCOMR

VCLVCL

DOTCLKDOTCLK

MD

DI_

VC

C

VSSD

NRESETNRESET

SDOSDO

VCC

VSSA

VGLVGL

VREG3VREG3

IOV

CC

NC

S

NR

ESET

DB

15

VC

I

DB8

VCO

MR

DB9

VREG1VREG1

DB

12

DB5

DB4DB

10

DB

14

DB6

DB7

VGHVGH

DB1

DB3

DB2

R20603/0R

DB0

GN

D

GN

D

OSCOSC

VSY NCVSY NC

VCC

VCCVCC

DB

17D

B16

VCI

TE

VD

DD

D1RB521S-30

12

VR210K(OPEN)

21

3

C70603/1u/10V

C110603/1u/10V

C11AB0603/2.2u/10V

C90805/1u/25V

C130603/1u/10V

D2RB521S-30

1 2

C21AB0603/1u/10V

C100805/1u/25V

TR

206

03/1

00R

C50603/1u/10V

OSC

TR

106

03/1

00R

C60603/1u/10V

C20603/1u/10V

PW

M_O

UT

VRE

G1

C120603/1u/10V

C40603/1u/10V

C10603/1u/10V

C30603/1u/10V

C22AB0603/1u/10V

CX11AB0603/2.2u/10V

VLC

D

NIS

D

C80805/1u/25V

NISDNISD

C12AB0603/1u/10V

VCO

ML

VCO

MH

VCI

D3RB521S-30

12

VGH

VC

OM VC

L

VGL

VCC

VRE

G3

R10603/0R

VG

S

VR1

10K(OPEN)

21

3

MD

DI_

VCC

PW

M_O

UT

VCI

VSS

D

VSS

A

BS0

U1

CMO F03001

VSSA

4

VSSA

5

VSSA

6

IOV

CC

10

VSSD

7

IOV

CC

11

BS0

13

BS2

15

NR

ESE

T17

VSYN

C18

HS

YNC

19

DO

TC

LK20

ENAB

LE21

DB

1722

DB

1623

DB

1524

DB

1425

DB

1326

DB

1227

DB

1128

DB

1029

DB

930

DB

831

DB

732

DB

633

DB

534

DB

435

DB

336

DB

237

DB

138

DB

039

SDO

40

SDI

41

NW

R_R

NW

43

DN

C_S

CL

45

NR

D_E

42

E252

NW

R2

53

PWM

_OU

T54

P68

16

VGS

78

GP

IO0

55

GP

IO1

56

GP

IO2

57

GP

IO3

58

GP

IO4

59

GP

IO5

60

GP

IO6

61

GP

IO7

62

MD

DI_

VCC

65

MD

DI_

VSS

67

IOG

ND

DU

M3

69

STB+

70

IOG

ND

DU

M4

71

STB-

72

IOG

ND

DU

M5

73

BS1

14

RS

250

NC

S46

NIS

D47

BUR

N48

TE49

NC

S2

51

OS

C63

DA

TA+

74

IOG

ND

DU

M6

75

DA

TA-

76

IOG

ND

DU

M7

77

VCO

M79

VCO

MH

83VC

OM

L81

VREG

184

VCO

MR

85

VCL

87

VGH

88

VGL

90

VREG

392

VLC

D93

CX

11B

95

CX

11A

97

C11

B10

0

C11

A10

2

VCC

103

VCI

104

C12

B10

6

C12

A10

8

C21

B11

0

C21

A11

3

C22

B11

6

C22

A11

9

EXTC

12

IFSE

L044

MD

DI_

LDO

66

VDD

D3

VDD

D2

VCO

M1

VSSD

8

VSSD

9

MD

DI_

VCC

64

MD

DI_

VSS

68

VCO

M80

VCO

ML

82

VCL

86

VGH

89

VGL

91

VLC

D94

CX

11B

96

CX

11A

98

C11

B99

C11

A10

1

VCI

105

C12

B10

7

C12

A10

9

C21

B11

1

C21

B11

2

C21

A11

4

C21

A11

5

C22

A12

0

C22

A12

1

C22

B11

7

C22

B11

8

VCO

M12

2

GND1GND

GND2GND

J1

FPC56-0.5-4.0L

VC

I1

VC

I2

GN

D3

VC

C4

IOV

CC

5

nRE

SET

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB

915

DB

816

DB

717

DB

618

DB

519

DB

420

DB

321

DB

222

DB

123

DB

024

nRD

_E25

NW

R_R

NW

26

DN

C_S

CL

27

nCS

28

FLM

29

GN

D30

NC

31

VSY

NC

32

HSY

NC

33

DO

TC

LK34

EN

ABL

E35

SD

O36

SD

I37

NC

38

MD

DI_

VC

C39

MD

DI_

VSS

40

STB

+41

STB-

42

MD

DI_

VSS

43

DA

TA+

44

DAT

A-45

MD

DI_

VSS

46

RES

_SE

L147

RES

_SE

L048

EXTC

49

P68

50

BS2

51

BS1

52

BS0

53

GN

D54

BL+/

NC

55

BL_G

ND

/NC

56


VCO

M

HS

YNC

DO

TCLK

VSY

NC

SD

OS

DI

EN

ABLE

VSY

NC

DO

TCLK

EN

ABL

E

VSY

NC

4. When VCI=VCC=IOVCC, thne MDDI_VCC can connect with them together.5. If FPC's size is very smaller, then user can remove Diode of VGH and VLCD.

0 01 1

SPI IDBS0

DN

C_S

CL

SD

O

Figure 5. 2 Reference FPC circuit of Register-content interface mode’s RGB interface





APPLICATION NOTE V015.1.3 MDDI interface

NRESETNRESET

VSSA

VGLVGL

VREG3VREG3

E2E2

VCO

MR

VREG1VREG1

VGHVGH

R20603/0R

OSCOSC

VC

C

VCCVCC

VDD

D

VCI

D1RB521S-30

12

VR310K(OPEN)

21

3

C70603/1u/10V

C110603/1u/10V

C11AB0603/2.2u/10V

ST

B+

C90805/1u/25V

DA

TA-

DA

TA+

ST

B-

C130603/1u/10V

D2RB521S-30

1 2

C21AB0603/1u/10V

C100805/1u/25V

TR

506

03/1

00R

C50603/1u/10V

OSC

TR

606

03/1

00R

C60603/1u/10V

C20603/1u/10V

VRE

G1

C120603/1u/10V

C40603/1u/10V

C10603/1u/10V

C30603/1u/10V

C22AB0603/1u/10V

CX11AB0603/2.2u/10V

NIS

DVL

CD

C80805/1u/25V

NISDNISD

C12AB0603/1u/10V

VCO

ML

VCO

MH

VCI

VGH

D3RB521S-30

12

VCL

VCO

M

VGL

VRE

G3

VCC

R10603/0R

VG

S

VR4

10K(OPEN)

21

3

PWM

_OU

T

VCI

VSS

D

VSS

A

U1

CMO F03001

VSS

A4

VSS

A5

VSS

A6

IOVC

C10

VSS

D7

IOVC

C11

BS0

13

BS2

15

NR

ESE

T17

VSY

NC

18

HS

YNC

19

DO

TC

LK20

EN

ABLE

21

DB

1722

DB

1623

DB

1524

DB

1425

DB

1326

DB

1227

DB

1128

DB

1029

DB

930

DB

831

DB

732

DB

633

DB

534

DB

435

DB

336

DB

237

DB

138

DB

039

SD

O40

SD

I41

NW

R_R

NW

43

DN

C_S

CL

45

NR

D_E

42

E2

52

NW

R2

53

PW

M_O

UT

54

P68

16

VG

S78

GP

IO0

55

GP

IO1

56

GP

IO2

57

GP

IO3

58

GP

IO4

59

GP

IO5

60

GP

IO6

61

GP

IO7

62

MD

DI_

VC

C65

MD

DI_

VS

S67

IOG

ND

DU

M3

69

STB

+70

IOG

ND

DU

M4

71

STB

-72

IOG

ND

DU

M5

73

BS1

14

RS

250

NC

S46

NIS

D47

BU

RN

48

TE

49

NC

S2

51

OS

C63

DA

TA+

74

IOG

ND

DU

M6

75

DA

TA-

76

IOG

ND

DU

M7

77

VC

OM

79

VC

OM

H83

VC

OM

L81

VR

EG1

84

VC

OM

R85

VC

L87

VG

H88

VG

L90

VR

EG3

92

VLC

D93

CX

11B

95

CX

11A

97

C11

B10

0

C11

A10

2

VC

C10

3

VC

I10

4

C12

B10

6

C12

A10

8

C21

B11

0

C21

A11

3

C22

B11

6

C22

A11

9

EXT

C12

IFS

EL0

44

MD

DI_

LDO

66

VD

DD

3V

DD

D2

VC

OM

1

VSS

D8

VSS

D9

MD

DI_

VC

C64

MD

DI_

VS

S68

VC

OM

80

VC

OM

L82

VC

L86

VG

H89

VG

L91

VLC

D94

CX

11B

96

CX

11A

98

C11

B99

C11

A10

1

VC

I10

5

C12

B10

7

C12

A10

9

C21

B11

1

C21

B11

2

C21

A11

4

C21

A11

5

C22

A12

0

C22

A12

1

C22

B11

7

C22

B11

8

VC

OM

122

GND1GND

GND2GND

BUR

N


VC

OM

C140603/1u/10V

IOVCC

IOV

CC

E2

IOV

CC

DBS

11

DBS

13

DBS

15

DB

S8

DB

S9

DB

S5

DBS

14

DBS

12

DB

S4

DB

S7

DBS

10

DB

S3

DB

S6

DB

S1

DB

S2

NW

R2

DBS

16

DB

S0

RS2

DBS

17

NC

S2

6. STB+, STB- and Data+, Data- need shading with ground. 7. STB+, STB- and Data+, Data- need layout the same length.

5. If FPC's size is very smaller, then user can remove Diode of VGH and VLCD.4. When VCI=VCC=IOVCC, thne MDDI_VCC can connect with them together.

|--------------------------------------------|| |To Sub Panel Interface

DA

TA

+D

AT

A-

ST

B+

ST

B-

DB

S11

MD

DI_

VC

C

GN

D

DB

S13

IOV

CC

NC

S2

VC

CVC

I

DB

S15

DBS

9D

BS8

NR

ES

ET

DB

S12

DBS

5

BURNBURN

BUR

N

DBS

4

DB

S10

DB

S14

DBS

3

DBS

6D

BS7

DBS

1 NW

R2

RS

2

DBS

0

DBS

2 GN

D

GN

D

RE

S_SE

L0

TE

DB

S17

DB

S16

PW

M_O

UT

RE

S_SE

L1

J1

FPC56-0.5-4.0L

VC

I1

VC

I2

GN

D3

VC

C4

IOV

CC

5

nRE

SET

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB9

15

DB8

16

DB7

17

DB6

18

DB5

19

DB4

20

DB3

21

DB2

22

DB1

23

DB0

24

nRD

_E25

NW

R_R

NW

26

DN

C_S

CL

27

nCS

28

FLM

29

GN

D30

NC

31

VSY

NC

32

HS

YN

C33

DO

TC

LK34

EN

AB

LE35

SD

O36

SD

I37

NC

38

MD

DI_

VC

C39

MD

DI_

VSS

40

ST

B+41

STB

-42

MD

DI_

VSS

43

DA

TA+

44

DA

TA-

45

MD

DI_

VSS

46

RES

_SE

L147

RES

_SE

L048

EXT

C49

P68

50

BS2

51

BS1

52

BS0

53

GN

D54

BL+

/NC

55

BL_

GN

D/N

C56

E2

VC

OM

NIS

D

IOV

CC

IOV

CC

E2 RS2

NW

R2

NR

ESE

T

NC

S2

3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description".

VC

L

VLC

D2. SDO pin is output pin. SDO pin must be left floating when no use.

VG

L

VG

HVC

I

VR

EG1

IOVC

C

VR

EG3

VC

OM

R

VC

OM

L

VC

OM

VBG

P

VC

OM

H

VD

DD

TE OSC

VBGPVBGP

TE

RS2RS2

NR

ESE

T

VCOMVCOM

NCS2NCS2

R30603/0R

VDDDVDDD

NWR2NWR2

VLCDVLCD

VCIVCI VCOMH

VCOMH

IOVCCIOVCC

TETE

VCOMLVCOML

VCOMRVCOMR

VCLVCL

MD

DI_

VC

C

VSSD

Figure 5. 3 Reference FPC circuit of Register-content interface mode’s MDDI interface




HX8352-A 240RGB x480 dot, 262K-Color TFT Controller Driver

APPLICATION NOTE V01 The specification of FPC circuit and pins connection is shown as following table:

Pad Name Connection Typical capacitance value

(B characteristics)

VCOMH Connect to Capacitor (Max 6V): VCOMH---(+)----| |--- (-)------ VSSA 1.0µF

VCOML Connect to Capacitor (Max 3V): VCOML ---(-)----| |--- (+)----- VSSA 1.0µF

VGL Connect to Capacitor (Max 16V): VGL ---(-)----| |--- (+)----- VSSA 1.0µF

VGH Connect to Capacitor (Max 21V): VGH ---(+)----| |--- (-)----- VSSA 1.0µF

VCL Connect to Capacitor (Max 5V): VCL ---(-)----| |--- (+)----- VSSA 1.0µF

C22A,C22B Connect to Capacitor (Max 7V): C22A ---(+)----| |--- (-)-----C22B 1.0µF

C21A,C21B Connect to Capacitor (Max 7V): C21A ---(+)----| |--- (-)-----C21B 1.0µF

CX11A,CX11B Connect to Capacitor (Max 7V): CX11A ---(+)----| |--- (-)-----CX11B 2.2µF

C11A, C11B Connect to Capacitor (Max 5V): C11A ---(+)----| |--- (-)-----C11B 2.2µF

C12A, C12B Connect to Capacitor (Max 5V): C12A ---(+)----| |--- (-)-----C12B 1.0µF

VREG1 Connect to Capacitor (Max 6V): VREG1 ---(+)----| |--- (-)-----VSSA 1.0µF

VREG3 Connect to Capacitor (Max 16V): VREG3 ---(+)----| |--- (-)-----VSSA 1.0µF

VDDD Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 1.0µF

DDVDH Connect to Capacitor (Max 6V): DDVDH ---(+)----| |--- (-)-----VSSA 1.0µF

VCI Connect to Capacitor (Max 6V): VCI ---(+)----| |--- (-)-----VSSA 2.2µF

IOVCC Connect to Capacitor (Max 6V): IOVCC ---(+)----| |--- (-)-----VSSA 1.0µF

Note: The aforementioned capacitor must be connected otherwise it will cause poor display quality.

Table 5. 1 Connected Capacitor

Pins connection Feature a. VCI – VLCD b. VCI – VGH c. VSSD – VGL

VF < 0.4V / 20mA at 25°C, VR ≥30V (Recommended diode: RB521S-30)

Table 5. 2 Connected Schottkey diode






6. LCD Power Generation

6.1 LCD Power Generation Scheme

The boost voltage generated is shown as below.

VSSA, VSSD (0V)

VREG1 (3.5 ~ (VLCD-0.5)V)

VCOMH

VGH(4 VCI ~ 6 VCI)

VCOML

VCL

VGH

x 2~3

x (-1)

VCI (2.3 ~ 3.3V)

VLCD (4.6V ~ 6.0V)VLCD

VREG3

VBGP(1.25V)

x 4~6

VDDD(1.8V)

VGL(-5 VCI ~ -3 VCI)

DC/DC

DC/DC

DC/DC

DC/DCx (-3)~(-5)

VGL

VCOML

VCOMH

VDDDVCOM Amplitude

VREG1

IOVCC (1.65 ~ 3.3V)

VCC (2.3 ~ 3.3V)

Figure 6. 1 LCD power generation scheme





APPLICATION NOTE V016.2 Various Boosting Steps

The boost steps of each boosting voltage are selected according to how the external capacitors are connected. Different booster applications are shown as below.

VLCD=2xVCI

VCL=-1xVCI

VGH=6xVCIVGL=-5xVCI

VLCD

VCLC12A

C12B

C21A

C21B

C22A

C22B

VGH

VGL

C11A

C11B

Figure 6. 2 Various boosting steps






7. Software Configuration 7.1 Features 7.1.1 Display

l Resolution: 240(H) x RGB(H) x 480(V) l Display Color modes

A. Normal Display Mode On a. Register-Content interface mode

i. 262,144(R(6),G(6),B(6)) colors ii. 65,536(R(5),G(6),B(5)) colors

B. Idle Mode On a. 8 (R(1),G(1),B(1)) colors.

7.1.2 Display module

l AM-LCD glass 240xRGBx320 l On module VCOM control (-2.0 to 5.5V Common electrode output voltage range) l On module DC/DC converter

A. DDVDH = 4.6 to 6.0V (Source output voltage range) B. VGH = +9.0 to +16.5V (Positive Gate output voltage range) C. VGL = -6.0 to -13.5V (Negative Gate output voltage range)

l Frame Memory area 240 (H) x 480 (V) x 18 bit 7.1.3 Display/Control interface

l Display Interface types supported A. Register-Content interface mode

n 8-/16-/18-bit MPU parallel interface. n Serial data transfer interface. n 16, 18 data lines parallel video (RGB) interface. n MDDI (Mobile Display Digital Interface) interface. n Control Interface types supported

B. Register-Content interface mode (IFSEL0 = 1)

l Logic voltage: A. Register-Content interface mode: (IOVCC): 1.65V ~ 3.3V

(VCC): 2.3V ~ 3.3V.

l Driver power supply (VCI): 2.3 ~ 3.3V l Color modes

A. 16 bit/pixel: R(5), G(6), B(5) B. 18 bit/pixel: R(6), G(6), B(6)





APPLICATION NOTE V017.1.4 Others

l Low power consumption, suitable for battery operated systems l Image sticking eliminated function l CMOS compatible inputs l Optimized layout for COG assembly l Temperature range: -40 ~ +85 °C l Proprietary multi phase driving for lower power consumption l Support external VDD for lower power consumption (such as 1.8 volts input) l Support RGB through mode with lower power consumption l Support Gamma correction of RGB independence l Support normal black/normal white LCD l Support wide view angle display l Support burn-in mode for efficient test in module production l On-chip OTP (one-time-programming) non-volatile memory





APPLICATION NOTE V017.2 GRAM mapping

Note: RA=Row Address,

CA=Column Address, MX=Mirror X-axis (Column address direction parameter), D6 parameter of Memory Access Control (R16h)

command MY=Mirror Y-axis (Row address direction parameter), D7 parameter of Memory Access Control (R16h)

command GS=Scan direction parameter, D4 parameter of Memory Access Control (R16h) command BGR=Red, Green and Blue pixel position change, D3 parameter of Memory Access Control (R16h)

command

Figure 7. 1 Memory Map. (240RGBx320)





APPLICATION NOTE V017.3 Scan Function

The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by “Memory Data Access Control” Command, Bits MY, MX, MV as described below.

MY

MX

MV

Phy

sica

lR

owP

oint

er

Figure 7. 2 MY, MX, MV Setting of 240RGB x 432 Dot

MY MX MV CASET PASET 0 0 0 Direct to Physical Column Pointer Direct to Physical Page Pointer 0 0 1 Direct to Physical Column Pointer Direct to (319-Physical Page Pointer) 0 1 0 Direct to (239-Physical Column Pointer) Direct to Physical Page Pointer 0 1 1 Direct to (239-Physical Column Pointer) Direct to (319-Physical Page Pointer) 1 0 0 Direct to Physical Page Pointer Direct to Physical Column Pointer 1 0 1 Direct to (319-Physical Page Pointer) Direct to Physical Column Pointer 1 1 0 Direct to Physical Page Pointer Direct to (239-Physical Column Pointer) 1 1 1 Direct to (319-Physical Page Pointer) Direct to (239-Physical Column Pointer)

Table 7. 1 MY, MX, MV Setting of 240RGB x 432 Dot





APPLICATION NOTE V017.4 Interface Mode 7.4.1 Interface Mode Selection

IFSEL0 BS2-0 Register Data Display Data

0 000, 001, 010, 011, 100, 101, 110

Command-Parameter interface (MPU interface) GRAM

0 111 Command-Parameter interface (SPI + RGB interface)

Normal: RGB interface Partial: GRAM

1 000, 001, 010, 011, 100

Register-Content interface (MPU interface) GRAM

1 101 MDDI interface GRAM

1 11x Register-Content interface (SPI + RGB interface)

Normal: RGB interface Partial: GRAM

Table 7. 2 Interface Mode Selection

7.4.2 Register-Content Interface Mode

P68 Input signal format selection

0 Format for I80 series MPU 1 Format for M68 series MPU

Table 7. 3 MPU selection in Register-content Interface Circuit

BS2 BS1 BS0 Interface Transferring Method of RAM data

Transferring Method of Command

0 0 0 16-bit collective 0 0 1

16-bit system interface 16-bit + 2 bit

0 1 0 18-bit system interface 18-bit collective 0 1 1 8-bit + 8-bit + 8-bit 1 0 0 8-bit system interface 8-bit + 8-bit 1 0 1 MDDI interface 18-bit

8-bit collective

1 1 x Serial bus transfer interface 16 or 24-bit serial 8-bit serial

Table 7. 4 Interface Selection in Register-content Interface Mode





APPLICATION NOTE V01Parallel Bus System Interface a. Data Pin Function for I80/M68 Series CPU

Operations E_NWR RW_NRD DNC_SCL Writes Indexes into IR 0 1 0 Reads internal status 1 0 0 Writes command into register or data into GRAM 0 1 1 Reads command from register or data from GRAM 1 0 1

Table 7. 5 Data Pin Function for I80 Series CPU

Operations E_NWR RW_NRD DNC_SCL Writes Indexes into IR 1 0 0 Reads internal status 1 1 0 Writes command into register or data into GRAM 1 0 1 Reads command from register or data from GRAM 1 1 1

Table 7. 6 Data Pin Function for M68 Series CPU

b. Bit mapping of one pixel data Input Data (8-/16-/18-bit Interface) Written to GRAM through Write Data Register

Figure 7. 3 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 18( 6 + 6 + 6 )

Bit-Data Input (“BS2, BS1, BS0”=”011”)

GRAM Data

Input Data Bus

Transfer Order

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0 B5 B4 B3 B2 B1 B0

DB7

DB6

DB5

DB4

DB3

DB2

DB7

DB6

DB4

DB3

DB2

DB5

8-bit Data

1

65536 Colors are avaliable

8-bit Data

2

DB1

DB0

DB1

DB0

Figure 7. 4 Input Data Bus and GRAM Data Mapping in 8-Bit Bus System Interface with 16(5 + 6 + 5)







Figure 7. 5 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 16 Bit-Data

Input (“BS2, BS1, BS0”=”000”)

Figure 7. 6 Input Data Bus and GRAM Data Mapping in 16-Bit Bus System Interface with 18(16+2)


Figure 7. 7 Input Data Bus and GRAM Data Mapping in 18-Bit Bus System Interface

(“BS2, BS1, BS0”=”010”)





APPLICATION NOTE V01i80- System Interface Timing

Write to the register

Read the register

NCS

DNC_SCL

NWR_RNW

D7-0 Command write to the register"index" write to index register

NCS

DNC_SCL

NRD_E

D7-0 Command read from the register"index" write to index register

NWR_RNW

NRD_E

Figure 7. 8 Register read/write Timing in Parallel Bus System Interface (for I80 series MPU)






Figure 7. 9 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for I80 series MPU)





APPLICATION NOTE V01Write to the graphic RAM (8-bit 262K Color)

DNC_SCL

D7-0

nth pixel ; Address = N

NCS

(n+1)th pixel ; Address = N+1

"22" h 1st write data 3rd write data 2nd write data 3rd write data1st write data2nd write data

Read the graphic RAM (8-bit 262K Color)

DNC_SCL

NCS

Dummy Read Data

"22" hD7-0

1 pixel data(The format refer 8-bit Interface)

1st read data 2nd read read 3rd read data

B R GR G

NRD_E

NWR_RNW

NRD_E

NWR_RNW

Figure 7. 10 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for I80 series MPU)





APPLICATION NOTE V01m68- System Interface Timing

Write to the register

Read the register

NCS

DNC_SCL

D7-0 Command write to the register"index" write to index register

NCS

DNC_SCL

D7-0 Command read from the register"index" write to index register

NRD_E

NWR_RNW

NRD_E

NWR_RNW

Figure 7. 11 Register read/write Timing in Parallel Bus System Interface (for M68 series MPU)






NCS

DNC_SCL

NWR_RNW

"22"h write to index register Display data write to RAM Display data write to RAM

nth pixel, Address = N (n+1) pixel, Address = N +1

NRD_E

D15-0/D17-0

NCS

DNC_SCL

NWR_RNW

dummy read data 1st read data

NRD_E

"22"h


D17-0

DNC_SCL

NRD_E

nth pixel ; Address = N

NCS


"22" h 1st write data 1st write data 1st write data 2nd write data2nd write data2nd write data


NWR_RNW

D15-0

DNC_SCL

Dummy Read Data

NCS

"22" hD7-0


1st read data 2nd read data 3rd read data

R G B GR

NRD_E

NWR_RNW

Figure 7. 12 GRAM read/write Timing in 16-/18-bit Parallel Bus System Interface (for M68 series MPU)






Figure 7. 13 GRAM read/write Timing in 8-bit Parallel Bus System Interface (for M68 series MPU)





APPLICATION NOTE V017.4.3 Serial Data Transfer interface

RS R/W Function 0 0 Writes Indexes into IR 1 0 Writes command into register or data into GRAM 1 1 Reads command from register or data from GRAM

Table 7. 7 The Function of RS and R/W Bit bus

Serial Data Transfer interface Timing

Figure 7. 14 Data Write Timing in Serial Bus System Interface

Figure 7. 15 Data Read Timing in Serial Bus System Interface





APPLICATION NOTE V017.4.5 RGB Interface

EPL ENABLE Display 0 0 Disable 0 1 Enable 1 0 Enable 1 1 Disable

Table 7. 8 EPL bit setting and Valid ENABLE Signal

RGB Interface Timing

Display period

HSYNC

VSYNC

DOTCLK

( EPL bit = 0 )

Display area for RAM data

( DPL bit = 0 )

( HSPL bit = 0 )

(VSPL bit=0)

ENABLE

D17-0

Vertical Back porch

Horizontal Back porch

Figure 7. 16 RGB Interface Circuit Input Timing





APPLICATION NOTE V01(a) 18 bit/pixel color order (R 6-bit, G 6-bit, B 6-bit), 262,144 colors (CSEL(2-0) = “110”)

Figure 7. 17 18 bit / pixel Data Input of RGB Interface





APPLICATION NOTE V01(b) 16 bit/pixel color order (R 5-bit, G 6-bit, B 5-bit), 65,536 colors (CSEL(2-0) = “101”)

NRESET

VSYNC

HSYNC

ENABLE

DOTCLK

R10 R20 R30 R40 R50D13

R14 R24 R34 R44 R54

R13 R23 R33 R43 R53

R12 R22 R32 R42 R52

D17

D16

D15

R11 R21 R31 R41 R51D14

G15 G25 G35 G45 G55

D12

D11

G12 G22 G32 G42 G52

G11 G21 G31 G41 G51

G10 G20 G30 G40 G50

B14 B24 B34 B44 B54

G13 G23 G33 G43 G53D9

D8

D7

D6

D5

G14 G24 G34 G44 G54D10

B13 B23 B33 B43 B53

B12 B22 B32 B42 B52

B11 B21 B31 B41 B51

B10 B20 B30 B40 B50

D4

D3

D2

D1

D0

16-bit(Pixel n)

16-bit(Pixel n+1)

16 -bit(Pixel n+2)

R1 G1 B1 R2 G2 B2 R3 G3 B3

(bit extension) Rlsb=Rmsb, Blsb=Bmsb,do not need lookup table

18-bit/pixel

Figure 7. 18 16 bit / pixel Data Input of RGB Interface





APPLICATION NOTE V017.4.6 MDDI Interface

The HX-8352-A support MDDI, which is a differential serial interface with high-speed, low voltage swing characteristics. Both command and display image data can be transferred by MDDI. The devices connected by Data and STB link are host and client part. Host transfer data to client in “forward” direction, client transfer data to host in “reverse” direction. The Data line is Dual direction, both command and image data are all send through the Data line. The STB line send strobe signal from host to client. Data transferred in MDDI link are encoded as packet type.

Figure 7. 19 Physical Connection of MDDI Host and Client

7.4.6.1 Terminology

The devices connected by the MDDI link are called the host and client. Data going from the host to the client travels in the forward direction, and data from the client to the host travels in the reverse direction.

Figure 7. 20 MDDI Terminology

Figure 7. 21 Example of Bi-Directional MDDI Communication





APPLICATION NOTE V017.4.6.2 MDDI Packet

Data transmitted over the MDDI link is grouped into packets. Several packets format is supported in HX8352-A. Most packets are in forward direction, transferred from host to client; but reverse encapsulation packet is in reverse direction, transferred from MDDI client to host. A number of packets, started by sub-frame header packet, construct one sub frame.

Figure 7. 22 MDDI Packet Structure

Refer to MDDI frame structure, sub-frame header packet is placed in front of a sub-frame, and some sub-frames make up a media-frame. HX8352-A support 9 types of packets, which described in the table below.

Packet Function Direction Sub-frame header packet Header of each sub frame Forward Register access packet Register setting Forward Video stream packet Video data transfer Forward Filler packet Fill empty packet space Forward Reverse link encapsulation packet Reverse data packet Reverse Round-trip delay measurement packet Host->client->host delay check Forward/Reverse Client capability packet Capability of client check Reverse Client request and status packet Information about client status Reverse Link shutdown packet End of frame Forward

Figure 7. 23 List of Supported MDDI Packet





APPLICATION NOTE V01Sub-frame Header Packet

Register Access Packet





APPLICATION NOTE V01Video Stream Packet

Filler Packet

Link Shutdown Packet





APPLICATION NOTE V017.4.6.3 Hibernation / Wake up

HX8352-A supports hibernation mode for reduce current consumption. The MDDI link can enter the hibernation state quickly and wake up from hibernation quickly. This allows the system to force the MDDI link into hibernation frequently to reduce power consumption. In hibernation mode, hi-speed drivers and receivers are disabled and low-speed & low-power receivers are enabled to detect wake-up sequence.

HOST CLIENT

VT=0

VT=0

VT= 125mV

VT=0

STB(host)

Enable(host)

Data

(host to client)

Data

Wake-up

RTerm

RTerm

STB(client)

Data

Data

Enable(client)

Wake-up

(host to client)

client to host

(host to client)

client to host

client to host

MDDI_STB+

MDDI_STB-

MDDI_DATA+

MDDI_DATA-

VT=125mV

OFF

OFF

OFF

OFF

OFF

OFF

ONON

Figure 7. 24 MDDI Transceiver / Receiver State in Hibernation

When the link wakes up from hibernation the host and client exchange a sequence of pulses. These pulsed can be detected using low-speed line receivers that consume only a fraction of the current as the differential receivers required to receive the signals at the maximum link operating speed. Either the host or client can wake up the link, which is supported in HX8352-A: Host-Initial Wakeup & Client-Initial Wakeup.





APPLICATION NOTE V017.4.6.4 MDDI Link Wakeup Sequence

Figure below provide a host-initiated wake-up is described below without contention from the client trying to wake up at the same time. The labeled events are: Host-Initiated Wake-up

Figure 7. 25 Host-initiated Link Wakeup Sequence

A. The host sends a Link Shutdown Packet to inform the client that the link will

transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for

64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C.

C. The host enters the low-power hibernation state by disabling the MDDI_Data0 and MDDI_Stb drivers and by placing the host controller into a low-power hibernation state. It is also allowable for MDDI_Stb to be driven to a logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state.

D. After a while, the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. The client first detects the wake-up pulse using a low-power differential receiver having a +125mV input offset voltage.

E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level. The host begins to toggle MDDI_Stb in a manner consistent with having a logic-zero level on MDDI_Data0 for a duration of 150 MDDI_Stb cycles.

F. The host drives MDDI_Data0 to a logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles.

G. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at point G the MDDI host generates MDDI_Stb based on the logic level on MDDI_Data0 so that proper data-strobe encoding commences from point G.





APPLICATION NOTE V01An example of a typical client-initiated service request event with no contention is illustrated in below figure. The labeled events are：

Client-Initiated Wake-up

Figure 7. 26 Client-initiated Link Wake-up Sequence

A. The host sends a Link Shutdown Packet to inform the client that the link will

transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for

64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C.

C. The host enters the low-power hibernation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs. It is also allowable for MDDI_Stb to be driven to a logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state.

D. After a while, the client begins the link restart sequence by enabling the MDDI_Stb receiver and also enabling an offset in its MDDI_Stb receiver to guarantee the state of the received version of MDDI_Stb is a logic-zero level in the client before the host enables its MDDI_Stb driver. The client will need to enable the offset in MDDI_Stb immediately before enabling its MDDI_Stb receiver to ensure that the MDDI_Stb receiver in the client is always receiving a valid differential signal and to prevent erroneous received signals from propagating into the client. After that, the client enables its MDDI_Data0 driver while driving MDDI_Data0 to a logic-one level. It is allowed for MDDI_Data0 and MDDI_Stb to be enabled simultaneously if the time to enable the offset and enable the standard MDDI_Stb differential receiver is less than 200 nsec.

E. Within 1 msec the host recognizes the service request pulse, and the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid fully driven logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb.

F. The host begins outputting pulses on MDDI_Stb and shall keep MDDI_Data0 at a logic-one level for a total duration of 150 MDDI_Stb pulses through point H. The host generates MDDI_Stb in a manner consistent with sending a logic-zero level on MDDI_Data0. When the client recognizes the first pulse on MDDI_Stb it shall disable the offset in its MDDI_Stb receiver.






G. The client continues to drive MDDI_Data0 to a logic-one level for 70 MDDI_Stb pulses, and the client disables its MDDI_Data0 driver at point G. The host continues to drive MDDI_Data0 to a logic-one level for a duration of 80 additional MDDI_Stb pulses, and at point H drives MDDI_Data0 to a logic-zero level.

H. The host drives MDDI_Data0 to a logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles.

I. After asserting MDDI_Data0 to a logic-zero level and driving MDDI_Stb for a duration of 50 MDDI_Stb pulses the host begins to transmit data on the forward link at point I by sending a Sub-frame Header Packet. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles.





APPLICATION NOTE V017.4.6.5 Sequence for the Client to Wake up the Link

The HX8352-A supports two link wake up mode for the client based on VSYNC or GPIO. Only in hibernation mode, the client can wake up the link. User should configure the register for a wakeup before link is shut down.

Link wakeup based on VSYNC

When all display data finishes being displayed in display mode, a data request is sent to the MDDI host for new video data. The MDDI link is normally in hibernation mode for reducing power dissipation by the interface. Before the on-chip RAM is updated, the MDDI link must be woken up. In that case, you can use a link wakeup by the client as a data request. When the link wakeup register VWAKE_EN is set in VSYNC mode, the link is woken up by the client synchronously with a vertical sync signal generated in the HX8352-A. If the interface speed and the wakeup period are well known, link wakeup based on VSYNC can be used to attain consistent display. Figure below shows detailed timing on a link wakeup based on VSYNC.

SYNC STATE HIBERNATION STATE WAKE-UP STATE SYNC STATEA

link_active

frame_update

client_wakeup

B CD EF

The Detailed descriptions for labeled events are as follows:

A. MDDI host writes to the VSYNC based link wakeup register to enable a wake-up based on internal

vertical-sync signal.

B. link_active goes low when the host puts in the link into hibernation after no more data needs to be sent

to the HX8352-A

C. frame_update, the internal vertical-sync signal goes high indicating that update pointer has wrapped

around and is now reading from the beginning of the frame buffer. Link wake-up point can be set using

WKF and WKL (4Ah, 4Bh) registers. WKF specifies the number of frame before wake-up; WKL

specifies the number of lines before wake-up.

D. client_wakeup input to the MDDI client goes high to start the client initiated link wake-up.

E. link_active goes high after the host brings the link out of hibernation.

F. After link wake-up, client_wakeup signal and the VWAKE register are cleared automatically.





APPLICATION NOTE V01GPIO Based Link Wake-up In VSYNC-based link wake-up, wake-up enable register setting prior to link shut-down. GPIO based Link wake-up is enabled by interrupt from outside of the IC. For GPIO based link wake-up, GPIO interrupt enable and GPIO PAD mode (to input mode) setting must be set. Once HX8352-A receive interrupt, internal GPIO base link wake-up flag set to high, and the following procedure is similar to that of VSYNC based link wake-up. The following figure shows detailed timing for GPIO based link wake-up.





APPLICATION NOTE V01 7.4.6.6 Sub Panel Interface

The HX8352-A supports the Sub Panel interface which connected to Sub Panel driver IC with Parallel Interface. When HX8352-A receive MDDI packets from host device, the HX8352-A will convert MDDI packet to parallel data and send to sub panel driver IC.

Mobile System

MDDI host

LCD Driver IC

LCD Driver IC

Main DisplaySub Display

Parallel Interface (NCS2, RS2, NWR2, E2, DBS17-0)

MD

DI

Figure 7. 27 Sub Panel Interface





APPLICATION NOTE V01Sub Panel Function When the register access packet (R53h= ’00h’) is received, then following register access packets or video stream packets are transferred to the sub panel via Sub Panel Interface. Sub panel selection address (R53h) can be changed by setting register SUB_SEL. The SUB_SEL value must be set to unused address in both Main/Sub Panel Driver IC. If video data is transferred to the sub panel driver IC via the Sub Panel Interface, additional RAM Index (default 0022h) is automatically generated by HX8352-A.

Figure 7. 28 Main/Sub Panel Selection Procedure





APPLICATION NOTE V01Sub Panel Interface Timing The HX8352-A’s Sub Panel Interface is supports two type panel (TFT and STN) and offer 18-/16-/9-/8-bit interface format (i80 and m68 system).

TFT Type Sub Panel Timing

Figure 7. 29 18-/16-Bit Sub Panel Interface Register Access Data Timing for i80 Series TFT Sub Panel








Figure 7. 32 9-/8-Bit Sub Panel Interface Register Access Data Timing for m68 Series TFT Sub Panel






200FFh

3FF00h

1FF00h

00001h

11111h

CRC

HeaderCRC

Pixel data #1(11111h)

2

00804h

2 4 10

MDDIData

Stream

DBS[17:0]

NCS2

RS2

NWR2

112tBIT

Pixel data #3(3FF00h)


18tBIT

Index data Pixel data#1 Pixel data#5Pixel data#4Pixel data#2 Pixel data#3

8tBIT 8tBIT 8tBIT 8tBIT 8tBIT 8tBIT

2 4 2 22 444 4

16tBITIndex data write(SUBWR[10:0])

8tBIT 16tBITPixel write

16tBITPixel write

16tBITPixel write

16tBITPixel write

16tBITPixel write8tBIT

Space ofMostly each

4 pixels

1 Video Stream Packet(18-bpp) 320tBIT

Pixel data #2(200FFh)

Pixel data #4(1FF00h)

Figure 7. 33 18-Bit Sub Panel Interface Video Data Timing for i80 Series TFT Sub Panel

Figure 7. 34 18-Bit Sub Panel Interface Video Data Timing for M68 Series TFT Sub Panel






00FFh

FF00h

11FFh

0001h

1ABCh

Header Pixel data #1(1ABCh)

0202h

MDDIData

Stream

DBS[17:0]and DBS[8:1](DBS9 and DBS0 output Low)

NCS2

RS2

NWR2

96tBIT

1 Video Stream Packet (16-bpp)

CRC

304tBIT

Pixel data #3(FF00h)




Index data Pixel data #1 Pixel data #2 Pixel data #3 Pixel data #4 Pixel data #5

8 tBIT 8 tBIT 8 tBIT 8 tBIT 8 tBIT 8 tBIT

2 2 2 2 2 24 4 4 4 4 41016 tBIT

Index data write(SUBWR[10:0])

16 tBITpixel write

16 tBITpixel write

16 tBITpixel write

16 tBITpixel write

16 tBITpixel write

Figure 7. 35 16-Bit Sub Panel Interface Video Data Timing for I80 Series TFT Sub Panel

Figure 7. 36 16-Bit Sub Panel Interface Video Data Timing for m68 Series TFT Sub Panel







02hMSB

00hMSB

FFhMSB

11hMSB

00hMSB

1AhMSB

CRC

HeaderCRC

Pixel data #1

(1ABCh)

02hLSB

BChLSB

ADhLSB

00hLSB

FFhLSB

01hLSB

MDDIData

Stream

DBS[17:10](DBS[9:0]output Low)

NCS2

RS2

E2

1 Video Stream Packet (16-bpp)304 tBIT

Pixel data #2

(00ADh)

Pixel data #3

(FF00h)

Pixel data #5

(0001h)

Pixel data #4

(11FFh)

16 tBIT

Index data Pixel data #1 Pixel data #2 Pixel data #3 Pixel data #4 Pixel data #5

8tBIT 8tBIT 8tBIT 8tBIT 8tBIT8tBIT8tBIT 8tBIT 8tBIT8tBIT 8tBIT8tBIT

2 2 2 2 2 22222224 4 4444444444 4 444 4

96 tBIT

16 tBIT 16 tBIT 16 tBIT 16 tBIT 16 tBIT 16 tBITIndex data

write(SUBWR[10:0])

pixel write pixel write pixel writepixel write pixel write

4






APPLICATION NOTE V01STN Type Sub Panel Timing

CRC

Register Address(000h)

RegisterData

(1234h)

CRC

Header

5678h1234h

CRC

RegisterAddress(001h)

RegisterAddress(5678h)

CRC

HeaderMDDIData

Stream

DBS[17:0]and DBS[8:1](DBS9 and DBS0 output Low)

NCS2

RS2

NWR2

2 4 10 2 4 10

16 tBIT 16 tBIT

8 tBIT 8 tBIT

160 tBIT160 tBIT1 Register Access Packet 1 Register Access Packet

Figure 7. 41 18-/16-Bit Sub Panel Interface Register Access Data Timing for i80 Series STN Sub Panel

Figure 7. 42 9-/8-Bit Sub Panel Interface Register Access Data Timing for i80 Series STN Sub Panel






Figure 7. 43 18-/16-Bit Sub Panel Interface Register Access Data Timing for m68 Series STN Sub Panel

Figure 7. 44 9-/8-Bit Sub Panel Interface Register Access Data Timing for m68 Series STN Sub Panel






Figure 7. 45 18-Bit Sub Panel Interface Video Data Timing for i80 Series STN Sub Panel

Figure 7. 46 18-Bit Sub Panel Interface Video Data Timing for m68 Series STN Sub Panel





APPLICATION NOTE V017.5 Initial Procedure 7.5.1 Power Supply Setting Flow

Power ON RESET & Display OFF

DTE="0",D[1-0]="00"

For power-supply

setting (1)AP[2-0]="100",

Set BT[3-0], VRH[3-0],

VCM[6-0], VDV[4-0],

PON="0"

VCOMG="0"

Display ONsequence

VC1[2-0],

PON="1"

VCOMG="1"

GON="0"

Set N_SAP[7-0]

Power Supply Operation Startsetting bits

Display OFF setting bits

Power Supply Operation Start

setting bits

For other mode settings

For power-supplysetting (2)

For the settingbefore powersupply startup

Power supply setting initializing bits

Note1)1ms or more

Note2)10ms or more Oscillation Circuit Stabilizing time

Note3)40ms or more Step-up Circuit Stabilizing time

Note4)100ms or more Operational Amplifier Stabilizing Time

Note 1

Note 2

Note 3

Note 4

Vcc,Vci,IOVcc ON

DK="1"

Set GON, DTE, D[1-0]

Display OFFSequence

Display OFF

Normal DisplayDTE = "1", D[1-0]="11"GON = "1"

Display ON setting bits

Power OFF flow

AP[2-0]="000"PON="0"

N_SAP[7-0]="00000000"

VCOMG="0"

Issue instructions

for power-supply

setting (2)

Power supply halt

setting bits

Vcc,Vci,IVcc OFF

DK="1"

Set GON, DTE, D[1-0]

Power ON flow

VC3[2-0],

DK="0"

Figure 7. 53 Power Supply Setting Flow





APPLICATION NOTE V017.5.2 Display on/off Setting Flow

Figure 7. 54 Display On/Off Setting Flow





APPLICATION NOTE V017.5.3 Standby Mode Setting Flow

Start oscillation (OSC_EN = "1")

Wait 10ms

Setstandby

Release from standby

(STB= "0")

Release from

standby

Stop oscillation (OSC_EN = "0")

Power supply setting

Display on sequence

Display off sequence

Set standby (STB = "1")

Figure 7. 55 Standby Mode Setting Flow





APPLICATION NOTE V017.6 Initial code for reference 7.6.1 The reference setting of Normal Display for Register-Content Interface Mode 7.6.1.1 The reference setting of CMO 3.0” Panel void HX8352_Init_CMO30(void) { RESET(); DelayX1ms(150); Set_LCD_8B_REG(0x83,0x02); // TESTM=1 Set_LCD_8B_REG(0x85,0x03); // VDC_SEL=011. Set_LCD_8B_REG(0x8B,0x00); // STBA[15:8]=0x00 Set_LCD_8B_REG(0x8C,0x93); // STBA[7]=1, STBA[5:4]=01, STBA[1:0]=11 Set_LCD_8B_REG(0x91,0x01); // DCDC_SYNC=1 Set_LCD_8B_REG(0x83,0x00); // TESTM=0 // Gamma Setting Set_LCD_8B_REG(0x3E,0xF0); Set_LCD_8B_REG(0x3F,0x07); Set_LCD_8B_REG(0x40,0x00); Set_LCD_8B_REG(0x41,0x43); Set_LCD_8B_REG(0x42,0x16); Set_LCD_8B_REG(0x43,0x16); Set_LCD_8B_REG(0x44,0x43); Set_LCD_8B_REG(0x45,0x77); Set_LCD_8B_REG(0x46,0x00); Set_LCD_8B_REG(0x47,0x1E); Set_LCD_8B_REG(0x48,0x0F); Set_LCD_8B_REG(0x49,0x00); // Power Supply Setting Set_LCD_8B_REG(0x17,0x91); // RADJ=0110, OSC_EN=1 Set_LCD_8B_REG(0x23,0x01); // TE 0n Set_LCD_8B_REG(0x2B,0xF9); // N_DCDC=0xF9. DelayX1ms(10); Set_LCD_8B_REG(0x1B,0x14); // BT=0001, AP=100 Set_LCD_8B_REG(0x1A,0x11); // VC3=001, VC1=001 (VLCD/DDVDH)=6.45V) Set_LCD_8B_REG(0x1C,0x0D); // VRH=1110 (VREG1=6.0V) Set_LCD_8B_REG(0x1F,0x27); // VCM=010_1011 DelayX1ms(20); Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=1, XDK=0, // VLCD_TRI=1, STB=0 Set_LCD_8B_REG(0x19,0x1A); // GASENB=0, PON=1, DK=1, XDK=0, // VLCD_TRI=1, STB=0 DelayX1ms(40); Set_LCD_8B_REG(0x19,0x12); // GASENB=0, PON=1, DK=0, XDK=0, // VLCD_TRI=1, STB=0 // VLCD=2XVCI by 2 CAPs DelayX1ms(40); Set_LCD_8B_REG(0x1E,0x2C); // VCOMG=1, VDV=0_1110 DelayX1ms(100);





APPLICATION NOTE V01// DGC Function Enable Set_LCD_8B_REG(0x5A,0x01); DGC_PA_REG(0x5C); // Display ON Setting Set_LCD_8B_REG(0x3C,0xC0); // N_SAP=1100 000 Set_LCD_8B_REG(0x3D,0xC0); // I_SAP =1100 0000 Set_LCD_8B_REG(0x34,0x38); // EQS=1000 0111 Set_LCD_8B_REG(0x35,0x38); // EQP=0011 1000 Set_LCD_8B_REG(0x24,0x38); // GON=1, DTE=1, D=10 DelayX1ms(40); Set_LCD_8B_REG(0x24,0x3C); // GON=1, DTE=1, D=11 Set_LCD_8B_REG(0x16,0x08); // BGR=1 Set_LCD_8B_REG(0x01,0x02); // INVON=0, NORNO=1 Set_LCD_8B_REG(0x55,0x00); } void DGC_PA_REG(unsigned char ADDR) { unsigned char i; M51_CTRL_LCD_nCS = 0; M51_CTRL_LCD_RS = 0; WR_8B_FORMAT(ADDR); //ADDR=0x5C. M51_CTRL_LCD_RS = 1; for( i=0; i<=2; i++) { WR_8B_FORMAT(0x01 ); WR_8B_FORMAT(0x01 ); WR_8B_FORMAT(0x01 ); WR_8B_FORMAT(0x01 ); WR_8B_FORMAT(0x07 ); WR_8B_FORMAT(0x11 ); WR_8B_FORMAT(0x17 ); WR_8B_FORMAT(0x1B ); WR_8B_FORMAT(0x1E ); WR_8B_FORMAT(0x22 ); WR_8B_FORMAT(0x27 ); WR_8B_FORMAT(0x2C ); WR_8B_FORMAT(0x30 ); WR_8B_FORMAT(0x35 ); WR_8B_FORMAT(0x39 ); WR_8B_FORMAT(0x3D ); WR_8B_FORMAT(0x41 ); WR_8B_FORMAT(0x45 ); WR_8B_FORMAT(0x49 ); WR_8B_FORMAT(0x4D ); WR_8B_FORMAT(0x51 ); WR_8B_FORMAT(0x54 ); WR_8B_FORMAT(0x58 ); WR_8B_FORMAT(0x5B ); WR_8B_FORMAT(0x5F ); WR_8B_FORMAT(0x62 ); WR_8B_FORMAT(0x66 );





APPLICATION NOTE V01 WR_8B_FORMAT(0x69 ); WR_8B_FORMAT(0x6D ); WR_8B_FORMAT(0x71 ); WR_8B_FORMAT(0x74 ); WR_8B_FORMAT(0x78 ); WR_8B_FORMAT(0x7C ); WR_8B_FORMAT(0x80 ); WR_8B_FORMAT(0x84 ); WR_8B_FORMAT(0x88 ); WR_8B_FORMAT(0x8D ); WR_8B_FORMAT(0x91 ); WR_8B_FORMAT(0x96 ); WR_8B_FORMAT(0x9A ); WR_8B_FORMAT(0x9F ); WR_8B_FORMAT(0xA4 ); WR_8B_FORMAT(0xA9 ); WR_8B_FORMAT(0xAD ); WR_8B_FORMAT(0xB0 ); WR_8B_FORMAT(0xB4 ); WR_8B_FORMAT(0xB7 ); WR_8B_FORMAT(0xBB ); WR_8B_FORMAT(0xBF ); WR_8B_FORMAT(0xC3 ); WR_8B_FORMAT(0xC7 ); WR_8B_FORMAT(0xCC ); WR_8B_FORMAT(0xD0 ); WR_8B_FORMAT(0xD6 ); WR_8B_FORMAT(0xDB ); WR_8B_FORMAT(0xDF ); WR_8B_FORMAT(0xE3 ); WR_8B_FORMAT(0xE7 ); WR_8B_FORMAT(0xEB ); WR_8B_FORMAT(0xEE ); WR_8B_FORMAT(0xF1 ); WR_8B_FORMAT(0xF5 ); WR_8B_FORMAT(0xF7 ); WR_8B_FORMAT(0xFC ); } M51_CTRL_LCD_nCS = 1; }





APPLICATION NOTE V017.6.1.2 The reference setting of CMO 2.8” Panel void HX8352_Init_CMO28(void) { RESET(); DelayX1ms(150); Set_LCD_8B_REG(0x83,0x02); // TESTM=1 Set_LCD_8B_REG(0x85,0x03); // VDC_SEL=011. Set_LCD_8B_REG(0x8B,0x01); // STBA[15:8]=0x01 Set_LCD_8B_REG(0x8C,0x93); // STBA[7]=1, STBA[5:4]=01,

//STBA[1:0=11 Set_LCD_8B_REG(0x91,0x01); // DCDC_SYNC=1 Set_LCD_8B_REG(0x83,0x00); // TESTM=0 // Gamma Setting Set_LCD_8B_REG(0x3E,0xA5); Set_LCD_8B_REG(0x3F,0x52); Set_LCD_8B_REG(0x40,0x00); Set_LCD_8B_REG(0x41,0x36); Set_LCD_8B_REG(0x42,0x00); Set_LCD_8B_REG(0x43,0x77); Set_LCD_8B_REG(0x44,0x15); Set_LCD_8B_REG(0x45,0x76); Set_LCD_8B_REG(0x46,0x01); Set_LCD_8B_REG(0x47,0x00); Set_LCD_8B_REG(0x48,0x00); Set_LCD_8B_REG(0x49,0x02); // Power Supply Setting

Set_LCD_8B_REG(0x17,0x91); // RADJ=1100, OSC_EN=1 Set_LCD_8B_REG(0x23,0x01); // TE 0n Set_LCD_8B_REG(0x2B,0xF9); // N_DCDC=0xF9. DelayX1ms(10); Set_LCD_8B_REG(0x1B,0x14); // BT=0001, AP=100 Set_LCD_8B_REG(0x1A,0x11); // VC3=001, VC1=001 (VLCD=6V) Set_LCD_8B_REG(0x1C,0x0D); // VRH=1101 (VREG1=5.5V) Set_LCD_8B_REG(0x1F,0x3A); // VCM=011_1010 DelayX1ms(20); Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=1, XDK=0, // VLCD_TRI=1, STB=0 Set_LCD_8B_REG(0x19,0x1A); // GASENB=0, PON=1, DK=1, XDK=0, //VLCD_TRI=1, STB=0 DelayX1ms(40); Set_LCD_8B_REG(0x19,0x12); // GASENB=0, PON=1, DK=0, XDK=0,

//VLCD_TRI=1, STB=0, //VLCD=2XVCI by 2 CAPs DelayX1ms(40); Set_LCD_8B_REG(0x1E,0x2D); // VCOMG=1, VDV=0_1101 DelayX1ms(100);





APPLICATION NOTE V01// DGC Function Enable Set_LCD_8B_REG(0x5A,0x01); DGC_PA_REG(0x5C); // Display ON Setting Set_LCD_8B_REG(0x3C,0xC0); // N_SAP=1100 0000 Set_LCD_8B_REG(0x3D,0xC0); // I_SAP=1100 0000 Set_LCD_8B_REG(0x34,0x38); // EQS=1000 0111 Set_LCD_8B_REG(0x35,0x38); // EQP=0011 1000 Set_LCD_8B_REG(0x24,0x38); //GON=1, DTE=1, D=10 DelayX1ms(40); Set_LCD_8B_REG(0x24,0x3C); //GON=1, DTE=1, D=11

Set_LCD_8B_REG(0x16,0x08); //BGR=1

Set_LCD_8B_REG(0x01,0x06); //INVON=1, NORNO=1 Set_LCD_8B_REG(0x55,0x00); } void DGC_PA_REG(unsigned char ADDR) { unsigned char i; M51_CTRL_LCD_nCS = 0; M51_CTRL_LCD_RS = 0; WR_8B_FORMAT(ADDR); //ADDR=0x5C. M51_CTRL_LCD_RS = 1; for( i=0; i<=2; i++) { WR_8B_FORMAT(0x00); WR_8B_FORMAT(0x00); WR_8B_FORMAT(0x00); WR_8B_FORMAT(0x00); WR_8B_FORMAT(0x00); WR_8B_FORMAT(0x00); WR_8B_FORMAT(0x0D); WR_8B_FORMAT(0x14); WR_8B_FORMAT(0x19); WR_8B_FORMAT(0x1D); WR_8B_FORMAT(0x21); WR_8B_FORMAT(0x28); WR_8B_FORMAT(0x2F); WR_8B_FORMAT(0x34); WR_8B_FORMAT(0x39); WR_8B_FORMAT(0x3E); WR_8B_FORMAT(0x42); WR_8B_FORMAT(0x46); WR_8B_FORMAT(0x4A); WR_8B_FORMAT(0x4D); WR_8B_FORMAT(0x50); WR_8B_FORMAT(0x56); WR_8B_FORMAT(0x5B); WR_8B_FORMAT(0x60); WR_8B_FORMAT(0x64); WR_8B_FORMAT(0x69); WR_8B_FORMAT(0x6D);





APPLICATION NOTE V01 WR_8B_FORMAT(0x71); WR_8B_FORMAT(0x75); WR_8B_FORMAT(0x79); WR_8B_FORMAT(0x7D); WR_8B_FORMAT(0x81); WR_8B_FORMAT(0x84); WR_8B_FORMAT(0x88); WR_8B_FORMAT(0x8C); WR_8B_FORMAT(0x8F); WR_8B_FORMAT(0x92); WR_8B_FORMAT(0x96); WR_8B_FORMAT(0x99); WR_8B_FORMAT(0x9D); WR_8B_FORMAT(0xA0); WR_8B_FORMAT(0xA4); WR_8B_FORMAT(0xA7); WR_8B_FORMAT(0xAB); WR_8B_FORMAT(0xAE); WR_8B_FORMAT(0xB2); WR_8B_FORMAT(0xB5); WR_8B_FORMAT(0xB9); WR_8B_FORMAT(0xBD); WR_8B_FORMAT(0xC1); WR_8B_FORMAT(0xC4); WR_8B_FORMAT(0xC8); WR_8B_FORMAT(0xCD); WR_8B_FORMAT(0xD1); WR_8B_FORMAT(0xD6); WR_8B_FORMAT(0xDB); WR_8B_FORMAT(0xDE); WR_8B_FORMAT(0xE2); WR_8B_FORMAT(0xE6); WR_8B_FORMAT(0xEA); WR_8B_FORMAT(0xEE); WR_8B_FORMAT(0xF2); WR_8B_FORMAT(0xF6); WR_8B_FORMAT(0xFE); } M51_CTRL_LCD_nCS = 1;}





APPLICATION NOTE V017.6.2 The reference setting of into Standby mode for Register-Content Interface Mode void HX8352A_STB_INTO (void) { // Display Off Set_LCD_8B_REG(0x24,0x38); //GON=1, DTE=1, D=10 DelayX1ms (40); Set_LCD_8B_REG(0x24,0x28); //GON=1, DTE=0, D=10 DelayX1ms (40); Set_LCD_8B_REG(0x24,0x00); //GON=0, DTE=0, D=00 // Power Off Set_LCD_8B_REG(0x1E,0x14); // VCOMG=0, VDV=1_0100 DelayX1ms(10); Set_LCD_8B_REG(0x19,0x02); // GASENB=0, PON=0, DK=0, // XDK=0, VLCD_TRI=1, STB=0 DelayX1ms(10); Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=1, // XDK=0, VLCD_TRI=1, STB=0 DelayX1ms(10); Set_LCD_8B_REG(0x1B,0x40); // AP=000 DelayX1ms(10); Set_LCD_8B_REG(0x3C,0x00); // N_SAP=1100 0000 DelayX1ms(10); // Into STB mode Set_LCD_8B_REG(0x19,0x0B); // GASENB=0, PON=0, DK=0, // XDK=0, VLCD_TRI=1, STB=1 DelayX1ms(10); // Stop Oscillation Set_LCD_8B_REG(0x17,0x90); // RADJ=1001, OSC_EN=0 }





APPLICATION NOTE V017.6.3 The reference setting of exit Standby mode for Register-Content Interface Mode void HX8352A_STB_EXIT_3.0” (void) { // Start Oscillation Set_LCD_8B_REG(0x17,0x91); // RADJ=1001, OSC_EN=1 DelayX1ms(10); // Exit STB mode Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=0, // XDK=0, VLCD_TRI=1, STB=0 // Power Supply Setting Set_LCD_8B_REG(0x1B,0x14); // BT=0001, AP=100 Set_LCD_8B_REG(0x1A,0x11); // VC3=001, VC1=001 (VLCD/DDVDH)=6.45V) Set_LCD_8B_REG(0x1C,0x0D); // VRH=1110 (VREG1=6.0V) Set_LCD_8B_REG(0x1F,0x27); // VCM=010_1011 DelayX1ms(20); Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=1, XDK=0, //VLCD_TRI=1, STB=0 Set_LCD_8B_REG(0x19,0x1A); // GASENB=0, PON=1, DK=1, XDK=0, //VLCD_TRI=1, STB=0 DelayX1ms(40); Set_LCD_8B_REG(0x19,0x12); // GASENB=0, PON=1, DK=0, XDK=0, //VLCD_TRI=1, STB=0, // VLCD=2XVCI by 2 CAPs DelayX1ms(40); Set_LCD_8B_REG(0x1E,0x2C); // VCOMG=1, VDV=0_1110 DelayX1ms(100); // Display ON Setting

Set_LCD_8B_REG(0x3C,0xC0); // N_SAP=1100 0000 Set_LCD_8B_REG(0x3D,0xC0); // I_SAP=1100 0000 Set_LCD_8B_REG(0x34,0x38); // EQS=0011 1000 Set_LCD_8B_REG(0x35,0x38); // EQP=0011 1000 Set_LCD_8B_REG(0x24,0x38); //GON=1, DTE=1, D=10 DelayX1ms(40);

Set_LCD_8B_REG(0x24,0x3C); //GON=1, DTE=1, D=11 }





APPLICATION NOTE V01void HX8352A_STB_EXIT_2.8” (void) { // Start Oscillation Set_LCD_8B_REG(0x17,0x91); // RADJ=1001, OSC_EN=1 DelayX1ms(10); // Exit STB mode Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=0, // XDK=0, VLCD_TRI=1, STB=0 // Power Supply Setting Set_LCD_8B_REG(0x1B,0x14); // BT=0001, AP=100 Set_LCD_8B_REG(0x1A,0x11); // VC3=001, VC1=001 (VLCD=6V) Set_LCD_8B_REG(0x1C,0x0D); // VRH=1101 (VREG1=5.5V) Set_LCD_8B_REG(0x1F,0x3A); // VCM=011_1010 ==>VcomH DelayX1ms(20); Set_LCD_8B_REG(0x19,0x0A); // GASENB=0, PON=0, DK=1, XDK=0, //VLCD_TRI=1, STB=0 Set_LCD_8B_REG(0x19,0x1A); // GASENB=0, PON=1, DK=1, XDK=0, //VLCD_TRI=1, STB=0 DelayX1ms(40); Set_LCD_8B_REG(0x19,0x12); // GASENB=0, PON=1, DK=0, XDK=0,

//VLCD_TRI=1, // STB=0,VLCD=2XVCI by 2 CAPs

DelayX1ms(40); Set_LCD_8B_REG(0x1E,0x2D); // VCOMG=1, VDV=0_1101 DelayX1ms(100); // Display ON Setting Set_LCD_8B_REG(0x3C,0xC0); // N_SAP=1100 0000 Set_LCD_8B_REG(0x3D,0xC0); // I_SAP=1100 0000 Set_LCD_8B_REG(0x34,0x38); // EQS=0011 1000 Set_LCD_8B_REG(0x35,0x38); // EQP=0011 1000 Set_LCD_8B_REG(0x24,0x38); //GON=1, DTE=1, D=10 DelayX1ms(40); Set_LCD_8B_REG(0x24,0x3C); //GON=1, DTE=1, D=11 }






8. Revision History

Version Date Description of changes 2007/09/11 New setup 2007/11/28 Updated initial code in P64 ~ P72. 2008/02/24 Updated initial code in P64 ~ P72.

01

2008/03/12 Updated initial code in P64 ~ P72.



hx8352-a t an v01 0803020 - openhacks · 2016. 5. 12. · hx8352-a(t) 240rgb x 480 dot, 262k color,...

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