hx8347-g n an preliminary v01.03 20110330 · ( doc no. hx8347 -g(n) -an ) hx8347-g(n) 240rgb x 320...

( DOC No. HX8347-G(N)-AN )

HX8347-G(N) 240RGB x 320 dot, 262k color, with internal GRAM, TFT Mobile Single Chip Driver Preliminary version 01 April, 2010

-P.2- Himax Confidential

April, 2010 This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax.

1. MPU Mode Reference FPC Circuit .................. ........................................................................................... 5

1.1 BOE .................................................................................................................................................... 6 1.1-1BOE 2.2”Reference FPC Circuit ................. ................................................................................... 6 1.1-2 Initial Code for BOE 2.2” .................... ........................................................................................... 7 1.1-3 Initial Code for BOE 3.14” ................... .......................................................................................... 9 1.1-4 Initial Code for BOE 2.83” ................... .........................................................................................11 1.2 GiantPlus ...................................... ................................................................................................... 13 1.2-1GiantPlus 2.6”Reference FPC Circuit ........... .............................................................................. 13 1.2-2 Initial Code for GiantPlus 2.67” ............. ..................................................................................... 14 1.2-3 Initial Code for GiantPlus 2.83” ............. ..................................................................................... 16 1.3 Tianama........................................ .................................................................................................... 18 1.3-1Tianma 2.83”Reference FPC Circuit ............. .............................................................................. 18 1.3-2 Initial Code for Tianma 2.83” ................ ...................................................................................... 19 1.3-3 Initial Code for Tianma 3.14” ................ ...................................................................................... 23 1.4 CMI.................................................................................................................................................... 25 1.4-1CMI 2.8”Reference FPC Circuit ................. .................................................................................. 25 1.4-2 Initial Code for CMI 2.8” .................... .......................................................................................... 26

2. RGB Mode Reference FPC Circuit .................. ......................................................................................... 28 2.1. SPI+RGB Mode Reference Initial Code........... ............................................................................. 29

3. OTP Programming ................................. .................................................................................................... 31 4. Revision History ................................ ........................................................................................................ 32

HX8347-G(N) 240RGB x 320 dot, 262k color, with Internal GRAM, TFT Mobile Single Chip Driver List of Contents April, 2010



Figure 1. 1 HX8347-G MPU Application Reference Circuit.............................................................. 5 Figure 2. 2 HX8347-G SPI+RGB Application Reference Circuit .................................................... 28 Figure 3. 3 OTP flow ...................................................................................................................... 31

HX8347-G(N) 240RGB x 320 dot, 262k color, with Internal GRAM, TFT Mobile Single Chip Driver List of Figure November, 2009



Table 3. 1 OTP Address Mapping .................................................................................................. 31

HX8347-G(N) 240RGB x 220 dot, 262k color, with Internal GRAM, TFT Mobile Single Chip Driver List of Table

April, 2010



1. MPU Mode Reference FPC Circuit

IFSEL="1" COMMAND-PARAMETER INTERFACE

VCOM

C3

0603/1u/16V

DB

0S

DA

C21P C21N

C21AB10603/1u/10V

C22

P

C21

PC

21N

C22

N

C22AB10603/1u/10V

DB

1

C22NC22P

NW

R_S

CL

DB

2

NR

D

DN

C_S

CL

DB

3

U1

HX8347-G (BUMP UP)C12

P

C31

P

VS

SD

IM0

NR

ES

ET

NC

SD

NC

_SC

LN

WR

_SC

LN

RD

TE

ST

2V

SY

NC

VG

L

CO

NN

VG

H

G2

G4

G32

0

G1

G3

G31

7G

319

S1

S2

S3

S72

0S

719

S71

8

G6

G31

8

G31

5

G5

DD

VD

H

C31

N

C22

NC

22P

VC

OM

IM2

TE

ST

1

IM3

VS

SA

IFS

EL

VS

SD

IM1

DU

MM

Y27

DU

MM

Y

DU

MM

Y23

DU

MM

Y24

S26

2S

263

S36

1S

265

S26

6S

267

C21

PC

21N

DE

DO

TC

LKS

DA

DB

0D

B1

DB

2D

B3

DB

4D

B5

DB

6D

B7

DB

8D

B9

DB

10D

B11

DB

12D

B13

DB

14D

B15

DB

16D

B17

OS

CT

ET

ES

T3

CA

BC

_PW

M_O

UT

BC

_CT

RL

TE

ST

4T

ES

T5

TE

ST

6T

ES

T7

TE

ST

8T

ES

T9

TE

ST

10IO

VC

C

VR

EG

1V

CL

VP

P_O

TP

VC

I

C11

N

CO

NN

C12

N

VT

ES

T

VC

OM

_DU

MM

YV

CO

MH

_DU

MM

YV

CO

ML_

DU

MM

Y

HS

YN

C

VD

DD

C11

P

NC

S

DB

4

NR

ES

ET

240RGB x 320 TFT Panel

IM3

DB

6

IM2

DB

5

DB

7

IM1

IM0

VT

ES

T

VS

SD

DB

9D

B8

DB

11D

B10

VS

SD

VC

OM

H

DB

13D

B12 VC

OM

L

DB

14

DB

16

VG

L

DB

15

TE

DB

17

VP

P_O

TP

CA

BC

PW

M

DD

VD

H

C6

0603/1u/10V

C31P

VR

EG

1

C31N

C31AB10603/1u/6.3VC4

0603/1u/10V

VC

L

C31

NC

31P

C12NC12P

C11P

C12AB1 (OPEN)0603/1u/10V

C11N

C11AB0603/1u/6.3V

CO

NN

1

C12

NC

12P

C11

NC

11P

CO

NN

2

VC

I

C10603/1u/6.3V

VD

DD

IOV

CC

VS

SA

BC

CT

RL

VG

H

C2

0603/1u/25V

IOV

CC

NR

ES

ET

NR

D_E

DN

C_S

CL

NW

R_R

NW

3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description".

DD

VD

H

NC

SV

GL

VG

H

VC

L

VR

EG

1

VC

OM

L

VC

OM

TE

VC

OM

H

VD

DD

IM1

IM2

OS

C

IM0

DNC1DNC

NCS1NCS

VCOM1VCOM

VDDD1VDDD

NWR_SCL1NWR_SCL

VTEST1VTEST

DDVDH1DDVDH

IM3IM1

IM2IM2

VCOMH1VCOMH

IM1IM3

TE1TE

VCL1VCL

VCOML1VCOML

NRESET1NRESET

VT

ES

T

VGL1VGL

NR

ES

ET

IOV

CC

NRD_E1NRD

VC

I

VREG1VREG1

VGH1VGH

GN

D

OSC1OSC

IM4IM0

IM3

IM3 IM1

8080 MCU 16-bits Parallel type II

IM2

0

IM0

0

0

Interface mode

00

00 1

3-WIRE SERIAL INTERFACE


000

0

1

0 11

- --1

01

1

0 0

100

01

1

01

110 8080 MCU 9-bits Parallel type II

8080 MCU 16-bits Parallel type I



VSSA

VSSD

GN

DIM

0

IM2

IM1


Capacitor

C01 ( C11P/N ) 1uF / 6.3Volt.

C02 ( C12P/N )(Optional)

Recommended spec.

C05 ( C22P/N )

C04 ( C21P/N )

C03 ( DDVDH )

C07 ( VGL )

C06 ( VGH )

C10 ( VDDD )

C09 ( VCL)

C08 ( C31P/N )

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 6.3Volt.

1uF / 25 Volt.

1uF / 10 Volt.

1uF / 6.3 Volt.

1uF / 6.3 Volt.

1uF / 16 Volt.

1uF / 6.3 Volt.

2. SDI pin is I/O pin. SDO is no use.

CO

NN

1

CONN1CONN1

SD

A

CO

NN

2

DB

11

CONN2CONN2

DB

13

DB

8

DB

15

NC

S

DB

5

DB

9D

B10

DB

14

DB

12

DB

6D

B7

DB

4

NW

R_S

CL

DB

3

DB

0

DB

2D

B1

GN

D

DN

C_S

CL

NR

D

DB

17D

B16

TE

VSSC

CA

BC

PW

M

PWMPWM

VP

P_O

TP

VPP_OTP1VPP_OTP


8080 MCU 18-bits Paralle type I

GND1GND

GND2GND

J1

FPC60-0.5-4.0L

VC

I1

VC

I2

GN

D3

VC

C4

IOV

CC

5

nRE

SE

T6

DB

1713

DB

1614

DB

1515

DB

1416

DB

1317

DB

1218

DB

1119

DB

1020

DB

921

DB

822

DB

723

DB

624

DB

525

DB

426

DB

327

DB

228

DB

129

DB

030

nRD

_E31

NW

R_R

NW

32

DN

C33

nCS

34

FLM

35

GN

D36

PW

M_O

UT

37

VS

YN

C38

HS

YN

C39

DO

TC

LK40

EN

AB

LE41

SD

O42

SD

I43

NC

44

NC

45

NC

46

NC

47

NC

48

NC

49

NC

50

NC

51

EX

TC

52

DB

S53

IM3

54

IM2

55

IM1

56

IM0

57

GN

D58

BL+

/NC

59

BL_

GN

D/N

C60

DB

237

DB

228

DB

219

DB

2010

DB

1911

DB

1812

1. VCI, IOVCC are separated from different power so urce to get better display quality.

IM3

IOV

CC

VC

I

IOVCC1IOVCC

VCI1VCI

Figure 1. 1 HX8347-G MPU Application Reference Circ uit

HX8347-G(N) 240RGB x 320 dot, 262k color, with Internal GRAM, TFT Mobile Single Chip Driver Preliminary Version 01

November, 2009


April, 2010

HX8347-G(N) 240RGB x 320 dot, 262k color, TFT Mobile Single Chip Driver

APPLICATION NOTE Preliminary V01

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax.

1.1 BOE 1.1-1BOE 2.2”Reference FPC Circuit

CO

G2

CO

G1

VC

L

C09

1u/6.3V

DB

0

DD

VD

H

C03

1u/10V

DB

1

Title

Size Document Number Rev

Date: Sheet of

Driver IC：HIMAX HX8347-G A01

BOE 2.2" FPC Rev A01

B

1 1Tuesday , October 12, 2010

NOTES 1：Set IOVCC=2.8V(1.65~3.3V);VCI=2.8V(2.5~3.3V)

NOTES 3：Set IM3~IM0="0011"；80 system 18bit type I interface.

DB

2

/CS

DB

4

VP

P_O

TP

VPP_OTP

TE

DB

1

IM0

TE

IM1

VC

IV

CI

IOVCC

DB

5

DB

2D

B3

DB

3

IOV

CC

8080 MCU 18 bits parallel

GN

D

DB

13

DB

15D

B16

C081u/10V

J1Vci

1

Vci

2

GN

D3

Vcc

4

Vcc

5

RE

ST

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB

915

DB

816

DB

717

DB

618

DB

519

DB

420

DB

321

DB

222

DB

123

DB

024

RD

25

WR

26

RS

27

CS

28

FLM

29

GN

D30

BL+

31

BL-

32

DB

12

DB

17

DB

11

DB

9

/RE

SE

T

DB

14

DB

6

DB

8

/RD

DB

7

DB

10

DB

0

/WR

RS

TE

GN

D

IM3

VC

OM

1

VCOM1

C01 ( C11P/N )

DB

4


Recommended spec.Capacitor

C03 ( DDVDH )

1uF / 6.3Volt.

C06 ( VGH )

C05 ( C22P/N )

C04 ( C21P/N )

C09 ( VCL)

C08 ( C31P/N )

C07 ( VGL )

1uF / 6.3Volt.

C10 ( VDDD )

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 6.3 Volt.

1uF / 16 Volt.

1uF / 25 Volt.

1uF / 6.3 Volt.

1uF / 6.3 Volt.

OG

1

COG1 COG2

CO

G2

CA

BC

_PW

MO

UTCABC_PWMOUT

DB

5

IM2

DB

6

BC

_CT

RLD

B7

BC

_CT

RL

BC_CTRL

DB

8D

B9

C02

1u/6.3V (open)

DB

10

U1 BOE Panel

NU

LL2

VC

OM

3

VC

OM

4

VC

OM

5

FP

C_I

6

FP

C_O

7

TG

8

VC

OM

9

VC

OM

10

VC

OM

11

C22

P12

C22

N13

C21

P14

C21

N15

VG

H16

VG

H17

VG

L18

VG

L19

DD

VD

H20

DD

VD

H21

DD

VD

H22

C12

P23

C12

P24

C12

P25

C12

N26

C12

N27

C12

N28

C11

P29

C11

P30

C11

P31

C11

N32

C11

N33

C11

N34

VP

PO

TP

35

VP

PO

TP

36

VP

PO

TP

37

VC

I38

VC

I39

VC

I40

VC

I41

VS

SD

42

VS

SD

43

VS

SD

44

VS

SD

45

VS

SD

46

VS

SD

47

VS

SD

48

VS

SD

49

VS

SA

50

VS

SA

51

VS

SA

52

VS

SA

53

VS

SA

54

IFS

EL

55

IM3

56

IM2

57

IM1

58

IM0

59

NR

ES

ET

60

NC

S61

DN

C62

NW

R_S

CL

63

NR

D64

VS

YN

C65

HS

YN

C66

DE

67

DO

TC

LK68

SD

A69

DB

070

DB

171

DB

272

DB

373

DB

474

DB

575

DB

676

DB

777

DB

878

DB

979

DB

1080

DB

1181

DB

1282

DB

1383

DB

1484

DB

1585

DB

1686

DB

1787

TE

88

TE

ST

3/S

DO

89

BC

90

BC

_CT

RL

91

DU

MM

Y92

TE

ST

493

TE

ST

594

DU

MM

Y1

TE

ST

695

TE

ST

796

TE

ST

897

TE

ST

998

IOV

CC

99

IOV

CC

100

IOV

CC

101

IOV

CC

102

VD

DD

103

VD

DD

104

VD

DD

105

VD

DD

106

VD

DD

107

VD

DD

108

VR

EG

110

9

VR

EG

111

0

VR

EG

111

1

VC

L11

2

VC

L11

3

VC

L11

4

VC

L11

5

C31

P11

6

C31

P11

7

C31

P11

8

C31

N11

9

C31

N12

0

C31

N12

1

CO

NN

122

CO

NN

123

VC

OM

124

VC

OM

125

VC

OM

126

TG

127

FP

C_I

128

FP

C_O

129

VC

OM

130

VC

OM

131

VC

OM

132

NU

LL13

3

DU

MM

Y13

4

DB

11D

B12

IM3 IM1


IM2

0

0

IM0

0

Interface mode

0

00


10


0 00

00

1

-

11

-1

01

-

1

0 0

00

01

1

1

01

10


8080 MCU 9-bits Parallel type II1






DB

13D

B14

DB

15

VC

OM

VCOM

DB

16D

B17

/WR

/RD

VC

I

C051u/10V

IM1

IM2

IM3

/RE

SE

TIM

0

C041u/10V

VP

P_O

TP T

E

/CS

VG

H

C06

1u/25V

IOV

CC

RS

NOTES 2：Set IFSEL="1"；Command-Parameter interface mode.

VG

L

C07

1u/16V

C011u/6.3V V

DD

D

C101u/6.3V

CA

BC

_PW

MO

UT

IOV

CC


April, 2010




1.1-2 Initial Code for BOE 2.2”

//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); // Set_NOKIA_8B_PA(0x83); // Set_NOKIA_8B_PA(0x47); // Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(120); Set_NOKIA_8B_CMD(0x3A); //SET COLOR Set_NOKIA_8B_PA(0x06); // 06 262k//05 65k Set_NOKIA_8B_CMD(0xB6); //SETVCOM can reload from OTP Set_NOKIA_8B_PA(0x5A); // VMF Set_NOKIA_8B_PA(0x70); // VMH Set_NOKIA_8B_PA(0x58); // VML Set_NOKIA_8B_CMD(0xE0); // SETGAMMA Set_NOKIA_8B_PA(0x01); //1 Set_NOKIA_8B_PA(0x07); //2 Set_NOKIA_8B_PA(0x16); //3 Set_NOKIA_8B_PA(0x1E); //4 Set_NOKIA_8B_PA(0x1B); //5 Set_NOKIA_8B_PA(0x26); //6 Set_NOKIA_8B_PA(0x25); //7 Set_NOKIA_8B_PA(0x6F); //8 Set_NOKIA_8B_PA(0x02); //9 Set_NOKIA_8B_PA(0x1B); //A Set_NOKIA_8B_PA(0x1D); //B Set_NOKIA_8B_PA(0x1B); //C Set_NOKIA_8B_PA(0x16); //D Set_NOKIA_8B_PA(0x19); //1 Set_NOKIA_8B_PA(0x24); //2 Set_NOKIA_8B_PA(0x21); //3 Set_NOKIA_8B_PA(0x29); //4 Set_NOKIA_8B_PA(0x38); //5 Set_NOKIA_8B_PA(0x3E); //6 Set_NOKIA_8B_PA(0x10); //7 Set_NOKIA_8B_PA(0x5A); //8 Set_NOKIA_8B_PA(0x09); //9 Set_NOKIA_8B_PA(0x04); //A Set_NOKIA_8B_PA(0x02); //B Set_NOKIA_8B_PA(0x04); //C Set_NOKIA_8B_PA(0x1D); //D Set_NOKIA_8B_PA(0xCC); //E


April, 2010




Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(5); //Set GRAM Area Set_NOKIA_8B_CMD(0x2A); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0xEF); // Set_NOKIA_8B_CMD(0x2B); // Set_NOKIA_8B_PA(0x00); //1 Set_NOKIA_8B_PA(0x00); //2 Set_NOKIA_8B_PA(0x01); //3 Set_NOKIA_8B_PA(0x3F); //4 Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010





//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(150); Set_NOKIA_8B_CMD(0x35); //TE DelayX1ms(5); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x47); DelayX1ms(5); Set_NOKIA_8B_CMD(0xB0); // OSC Set_NOKIA_8B_PA(0x3A); // 90Hz DelayX1ms(5); Set_NOKIA_8B_CMD(0xB1); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x02); //BT Set_NOKIA_8B_PA(0x1A); //VREG1 Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0xD4); Set_NOKIA_8B_CMD(0xB5); // SETBGP Set_NOKIA_8B_PA(0x00); //VREF Set_NOKIA_8B_CMD(0xBF); //SETPTBA Set_NOKIA_8B_PA(0x00); //PTBA Set_NOKIA_8B_PA(0x00); //PTBA Set_NOKIA_8B_CMD(0xB4); // CYC Set_NOKIA_8B_PA(0x11); //NW Set_NOKIA_8B_PA(0x8F); //RTN Set_NOKIA_8B_PA(0x00); //DIV Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x0D); //GDON Set_NOKIA_8B_PA(0x88); //GDOFF Set_NOKIA_8B_CMD(0xE3); //Set EQ Panel Set_NOKIA_8B_PA(0x06); Set_NOKIA_8B_PA(0x01);


April, 2010




Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x06); Set_NOKIA_8B_CMD(0xC0); //Set STBA Set_NOKIA_8B_PA(0x7E); //OPON Set_NOKIA_8B_PA(0x38); //OPON Set_NOKIA_8B_PA(0x3C); //STBA Set_NOKIA_8B_PA(0xC6); //STBA Set_NOKIA_8B_PA(0x00); //GEN Set_NOKIA_8B_CMD(0xB6); // VCM //can reload from OTP Set_NOKIA_8B_PA(0xA3); // VMF Set_NOKIA_8B_PA(0x13); // VMH Set_NOKIA_8B_PA(0x78); // VML Set_NOKIA_8B_CMD(0xE0); //Gamma Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x0A); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x26); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x43); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x17); Set_NOKIA_8B_PA(0x17); Set_NOKIA_8B_PA(0x19); Set_NOKIA_8B_PA(0x35); Set_NOKIA_8B_PA(0x34); Set_NOKIA_8B_PA(0x38); Set_NOKIA_8B_PA(0x38); Set_NOKIA_8B_PA(0x3D); Set_NOKIA_8B_PA(0x3C); Set_NOKIA_8B_PA(0x7F); Set_NOKIA_8B_PA(0x08); Set_NOKIA_8B_PA(0x08); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x0F); Set_NOKIA_8B_PA(0x1F); Set_NOKIA_8B_PA(0xCC); Set_NOKIA_8B_CMD(0xCC); //SETPanel Set_NOKIA_8B_PA(0x09); // Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(120); Set_NOKIA_8B_CMD(0x2C);


April, 2010





//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(150); Set_NOKIA_8B_CMD(0x35); //TE DelayX1ms(5); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x47); DelayX1ms(5); Set_NOKIA_8B_CMD(0xB0); // OSC Set_NOKIA_8B_PA(0x3A); // 90Hz DelayX1ms(5); Set_NOKIA_8B_CMD(0xB1); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x02); //BT Set_NOKIA_8B_PA(0x1A); //VREG1 Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x44); Set_NOKIA_8B_PA(0x44); Set_NOKIA_8B_PA(0xD4); Set_NOKIA_8B_CMD(0xB5); // SETBGP Set_NOKIA_8B_PA(0x00); //VREF Set_NOKIA_8B_CMD(0xB4); // CYC Set_NOKIA_8B_PA(0x11); //NW Set_NOKIA_8B_PA(0x8F); //RTN Set_NOKIA_8B_PA(0x00); //DIV Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x0D); //GDON Set_NOKIA_8B_PA(0x88); //GDOFF Set_NOKIA_8B_CMD(0xE3); //Set EQ Panel Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x04); Set_NOKIA_8B_CMD(0xBF); //SETPTBA


April, 2010




Set_NOKIA_8B_PA(0x00); //PTBA Set_NOKIA_8B_PA(0x06); //PTBA Set_NOKIA_8B_CMD(0xC0); //Set STBA Set_NOKIA_8B_PA(0x84); //OPON Set_NOKIA_8B_PA(0x38); //OPON Set_NOKIA_8B_PA(0x3C); //STBA Set_NOKIA_8B_PA(0xC4); //STBA Set_NOKIA_8B_PA(0x00); //GEN Set_NOKIA_8B_CMD(0xB6); // VCM //can reload from OTP Set_NOKIA_8B_PA(0x80); // VMF Set_NOKIA_8B_PA(0x70); // VMH Set_NOKIA_8B_PA(0x58); // VML Set_NOKIA_8B_CMD(0xE0); //SET GAMMA Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x3C); Set_NOKIA_8B_PA(0x3C); Set_NOKIA_8B_PA(0x3E); Set_NOKIA_8B_PA(0x05); Set_NOKIA_8B_PA(0x78); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x0E); Set_NOKIA_8B_PA(0x13); Set_NOKIA_8B_PA(0x15); Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x38); Set_NOKIA_8B_PA(0x36); Set_NOKIA_8B_PA(0x3E); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x7A); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x0A); Set_NOKIA_8B_PA(0x0C); Set_NOKIA_8B_PA(0x11); Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0xCC); Set_NOKIA_8B_CMD(0xCC); //SETPanel Set_NOKIA_8B_PA(0x0B); // Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(120); Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010




1.2 GiantPlus 1.2-1GiantPlus 2.6”Reference FPC Circuit

VG

L

C07

1u/16V

C011u/6.3V V

DD

D

C101u/6.3V

CA

BC

_PW

MO

UT

IM2IM3 IM1


0

0

IM0

00

Interface mode

0

0


10


0 1 00

00

-

11

--1

01

1

0 0

100

01

1

01

110








IOV

CC

IM1IM0

IOVCC


IM3IM2

CO

G2

VC

L

CO

G1

C09

1u/6.3V

DB

0

DD

VD

H

C03

1u/10V

Title


Date: Sheet of


GP 2.6" FPC Rev A01

B

1 1Tuesday , October 12, 2010

DB

1



DB

2


DB

4

/CS

TE

VP

P_O

TP

VPP_OTP

DB

1

TE

VC

IV

CI DB

5

DB

3D

B2

IOV

CC

DB

3

GN

D

DB

16D

B15

DB

13

C081u/10V

J1Vci

1

Vci

2

GN

D3

Vcc

4

Vcc

5

RE

ST

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB

915

DB

816

DB

717

DB

618

DB

519

DB

420

DB

321

DB

222

DB

123

DB

024

RD

25

WR

26

RS

27

CS

28

FLM

29

GN

D30

BL+

31

BL-

32

DB

12

DB

9

DB

11

DB

17

DB

14

/RE

SE

T

/RD

DB

8

DB

6

DB

0

DB

10

DB

7

RS

/WR

GN

DT

E

VC

OM

1

VCOM1


C01 ( C11P/N )

DB

4

Capacitor Recommended spec.

C06 ( VGH )

1uF / 6.3Volt.

C03 ( DDVDH )

C09 ( VCL)

C04 ( C21P/N )

C05 ( C22P/N )

C07 ( VGL )

C08 ( C31P/N )

1uF / 10 Volt.

C10 ( VDDD )

1uF / 6.3Volt.

1uF / 6.3 Volt.

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 25 Volt.

1uF / 16 Volt.

1uF / 6.3 Volt.

1uF / 6.3 Volt.O

G1

COG1

CO

G2

COG2 CABC_PWMOUT

CA

BC

_PW

MO

UT

DB

5D

B6

BC

_CT

RLD

B7

DB

8

BC

_CT

RL

BC_CTRL

DB

9

C02

1u/6.3V (open)

DB

10D

B11

U1 GP Panel

NU

LL2

VC

OM

3

VC

OM

4

VC

OM

5

FP

C_I

6

FP

C_O

7

TG

8

VC

OM

9

VC

OM

10

VC

OM

11

C22

P12

C22

N13

C21

P14

C21

N15

VG

H16

VG

H17

VG

L18

VG

L19

DD

VD

H20

DD

VD

H21

DD

VD

H22

C12

P23

C12

P24

C12

P25

C12

N26

C12

N27

C12

N28

C11

P29

C11

P30

C11

P31

C11

N32

C11

N33

C11

N34

VP

PO

TP

35

VP

PO

TP

36

VP

PO

TP

37

VC

I38

VC

I39

VC

I40

VC

I41

VS

SD

42

VS

SD

43

VS

SD

44

VS

SD

45

VS

SD

46

VS

SD

47

VS

SD

48

VS

SD

49

VS

SA

50

VS

SA

51

VS

SA

52

VS

SA

53

VS

SA

54

IFS

EL

55

IM3

56

IM2

57

IM1

58

IM0

59

NR

ES

ET

60

NC

S61

DN

C62

NW

R_S

CL

63

NR

D64

VS

YN

C65

HS

YN

C66

DE

67

DO

TC

LK68

SD

A69

DB

070

DB

171

DB

272

DB

373

DB

474

DB

575

DB

676

DB

777

DB

878

DB

979

DB

1080

DB

1181

DB

1282

DB

1383

DB

1484

DB

1585

DB

1686

DB

1787

TE

88

TE

ST

3/S

DO

89

BC

90

BC

_CT

RL

91

DU

MM

Y92

TE

ST

493

TE

ST

594

DU

MM

Y1

TE

ST

695

TE

ST

796

TE

ST

897

TE

ST

998

IOV

CC

99

IOV

CC

100

IOV

CC

101

IOV

CC

102

VD

DD

103

VD

DD

104

VD

DD

105

VD

DD

106

VD

DD

107

VD

DD

108

VR

EG

110

9

VR

EG

111

0

VR

EG

111

1

VC

L11

2

VC

L11

3

VC

L11

4

VC

L11

5

C31

P11

6

C31

P11

7

C31

P11

8

C31

N11

9

C31

N12

0

C31

N12

1

CO

NN

122

CO

NN

123

VC

OM

124

VC

OM

125

VC

OM

126

TG

127

FP

C_I

128

FP

C_O

129

VC

OM

130

VC

OM

131

VC

OM

132

NU

LL13

3

DU

MM

Y13

4

DB

12

DB

14D

B13

DB

15D

B16

VC

OM

VCOM

DB

17

/WR

/RD

VC

I

C051u/10V

IM3

IM2

IM1

IM0

/RE

SE

T

C041u/10V

TE

VP

P_O

TP

VG

H

/CS

C06

1u/25V

IOV

CC

RS


April, 2010




1.2-2 Initial Code for GiantPlus 2.67”

//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); // Set_NOKIA_8B_PA(0x83); // Set_NOKIA_8B_PA(0x47); // Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(120); Set_NOKIA_8B_CMD(0x3A); //SET COLOR Set_NOKIA_8B_PA(0x06); // 06 262k//05 65k Set_NOKIA_8B_CMD(0xB6); //SETVCOM can reload from OTP Set_NOKIA_8B_PA(0x69); // VMF Set_NOKIA_8B_PA(0x70); // VMH Set_NOKIA_8B_PA(0x98); // VML Set_NOKIA_8B_CMD(0xE0); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x14); Set_NOKIA_8B_PA(0x11); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x1D); Set_NOKIA_8B_PA(0x5B); Set_NOKIA_8B_PA(0x0C); Set_NOKIA_8B_PA(0x1A); Set_NOKIA_8B_PA(0x1C); Set_NOKIA_8B_PA(0x1C); Set_NOKIA_8B_PA(0x1B); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x1A); Set_NOKIA_8B_PA(0x17); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x0A); Set_NOKIA_8B_PA(0x61); Set_NOKIA_8B_PA(0x08); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x0B); Set_NOKIA_8B_PA(0x14); Set_NOKIA_8B_PA(0xFF);


April, 2010




//Set GRAM Area Set_NOKIA_8B_CMD(0x2A); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0xEF); // Set_NOKIA_8B_CMD(0x2B); // Set_NOKIA_8B_PA(0x00); //1 Set_NOKIA_8B_PA(0x00); //2 Set_NOKIA_8B_PA(0x01); //3 Set_NOKIA_8B_PA(0x3F); //4 Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010




1.2-3 Initial Code for GiantPlus 2.83”

//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(150); Set_NOKIA_8B_CMD(0x35); //TE DelayX1ms(5); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x47); DelayX1ms(5); Set_NOKIA_8B_CMD(0xB0); // OSC Set_NOKIA_8B_PA(0x3A); // 90Hz DelayX1ms(5); Set_NOKIA_8B_CMD(0xB1); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x02); //BT Set_NOKIA_8B_PA(0x1A); //VREG1 Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0xD4); Set_NOKIA_8B_CMD(0xB5); // SETBGP Set_NOKIA_8B_PA(0x02); //VREF Set_NOKIA_8B_CMD(0xBF); //SETPTBA Set_NOKIA_8B_PA(0x00); //PTBA Set_NOKIA_8B_PA(0x06); //PTBA Set_NOKIA_8B_CMD(0xB4); // CYC Set_NOKIA_8B_PA(0x11); //NW Set_NOKIA_8B_PA(0x8F); //RTN Set_NOKIA_8B_PA(0x00); //DIV Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x2D); //GDON Set_NOKIA_8B_PA(0x88); //GDOFF Set_NOKIA_8B_CMD(0xE3); //Set EQ Panel Set_NOKIA_8B_PA(0x03);


April, 2010




Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_CMD(0xC0); //Set STBA Set_NOKIA_8B_PA(0x84); //OPON Set_NOKIA_8B_PA(0x38); //OPON Set_NOKIA_8B_PA(0x3C); //STBA Set_NOKIA_8B_PA(0xC7); //STBA Set_NOKIA_8B_PA(0x00); //GEN Set_NOKIA_8B_CMD(0xB6); // VCM //can reload from OTP Set_NOKIA_8B_PA(0x88); // VMF Set_NOKIA_8B_PA(0x77); // VMH Set_NOKIA_8B_PA(0x47); // VML Set_NOKIA_8B_CMD(0xE0); //SET GAMMA Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0x1E); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x1C); //18 Set_NOKIA_8B_PA(0x6C ); //6E Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x17); //16 Set_NOKIA_8B_PA(0x1B); Set_NOKIA_8B_PA(0x18); //1A Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x17); Set_NOKIA_8B_PA(0x21); Set_NOKIA_8B_PA(0x1D); Set_NOKIA_8B_PA(0x3C); Set_NOKIA_8B_PA(0x3C); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x0C); //0E Set_NOKIA_8B_PA(0x69); //65 Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x03); //05 Set_NOKIA_8B_PA(0x04); Set_NOKIA_8B_PA(0x0A); //09 Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_CMD(0xCC); //SETPanel Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(5); Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010




1.3 Tianama 1.3-1Tianma 2.83”Reference FPC Circuit

CO

G1

CO

G2

VC

L

C09

1u/6.3V

DB

0

DD

VD

H

C03

1u/10V

DB

1

Title


Date: Sheet of


Tianma 2.8" FPC Rev A01

B

1 1Wednesday , January 27, 2010



DB

4

VP

P_O

TP

DB

2

TE

/CS

VPP_OTP

IM0

DB

1

TE

IM1

VC

IV

CI

IOVCC

DB

5

DB

2D

B3

IOV

CC

DB

3


GN

D

DB

16

DB

13

DB

15

C081u/10V

J1Vci

1

Vci

2

GN

D3

Vcc

4

Vcc

5

RE

ST

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB

915

DB

816

DB

717

DB

618

DB

519

DB

420

DB

321

DB

222

DB

123

DB

024

RD

25

WR

26

RS

27

CS

28

FLM

29

GN

D30

BL+

31

BL-

32

DB

17

DB

11

DB

14

DB

12

DB

9

/RE

SE

T

DB

10

DB

6

DB

8

/WR

/RD

DB

7

GN

D

DB

0

IM3

RS

TE

VC

OM

1

VCOM1

Capacitor

C01 ( C11P/N )

DB

4


Recommended spec.

C04 ( C21P/N )

C03 ( DDVDH )

1uF / 6.3Volt.

C07 ( VGL )

C06 ( VGH )

C05 ( C22P/N )

C09 ( VCL)

C08 ( C31P/N )

1uF / 10 Volt.

1uF / 6.3Volt.

C10 ( VDDD )

1uF / 25 Volt.

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 6.3 Volt.

1uF / 16 Volt.

1uF / 6.3 Volt.

1uF / 6.3 Volt.

OG

1

COG1

CO

G2

COG2 CABC_PWMOUT

CA

BC

_PW

MO

UT

DB

5

IM2

DB

6

BC

_CT

RL

BC

_CT

RL

DB

7

BC_CTRL

DB

8D

B9

C02

1u/6.3V (open)

DB

10

U1 Tianma Panel

NU

LL2

VC

OM

3

VC

OM

4

VC

OM

5

FP

C_I

6

FP

C_O

7

TG

8

VC

OM

9

VC

OM

10

VC

OM

11

C22

P12

C22

N13

C21

P14

C21

N15

VG

H16

VG

H17

VG

L18

VG

L19

DD

VD

H20

DD

VD

H21

DD

VD

H22

C12

P23

C12

P24

C12

P25

C12

N26

C12

N27

C12

N28

C11

P29

C11

P30

C11

P31

C11

N32

C11

N33

C11

N34

VP

PO

TP

35

VP

PO

TP

36

VP

PO

TP

37

VC

I38

VC

I39

VC

I40

VC

I41

VS

SD

42

VS

SD

43

VS

SD

44

VS

SD

45

VS

SD

46

VS

SD

47

VS

SD

48

VS

SD

49

VS

SA

50

VS

SA

51

VS

SA

52

VS

SA

53

VS

SA

54

IFS

EL

55

IM3

56

IM2

57

IM1

58

IM0

59

NR

ES

ET

60

NC

S61

DN

C62

NW

R_S

CL

63

NR

D64

VS

YN

C65

HS

YN

C66

DE

67

DO

TC

LK68

SD

A69

DB

070

DB

171

DB

272

DB

373

DB

474

DB

575

DB

676

DB

777

DB

878

DB

979

DB

1080

DB

1181

DB

1282

DB

1383

DB

1484

DB

1585

DB

1686

DB

1787

TE

88

TE

ST

3/S

DO

89

BC

90

BC

_CT

RL

91

DU

MM

Y92

TE

ST

493

TE

ST

594

DU

MM

Y1

TE

ST

695

TE

ST

796

TE

ST

897

TE

ST

998

IOV

CC

99

IOV

CC

100

IOV

CC

101

IOV

CC

102

VD

DD

103

VD

DD

104

VD

DD

105

VD

DD

106

VD

DD

107

VD

DD

108

VR

EG

110

9

VR

EG

111

0

VR

EG

111

1

VC

L11

2

VC

L11

3

VC

L11

4

VC

L11

5

C31

P11

6

C31

P11

7

C31

P11

8

C31

N11

9

C31

N12

0

C31

N12

1

CO

NN

122

CO

NN

123

VC

OM

124

VC

OM

125

VC

OM

126

TG

127

FP

C_I

128

FP

C_O

129

VC

OM

130

VC

OM

131

VC

OM

132

NU

LL13

3

DU

MM

Y13

4

DB

12D

B11

IM3 IM1


IM2

0

IM0

0

0

Interface mode

0

00

10



000

00

1

11

-1-

01

-

0 0

001

01

1

01

101








DB

14D

B13

DB

15

VC

OM

VCOM

DB

16D

B17

/WR

/RD

VC

I

C051u/10V

IM3

IM0

IM1

IM2

/RE

SE

T

C041u/10V

VP

P_O

TP

VG

H

/CS

TE

C06

1u/25V

IOV

CC

RS


VG

L

C07

1u/16V

VD

DD

C011u/6.3V

C101u/6.3V

IOV

CC

CA

BC

_PW

MO

UT


April, 2010




1.3-2 Initial Code for Tianma 2.83”

//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(150); Set_NOKIA_8B_CMD(0x35); //TE DelayX1ms(5); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x47); DelayX1ms(5); Set_NOKIA_8B_CMD(0xB0); // OSC Set_NOKIA_8B_PA(0x3A); // 90Hz DelayX1ms(5); Set_NOKIA_8B_CMD(0xB1); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x02); //BT Set_NOKIA_8B_PA(0x1A); //VREG1 Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0x22); // Set_NOKIA_8B_PA(0xD4); Set_NOKIA_8B_CMD(0xB5); // SETBGP Set_NOKIA_8B_PA(0x00); //VREF Set_NOKIA_8B_CMD(0xBF); //Set PTBA Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_CMD(0xB4); // CYC Set_NOKIA_8B_PA(0x11); //NW Set_NOKIA_8B_PA(0x8F); //RTN Set_NOKIA_8B_PA(0x00); //DIV Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x33); //GDON Set_NOKIA_8B_PA(0x88); //GDOFF Set_NOKIA_8B_CMD(0xE3); //Set EQ Panel Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_PA(0x06);


April, 2010




Set_NOKIA_8B_PA(0x0A); Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_CMD(0xC0); //Set STBA Set_NOKIA_8B_PA(0x84); //OPON Set_NOKIA_8B_PA(0x38); //OPON Set_NOKIA_8B_PA(0x3C); //STBA Set_NOKIA_8B_PA(0xC4); //STBA Set_NOKIA_8B_PA(0x00); //GEN Set_NOKIA_8B_CMD(0xB6); // VCM //can reload from OTP Set_NOKIA_8B_PA(0x7D); // VMF Set_NOKIA_8B_PA(0x77); // VMH Set_NOKIA_8B_PA(0x5F); // VML Set_NOKIA_8B_CMD(0xE0); //SET GAMMA Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x1B); Set_NOKIA_8B_PA(0x17); Set_NOKIA_8B_PA(0x20); Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x55); //5B Set_NOKIA_8B_PA(0x05); Set_NOKIA_8B_PA(0x15); //14 16 Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0x16); //19 Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x1F); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x3E); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x20); //25 Set_NOKIA_8B_PA(0x7E); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x03); //06 Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x0B); //0B 0C Set_NOKIA_8B_PA(0x1A); Set_NOKIA_8B_PA(0xCC); Set_NOKIA_8B_CMD(0xC1); //SET DGC Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x08); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0x20); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x30); Set_NOKIA_8B_PA(0x38);


April, 2010




Set_NOKIA_8B_PA(0x40); Set_NOKIA_8B_PA(0x48); Set_NOKIA_8B_PA(0x50); Set_NOKIA_8B_PA(0x58); Set_NOKIA_8B_PA(0x60); Set_NOKIA_8B_PA(0x68); Set_NOKIA_8B_PA(0x70); Set_NOKIA_8B_PA(0x78); Set_NOKIA_8B_PA(0x80); Set_NOKIA_8B_PA(0x88); Set_NOKIA_8B_PA(0x90); Set_NOKIA_8B_PA(0x98); Set_NOKIA_8B_PA(0xA0); Set_NOKIA_8B_PA(0xA8); Set_NOKIA_8B_PA(0xB0); Set_NOKIA_8B_PA(0xB8); Set_NOKIA_8B_PA(0xC0); Set_NOKIA_8B_PA(0xC8); Set_NOKIA_8B_PA(0xD0); Set_NOKIA_8B_PA(0xD8); Set_NOKIA_8B_PA(0xE0); Set_NOKIA_8B_PA(0xE8); Set_NOKIA_8B_PA(0xF0); Set_NOKIA_8B_PA(0xF8); Set_NOKIA_8B_PA(0xFC); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x08); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0x20); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x33); Set_NOKIA_8B_PA(0x3B); Set_NOKIA_8B_PA(0x43); Set_NOKIA_8B_PA(0x4B); Set_NOKIA_8B_PA(0x50); Set_NOKIA_8B_PA(0x58); Set_NOKIA_8B_PA(0x60); Set_NOKIA_8B_PA(0x68); Set_NOKIA_8B_PA(0x70); Set_NOKIA_8B_PA(0x78); Set_NOKIA_8B_PA(0x80); Set_NOKIA_8B_PA(0x88); Set_NOKIA_8B_PA(0x90); Set_NOKIA_8B_PA(0x98); Set_NOKIA_8B_PA(0xA0); Set_NOKIA_8B_PA(0xA8); Set_NOKIA_8B_PA(0xB0); Set_NOKIA_8B_PA(0xB8); Set_NOKIA_8B_PA(0xBF); Set_NOKIA_8B_PA(0xC7);


April, 2010




Set_NOKIA_8B_PA(0xCF); Set_NOKIA_8B_PA(0xD7); Set_NOKIA_8B_PA(0xDF); Set_NOKIA_8B_PA(0xE8); Set_NOKIA_8B_PA(0xF0); Set_NOKIA_8B_PA(0xF7); Set_NOKIA_8B_PA(0xFA); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x08); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0x20); Set_NOKIA_8B_PA(0x28); Set_NOKIA_8B_PA(0x33); Set_NOKIA_8B_PA(0x3B); Set_NOKIA_8B_PA(0x43); Set_NOKIA_8B_PA(0x4B); Set_NOKIA_8B_PA(0x50); Set_NOKIA_8B_PA(0x58); Set_NOKIA_8B_PA(0x60); Set_NOKIA_8B_PA(0x68); Set_NOKIA_8B_PA(0x70); Set_NOKIA_8B_PA(0x78); Set_NOKIA_8B_PA(0x80); Set_NOKIA_8B_PA(0x88); Set_NOKIA_8B_PA(0x90); Set_NOKIA_8B_PA(0x98); Set_NOKIA_8B_PA(0xA0); Set_NOKIA_8B_PA(0xA8); Set_NOKIA_8B_PA(0xB0); Set_NOKIA_8B_PA(0xB8); Set_NOKIA_8B_PA(0xBF); Set_NOKIA_8B_PA(0xC7); Set_NOKIA_8B_PA(0xCF); Set_NOKIA_8B_PA(0xD7); Set_NOKIA_8B_PA(0xDF); Set_NOKIA_8B_PA(0xE8); Set_NOKIA_8B_PA(0xF0); Set_NOKIA_8B_PA(0xF7); Set_NOKIA_8B_PA(0xFA); Set_NOKIA_8B_CMD(0xCC); //SETPanel Set_NOKIA_8B_PA(0x09); // Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(120); Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010




1.3-3 Initial Code for Tianma 3.14”

//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(150); Set_NOKIA_8B_CMD(0x35); //TE DelayX1ms(5); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x47); DelayX1ms(5); Set_NOKIA_8B_CMD(0xB0); // OSC Set_NOKIA_8B_PA(0x3A); // 90Hz DelayX1ms(5); Set_NOKIA_8B_CMD(0xB1); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x02); //BT Set_NOKIA_8B_PA(0x1A); //VREG1 Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x22); Set_NOKIA_8B_PA(0x22); // Set_NOKIA_8B_PA(0xD4); Set_NOKIA_8B_CMD(0xB5); // SETBGP Set_NOKIA_8B_PA(0x00); //VREF Set_NOKIA_8B_CMD(0xBF); //Set PTBA Set_NOKIA_8B_PA(0x00); // Set_NOKIA_8B_PA(0x06); // Set_NOKIA_8B_CMD(0xB4); // CYC Set_NOKIA_8B_PA(0x11); //NW Set_NOKIA_8B_PA(0x8F); //RTN Set_NOKIA_8B_PA(0x00); //DIV Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x0D); //GDON Set_NOKIA_8B_PA(0x88); //GDOFF Set_NOKIA_8B_CMD(0xE3); //Set EQ Panel Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_PA(0x02);


April, 2010




Set_NOKIA_8B_PA(0x0A); Set_NOKIA_8B_PA(0x04); Set_NOKIA_8B_CMD(0xC0); //Set STBA Set_NOKIA_8B_PA(0x84); //OPON Set_NOKIA_8B_PA(0x38); //OPON Set_NOKIA_8B_PA(0x3C); //STBA Set_NOKIA_8B_PA(0xC4); //STBA Set_NOKIA_8B_PA(0x00); //GEN Set_NOKIA_8B_CMD(0xB6); // VCM //can reload from OTP Set_NOKIA_8B_PA(0x7D); // VMF Set_NOKIA_8B_PA(0x70); // VMH Set_NOKIA_8B_PA(0x58); // VML Set_NOKIA_8B_CMD(0xE0); //SET GAMMA Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x02); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x15); Set_NOKIA_8B_PA(0x20); Set_NOKIA_8B_PA(0x05); Set_NOKIA_8B_PA(0x59); //5B Set_NOKIA_8B_PA(0x05); Set_NOKIA_8B_PA(0x11); //14 16 Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x17); //19 Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x1F); Set_NOKIA_8B_PA(0x2A); Set_NOKIA_8B_PA(0x29); Set_NOKIA_8B_PA(0x3F); Set_NOKIA_8B_PA(0x3D); Set_NOKIA_8B_PA(0x3E); Set_NOKIA_8B_PA(0x26); //25 Set_NOKIA_8B_PA(0x7A); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x08); //06 Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x0E); //0B 0C Set_NOKIA_8B_PA(0x1A); Set_NOKIA_8B_PA(0xCC); Set_NOKIA_8B_CMD(0xCC); //SETPanel Set_NOKIA_8B_PA(0x09); // Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(120); Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010




1.4 CMI 1.4-1CMI 2.8”Reference FPC Circuit


Title


Date: Sheet of


CMO 2.8" FPC Rev A01

B

1 1Wednesday , March 30, 2011


TE

/CS

DB

4

VP

P_O

TP

VPP_OTP

DB

1

IM0

TE

VC

IV

CI

IM1

IOVCC

DB

2D

B3

DB

5


GN

D

IOV

CC

DB

16

DB

13

DB

15

J1Vci

1

Vci

2

GN

D3

Vcc

4

Vcc

5

RE

ST

6

DB

177

DB

168

DB

159

DB

1410

DB

1311

DB

1212

DB

1113

DB

1014

DB

915

DB

816

DB

717

DB

618

DB

519

DB

420

DB

321

DB

222

DB

123

DB

024

RD

25

WR

26

RS

27

CS

28

FLM

29

GN

D30

BL+

31

BL-

32

DB

11

DB

9

/RE

SE

T

DB

14

DB

12

DB

17

/RD

DB

7

DB

10

DB

6

DB

8

IM3

RS

TE

GN

D

DB

0

/WR


Recommended spec.Capacitor

C01 ( C11P/N )

C06 ( VGH )

C05 ( C22P/N )

C04 ( C21P/N )

C03 ( DDVDH )

1uF / 6.3Volt.

1uF / 10 Volt.

1uF / 6.3Volt.

C10 ( VDDD )

C09 ( VCL)

C08 ( C31P/N )

C07 ( VGL )

1uF / 6.3 Volt.

1uF / 16 Volt.

1uF / 25 Volt.

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 6.3 Volt.

1uF / 6.3 Volt.

COG1

OG

1

CABC_PWMOUTCOG2

CA

BC

_PW

MO

UT

CO

G2

IM2

BC_CTRL

BC

_CT

RL

C081u/10V

U1 CMO Panel

VC

OM

2

VC

OM

3

C22

P4

C22

N5

C21

P6

C21

N7

VG

H8

VG

H9

DU

MM

Y10

VG

L11

VG

L12

DU

MM

Y13

DD

VD

H14

DD

VD

H15

C12

P16

C12

P17

C12

N18

C12

N19

C11

P20

C11

P21

C11

N22

C11

N23

VP

P_O

TP

24

VC

I25

VC

I26

VS

SD

27

VS

SD

28

VS

SD

29

VS

SA

30

VS

SA

31

TE

ST

132

DU

MM

Y14

33

IFS

EL

34

IM3

35

IM2

36

IM1

37

IM0

38

RE

SX

39

NC

S40

DN

C_S

CL

41

NW

R_S

CL

42

NR

D43

VS

YN

C44

HS

YN

C45

DE

46

DO

TC

LK47

SD

A48

DB

049

DB

150

DB

251

DB

352

DB

453

DB

554

DB

655

DB

756

DB

857

DB

958

DB

1059

DB

1160

DB

1261

DB

1362

DB

1463

DB

1564

DB

1665

DB

1766

OS

C67

TE

68

TE

ST

369

PW

M_O

UT

70

BC

_CT

RL

71

DU

MM

Y11

72

TE

ST

473

TE

ST

574

TE

ST

675

TE

ST

776

TE

ST

877

TE

ST

978

IOV

CC

79

IOV

CC

80

VD

DD

81

VD

DD

82

VR

EG

183

VC

L84

VC

L85

C31

P86

C31

P87

C31

N88

C31

N89

CO

NN

190

CO

NN

291

VC

OM

L_D

UM

92

VC

OM

H_D

UM

93

VC

OM

_DU

M94

DU

MM

Y1

VC

OM

_DU

M95

DU

MM

Y96


IM2IM3

0

0

IM0IM1

000

Interface mode



100

0

1 000

-1-

110

0 001

-

1

1001

C011u/6.3V

101

010







IFSEL="1" COMMAND-PARAMETER INTERFACEC

OG

2C

OG

1


VCOM

VC

OM

VP

P_O

TP V

CI

VC

OM

VCOM

IOV

CC

/RD

/WR

/RE

SE

TIM

0IM

1IM

2IM

3

RS

/CS

C051u/10V

C041u/10V

VG

H

C06

1u/25V

DB

1D

B0

DB

6D

B5

DB

4D

B3

DB

2

DB

11D

B10

DB

9D

B8

DB

7

DB

17D

B16

DB

15D

B14

DB

13D

B12

VG

L

C07

1u/16V

TE

CA

BC

_PW

MO

UT

BC

_CT

RL

DD

VD

H

C03

1u/10V

IOV

CC

VD

DD

C101u/6.3V

C021u/6.3V (open)

VC

L

C09

1u/6.3V


April, 2010




1.4-2 Initial Code for CMI 2.8”

//##################################################################. M51_WR_REG(U05_LCD_POWER_ON, 0x0F); //VCI & IOVCC ON DelayX1ms(10); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); // SLPOUT DelayX1ms(150); Set_NOKIA_8B_CMD(0x35); //TE DelayX1ms(5); Set_NOKIA_8B_CMD(0xB9); //SETEXTC Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x47); DelayX1ms(5); Set_NOKIA_8B_CMD(0xB0); // OSC Set_NOKIA_8B_PA(0x36); // 70Hz DelayX1ms(5); Set_NOKIA_8B_CMD(0xB1); Set_NOKIA_8B_PA(0x00); Set_NOKIA_8B_PA(0x01); //BT Set_NOKIA_8B_PA(0x1A); //VREG1 Set_NOKIA_8B_PA(0x03); Set_NOKIA_8B_PA(0x44); Set_NOKIA_8B_PA(0x44); Set_NOKIA_8B_PA(0xD4); Set_NOKIA_8B_CMD(0xB4); // CYC Set_NOKIA_8B_PA(0x11); //NW Set_NOKIA_8B_PA(0x8F); //RTN Set_NOKIA_8B_PA(0x00); //DIV Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x04); //DUM Set_NOKIA_8B_PA(0x1D); //GDON Set_NOKIA_8B_PA(0x88); //GDOFF Set_NOKIA_8B_CMD(0xE3); //Set EQ Panel Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_PA(0x10); Set_NOKIA_8B_CMD(0xBF); //SETPTBA Set_NOKIA_8B_PA(0x00); //PTBA Set_NOKIA_8B_PA(0x00); //PTBA


April, 2010




Set_NOKIA_8B_CMD(0xC0); //Set STBA Set_NOKIA_8B_PA(0x70); //OPON Set_NOKIA_8B_PA(0x38); //OPON Set_NOKIA_8B_PA(0x3C); //STBA Set_NOKIA_8B_PA(0xC7); //STBA Set_NOKIA_8B_PA(0x00); //GEN Set_NOKIA_8B_CMD(0xB6); // VCM //can reload from OTP Set_NOKIA_8B_PA(0x57); // VMF Set_NOKIA_8B_PA(0x70); // VMH Set_NOKIA_8B_PA(0x58); // VML Set_NOKIA_8B_CMD(0xE0); //SET GAMMA Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x1F); Set_NOKIA_8B_PA(0x1C); Set_NOKIA_8B_PA(0x3E); Set_NOKIA_8B_PA(0x1B); Set_NOKIA_8B_PA(0x6B); Set_NOKIA_8B_PA(0x07); Set_NOKIA_8B_PA(0x13); Set_NOKIA_8B_PA(0x19); Set_NOKIA_8B_PA(0x19); Set_NOKIA_8B_PA(0x16); Set_NOKIA_8B_PA(0x01); Set_NOKIA_8B_PA(0x23); Set_NOKIA_8B_PA(0x20); Set_NOKIA_8B_PA(0x38); Set_NOKIA_8B_PA(0x38); Set_NOKIA_8B_PA(0x3E); Set_NOKIA_8B_PA(0x14); Set_NOKIA_8B_PA(0x64); Set_NOKIA_8B_PA(0x09); Set_NOKIA_8B_PA(0x06); Set_NOKIA_8B_PA(0x06); Set_NOKIA_8B_PA(0x0C); Set_NOKIA_8B_PA(0x18); Set_NOKIA_8B_PA(0xCC); Set_NOKIA_8B_CMD(0xCC); //SETPanel Set_NOKIA_8B_PA(0x09); // Set_NOKIA_8B_CMD(0x29); // display on DelayX1ms(120); Set_NOKIA_8B_CMD(0x2C); //Start GRAM write


April, 2010




2. RGB Mode Reference FPC Circuit

IM3

IM0

IM1

DB

6D

B7

DB

8

IOV

CC

IOV

CC

Capacitor

C01 ( C11P/N ) 1uF / 6.3Volt.


Recommended spec.

C04 ( C21P/N )

C03 ( DDVDH )

C07 ( VGL )

C06 ( VGH )

C05 ( C22P/N )

C10 ( VDDD )

C09 ( VCL)

C08 ( C31P/N )

DB

9

1uF / 10 Volt.

1uF / 6.3Volt.

1uF / 25 Volt.

1uF / 10 Volt.

1uF / 10 Volt.

1uF / 6.3 Volt.

1uF / 6.3 Volt.

1uF / 16 Volt.

1uF / 6.3 Volt.

NR

ES

ET DB

10

C120603/1u/10V

VC

L

NC

S

DB

11

DN

C_S

CL

DB

12

VS

YN

C DB

13

VS

YN

C

DE

DO

TC

LK

HS

YN

C

HSYNCHSYNC

ENABLEENABLE

DOTCLKDOTCLK

VSYNCVSYNC

HS

YN

C DB

14D

B15

DB

16

DD

VD

H

DB

17

CA

BC

PW

M

DO

TC

LK

VR

EG

1

DE

NR

ES

ET

DN

C_S

CL

DD

VD

H

VC

L

NC

S

VR

EG

1

VG

H

VG

L

VC

OM

VD

DD

C11AB30603/1u/6.3V

C11NC11P

VCOM2VCOM

NCS2NCS

C22

P

VDDD2VDDD

DNC_SCL1DNC_SCL1

SD

A

DDVDH2DDVDH

C12NC12P

C12AB1 (OPEN)20603/1u/6.3V

VG

H

C3

1P

C31P

C31AB20603/1u/6.3V

C31N

C70603/1u/6.3V

VCL2VCL


NRESET2NRESET

VGL2VGL

VD

DD

IOV

CC

IOV

CC

NR

ES

ET

VC

I

VREG2VREG1

VGH2VGH

C1

1PC

11N

GN

D

C90603/1u/10V

C22

N

C10

0603/1u/25V

C3

1N

C11

0603/1u/16V

VG

L

C21NC21P

C21AB30603/1u/10V

C22AB30603/1u/10V

C1

2P

C22P

C1

2N

C22N

C21

NC

21P

GN

D

CO

NN

2C

ON

N1

VP

P_

OT

P

BC

_CT

RL

SD

A

DN

C__

SC

LN

CS VSSA

GN

D

VSSD

VSSC

VS

SD

VS

SA

VS

SC

GND3GND

GND4GND

J2

FPC60-0.5-4.0L

VC

I1

VC

I2

GN

D3

VC

C4

IOV

CC

5

nRE

SE

T6

DB

17

13

DB

16

14

DB

15

15

DB

14

16

DB

13

17

DB

12

18

DB

11

19

DB

10

20

DB

921

DB

822

DB

723

DB

624

DB

525

DB

426

DB

327

DB

228

DB

129

DB

030

nR

D_E

31

NW

R_R

NW

32

DN

C33

nC

S34

FLM

35

GN

D36

PW

M_O

UT

37

VS

YN

C38

HS

YN

C39

DO

TC

LK40

EN

AB

LE41

SD

O42

SD

I43

NC

44

SH

UT

45

RL

46

TB

47

IDM

48

RE

V49

RC

M0

50

RC

M1

51

EX

TC

52

DB

S53

IM3

54

IM2

55

IM1

56

IM0

57

GN

D58

BL+

/NC

59

BL_

GN

D/N

C60

DB

23

7

DB

22

8

DB

21

9

DB

20

10

DB

19

11

DB

18

12

VC

I

VC

I

IOV

CC

VCI2VCI

IOVCC2IOVCC

DB

11

DB

5

DB

15

DB

13

DB

10

DB

8D

B9

DB

12

DB

14

DB

3D

B4

DB

7

DB

2

DB

0

DB

6

DB

16

DB

1

DB

17

VS

YN

C

DB

0

HS

YN

C

DB

1

DO

TC

LK

DB

2

BC_CTRL2BC_CTRL

BC

_C

TR

L

DE

DB

3

CO

NN

1

CONN3CONN1

CO

NN

2

CONN4CONN2

CA

BC

PW

M

PWM1PWM

U2

HX8347-G (BUMP UP)C12

P

C31

P

VS

SD

IM0

NR

ES

ET

NC

SD

NC

_S

CL

NW

R_S

CL

NR

DT

ES

T2

VS

YN

C

VG

L

CO

NN

VG

H

G2

G4

G32

0

G1

G3

G31

7G

319

S1

S2

S3

S72

0S

719

S71

8

G6

G31

8

G31

5

G5

DD

VD

H

C31

N

C22

NC

22P

VC

OM

IM2

TE

ST

1

IM3

VS

SA

IFS

EL

VS

SD

IM1

DU

MM

Y27

DU

MM

Y

DU

MM

Y23

DU

MM

Y24

S26

2S

263

S36

1S

265

S26

6S

267

C21

PC

21N

DE

DO

TC

LKS

DA

DB

0D

B1

DB

2D

B3

DB

4D

B5

DB

6D

B7

DB

8D

B9

DB

10

DB

11

DB

12

DB

13

DB

14

DB

15

DB

16

DB

17

OS

CT

ET

ES

T3

CA

BC

_PW

M_O

UT

BC

_C

TR

LT

ES

T4

TE

ST

5T

ES

T6

TE

ST

7T

ES

T8

TE

ST

9T

ES

T10

IOV

CC

VR

EG

1V

CL

VP

P_O

TP

VC

I

C11

N

CO

NN

C12

N

VT

ES

T

VC

OM

_DU

MM

YV

CO

MH

_DU

MM

YV

CO

ML_

DU

MM

Y

HS

YN

C

VD

DD

C11

P

240RGB x 320 TFT Panel

DB

4

VPP_OTP2VPP_OTP

VP

P_

OT

P

DB

5

Figure 2. 2 HX8347-G SPI+RGB Application Reference Circuit


April, 2010




2.1. SPI+RGB Mode Reference Initial Code //##################################################################. M51_WR_REG(U13_RGB_IF_ENABLE, 0x13); // RGB IF TIMING ENABLE. DelayX1ms(5); //RESET M51_WR_REG(U05_LCD_RST, 0x01); // LCD HW RST Enable DelayX1ms(5); M51_WR_REG(U05_LCD_RST, 0x00); // LCD HW RST Disable. DelayX1ms(10); SPI_3W_SET_CMD(0xB9); // SETEXTC SPI_3W_SET_Pas(0xFF); // SPI_3W_SET_Pas(0x83); // SPI_3W_SET_Pas(0x47); // SPI_3W_SET_CMD(0x11); // SLPOUT DelayX1ms(120); SPI_3W_SET_CMD(0xCC); //SET Panel SPI_3W_SET_Pas(0x09); // SPI_3W_SET_CMD(0xB3); // SET RGB mode SPI_3W_SET_Pas(0x00); // DPL,HPL,VPL,EPL SPI_3W_SET_Pas(0x02); // RCM[1:0] SPI_3W_SET_Pas(0x08); // HBP SPI_3W_SET_Pas(0x04); // HBP,VBP Set_NOKIA_8B_CMD(0x3A); //SET COLOR Set_NOKIA_8B_PA(0x60); // 60 262k//50 65k SPI_3W_SET_CMD(0xB6); //SETVCOM, can reload from OTP SPI_3W_SET_Pas(0x88); // VMF SPI_3W_SET_Pas(0x2F); // VMH SPI_3W_SET_Pas(0x57); // VML SPI_3W_SET_CMD(0xE0); // SETGAMMA SPI_3W_SET_Pas(0x00); //1 SPI_3W_SET_Pas(0x00); //2 SPI_3W_SET_Pas(0x01); //3 SPI_3W_SET_Pas(0x12); //4 SPI_3W_SET_Pas(0x10); //5 SPI_3W_SET_Pas(0x26); //6 SPI_3W_SET_Pas(0x08); //7 SPI_3W_SET_Pas(0x54); //8 SPI_3W_SET_Pas(0x02); //9 SPI_3W_SET_Pas(0x15); //A SPI_3W_SET_Pas(0x19); //B SPI_3W_SET_Pas(0x19); //C SPI_3W_SET_Pas(0x16); //D SPI_3W_SET_Pas(0x19); //1 SPI_3W_SET_Pas(0x2F); //2 SPI_3W_SET_Pas(0x2D); //3 SPI_3W_SET_Pas(0x3E); //4 SPI_3W_SET_Pas(0x3F); //5


April, 2010




SPI_3W_SET_Pas(0x3F); //6 SPI_3W_SET_Pas(0x2B); //7 SPI_3W_SET_Pas(0x77); //8 SPI_3W_SET_Pas(0x09); //9 SPI_3W_SET_Pas(0x06); //A SPI_3W_SET_Pas(0x06); //B SPI_3W_SET_Pas(0x0A); //C SPI_3W_SET_Pas(0x1D); //D SPI_3W_SET_Pas(0xCC); //E SPI_3W_SET_CMD(0x29); // display on DelayX1ms(5);


April, 2010




3. OTP Programming YA[2:0]=11

1 YA[2:0]=1

10 YA[2:0]=1

01 YA[2:0]=1

00 YA[2:0]=0

11 YA[2:0]=0

10 YA[2:0]=0

01 YA[2:0]=0

00 Non-Prog

ram XA[4:0]=00000 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 00h XA[4:0]=00001 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 00h XA[4:0]=00010 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 00h XA[4:0]=00011 VMF17 VMF16 VMF15 VMF14 VMF13 VMF12 VMF11 VMF10 00h XA[4:0]=00100 VMF17 VMF16 VMF15 VMF14 VMF13 VMF12 VMF11 VMF10 00h XA[4:0]=00101 VMF17 VMF16 VMF15 VMF14 VMF13 VMF12 VMF11 VMF10 00h XA[4:0]=00110 VMH7 VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0 00h XA[4:0]=00111 VML7 VML6 VML5 VML4 VML3 VML2 VML1 VML0 00h XA[4:0]=01000 Valid_ID Valid_VML Valid_VM

H Valid_VM

F3 Valid_VM

F2 Valid_VM

F1 00h

XA[4:0]=01001 Valid_panel

DDVDH_TRI

SS_Panel GS_Panel REV_Panel

BGR_Panel

00h

Table 3. 1 OTP Address Mapping

Find optimized value and record them(Only ‘1’ needs to be programed)

Set OTP_OTPEN=’1’(RB7h=14h)

Set OTP_PPRog=’1’(RB7h=16h)

Apply external Voltage to VPP 6.5V

Set related Address to XA[4:0] & YA[2:0]

Set OTP_PWE=’1’(RB7h=17h)

Set OTP_PWE=’0’(RB7h=16h)

Floating external Voltage 6.5V

Set OTP_PPRog=’0’(RB7h=14h)

Set OTP_OTPEN=’0’(RB7h=00h)

Re-Power on

Wait 600us

Wait 1us

Wait 1us

Wait 1us

Wait 1us

Wait 1us

Wait 1us

Wait 1us

Wait 1us

Note: Valid bit must program if user want use this OTP function Figure 3. 3 OTP flow


April, 2010




4. Revision History

Version Date Description of changes 2010/4/16 New setup 2010/8/31 Modify page title.

2010/10/12 Add GP 2.6” application

01

2011/03/30 Add BOE 2.83” and 3.14” application Add GP 2.83” application Add Tianma 2.83” and 3.14” application Add CMI 2.83” application

hx8347-g n an preliminary v01.03 20110330 · ( doc no. hx8347 -g(n) -an ) hx8347-g(n) 240rgb x 320...

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