hpps 2008 - filieri

IntroductionFormal models

Scheduling problemPerformance evaluation

Scheduling with timed automata

for temporal properties veri�cation via

model-checking

Antonio Filieri1

1Politecnico di Milano and University of Illinois at Chicago

720463 antonio.�[email protected]

Tutors: Marco D. Santambrogio, Paola Spoletini

HPPS PrjDAY - Jun 19, Milan

Antonio Filieri Scheduling with Timed Automata - 1/24



Outline

1 IntroductionWhy this work?What are we trying to do?

2 Formal modelsHow to describe a process?What is a Timed Automata?

3 Scheduling problemWhat do we mean with scheduling?How can we use Timed Automata?How can this stu� schedule?

4 Performance evaluationIs the method e�ective?




Problem statement and motivationsObjectives

Outline









Scheduling problem

Several tasks with dependencies one to each other, have to beexecuted on a limited, typically not su�cient amount ofresources.

Common approach: existence of certain known results drivesthe choice of problem formulation.

Optimal very expensive schedules Xor Sub-optimal faster ones.

Lot of ad-hoc solutions in each �eld.





Outline









Objectives of the project

1 Analyze scheduling algorithms based on Timed Automata interms of expressiveness and reusability of the model,complexity vs solution quality trade-o�, performance in simpleFPGA scheduling problem.

2 Complexity considerations, possible improvements and main

drawbacks.




Process ModelTimed automata

Outline









Process de�nition: static viewpoint

A process is de�ned as a set of tasks.

Basic description by extended DAGs (G =< V ,E ,W ,R >)based on DFGs.

Simplifying assumptions:

A task has associated a functional unit that can execute it.

A task cannot be preempted.

For each task con�guration and execution time are known apriori.





Outline









Timed Automata, UPPAAL extension

Timed automata concepts:

It is a �nite-state automaton with a �nite collection ofreal-valued clocks.Boolean conditions as well as clock evaluation.Keep in a state may require a staying condition holds.Transitions taken if �re condition satis�ed.Transition �ring can reset clocks.

Some UPPAAL enhancement:

Guard condition on transition must hold in order to �re.Synchronization channels point2point and broadcast.Finite domain integer variables.




FormalizationCase of studyVeri�cation

Outline









Scheduling formalization

A schedule for a problem J = (P,≺,M,µ,d) is determined bythe function st : P→R+ indicating the start time of each task.

Deterministic setting =⇒ en(p) = st(p)+d(p).

Feasible schedule if:1 Precedence: for every p,p′ ∈ P,p ≺ p′⇒ en(p)≤ st(p′).2 Mutual exclusion: for every two tasks p,p′ such that

µ(p) = µ(p′), [st(p),en(p)]∩ [st(p′),en(p′)] = /0.

The duration of a schedule is max{en(p) : p ∈ P}.An optimal schedule is one whose length is minimal.





Outline









1D FPGA scheduling, con�icts and assumptions

Con�guration prefetch: allow FU to be placed sometimesbefore execution.

FPGA uniformly recon�gurable: no reserved areas.

Partially Runtime-Recon�gurable (PRTR) FPGA (e.g. Virtexseries).

No speci�c policy with respect to placement: anywhere, free=⇒ usable.

Time to recon�gure proportional to required area.





Task modeling in UPPAALDynamic task model.

Task model

Done

Executingc<=E[tid]

Reconfigured

Reconfiguringc<=R[tid]

Init

c==E[tid]

RemoveTask(tid),done[tid]=true

PredAllDone(tid)

go?

c:=0

c==R[tid]

inuseR:=false

col:int[1,nC-1]

!inuseR && CanProceed(tid,col)

AllocateTask(tid,col),inuseR:=true,c:=0

Variables and constants

number of columns on the FPGA:int nC

number of tasks: int nTcolumns busy: bool inuse[nC +1]Recon�guration controller busy:bool inuseR

Task recon�guration times:int R[nT +1]Task execution times: int E [nT +1]Task required area: int W [nT +1]Task's leftmost column:int position[nT +1]





Outline









Scheduling by model-checking

Operational model and model-checking:

Possible behaviors of a system: correct sequences of states.

A model-checker search paths in a �nite state space from aninitial state.

Temporal logics (mainly LTL & CTL) can express a path'sproperties.

Properties of a schedule:

Reachability property: E<> P1.Done and P2.Done and ...

A feasible schedule is a path satisfying the reachabilityproperty.

An optimal schedule is one of the "fastest" feasible schedules(UPPAAL can �nd it).





Example of results

ProcessFeasible Sch. Optimal Sch.




Computation TimeConclusionsQuestions

Outline









Performance environment

Tests results coming RTAS07 proceedings, our own not yetcompleted.

Task graph randomly generated with TGFF utility.

1 to 3 start nodes, max input 2, max output 2.

Recon�guration time = width.

Computation time ∈ [4,12] width ∈ [3,9].

Model checking on Linux workstation, 4x AMD Opteron844(1.8GHz) 1MB E-Cache, 8GB RAM.

UPPAL command −t2 option.

Heuristic from [Banerjee, Bozorgzadeh 2005].





Memory and time costs

Memory cost Time cost

100 test cases from 8 to 20 tasks per set.





Quality of results vs heuristic

Remark: Optimal DAG scheduling is, in general, NP-complete.

15 columns 20 columns

100 test cases per each task number.





Quality of results vs heuristic

Timed automata are very high level descriptions.

Identifying an already computed subnet, its possible to reuseresults for sub-optimal fast scheduling.

Performance really depends on num of tasks, timing, andshape.

Worst-case exponential, best case (sequential tasks) linearwith respect to number of tasks.

Not so bad until 18 tasks because of optimality (really needit?).

Possible to exploit well-known shortest path algorithm to buildspecial purpose checkers.

Possible to express complex scheduling request (e.g. E<>T<20 and T1.Done and (T2.Done xor T3.Done) ).





Thanks for listening

Any question?

Any suggestion?

Any comment?


hpps 2008 - filieri

Economy & Finance

timed automata

antonio filieri1

politecnicodi milano

university of illinois

introduction formal