high speed digital design project
DESCRIPTION
High Speed Digital Design Project. SpaceWire Router. Part A Final Presentation. By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: October 2008. Project Goal. - PowerPoint PPT PresentationTRANSCRIPT
High Speed Digital Design ProjectHigh Speed Digital Design Project
SpaceWire RouterSpaceWire Router
By: Asaf Bercovich & Oren Cohen
Advisor: Mony Orbach
Semester: Winter 2007/2008
2-Semester Project
Date: October 2008
Part A Final Presentation
Project GoalProject Goal
• Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard.
• The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.
• Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard.
• The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.
System TopologySystem Topology
RouterRouter
System TopologySystem Topology
RouterRouter
PORT
• Full duplex
• Low latency
• Point-to-point
• Wormhole Routing
• Asynchronous communication
• Automatic failover
• 400 Mb/s of Traffic Total
Layer 2 (Character Level) Network Port
ReceiverReceiver
D1117 SpaceWire PortD1117 SpaceWire PortArchitectureArchitecture
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
Sys ClockSys Clock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start Link Start
State MachineState Machine
TransmitterTransmitter
FIFOFIFORX CLOCKRX CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Link ReadyLink Ready
TX ClockTX
Clock
Tx ClockTx Clock
Shift Register
Shift Register
LogicLogic
Port Transmitter“The Factory”
Port Transmitter“The Factory”
ControllerController
DoutDout
SoutSout
SpaceWire Character
TX Clock
DS Encoder
DS Encoder
TX DATA
Control Signals
LogicLogic LogicLogic
Layer 2 (Character Level) Network Port
ReceiverReceiver
D1117 SpaceWire PortD1117 SpaceWire PortArchitectureArchitecture
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
Sys ClockSys Clock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start Link Start
State MachineState Machine
TransmitterTransmitter
FIFOFIFORX CLOCKRX CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Link ReadyLink Ready
Tx ClockTx Clock
Port ReceiverPort Receiver
Shift Register
Shift Register
MEM
Error Reporting
RX_DATA to FIFO
RX Clock RecoveryRX Clock Recovery
DinDin
SinSin
Rx Clock
DinDinLogicLogic LogicLogic
Layer 2 (Character Level) Network Port
ReceiverReceiver
D1117 SpaceWire PortD1117 SpaceWire PortArchitectureArchitecture
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
Sys ClockSys Clock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start Link Start
State MachineState Machine
TransmitterTransmitter
FIFOFIFORX CLOCKRX CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Link ReadyLink Ready
Tx ClockTx Clock
Internal SignalsInternal SignalsTransmitterTransmitter
ReceiverReceiver
Port C
ontroller
(State M
achine)
RESETSend NULLsSend FCTsSend N-CharsSend Time-Codes
GotFCT
Got Time-CodeGotN-CharGotNULLCreditErrorRX_Err
RESET
Port Main Control – OverviewPort Main Control – Overview
Error Wait
Reset TxEnable Rx
Error Reset
Reset TxReset Rx
Ready
Reset TxEnable Rx
Started
Send NullEnable Rx
Connecting
Send Fct/NullEnable Rx
Run
Send AllEnable Rx
After 6.4 ɥs
A
fter 12.8 ɥs
[Link Start] Got Null
G
ot Fct
Rx Err OR Credit Error
[Link Disabled]
A
fter 12.8 ɥs
Rx Err OR
Got FctGot NChar
Rx Err OR
Got Fct
Got NChar
R
x Err O
RG
ot F
ctG
ot N
Ch
ar
Rx Err
OR
After 1
2.8
ɥsG
ot N
Cha
r
?
Port Main Control - ProblemPort Main Control - Problem
Error Wait
Reset TxEnable Rx
Error Reset
Reset TxReset Rx
Ready
Reset TxEnable Rx
Started
Send NullEnable Rx
Connecting
Send Fct/NullEnable Rx
Run
Send AllEnable Rx
After 6.4 ɥs
A
fter 12.8 ɥs
[Link Start] Got Null
G
ot FC
T
Rx Err OR Credit Error
[Link Disabled]
A
fter 12.8 ɥs
Rx Err OR
Got FCTGot NChar
Rx Err OR
Got FCT
Got NChar
R
x Err O
RG
ot F
CT
Go
t NC
har
Rx Err
OR
After 1
2.8
ɥsG
ot N
Cha
r
Port Main Control - ResolutionPort Main Control - Resolution
Error Wait
Reset TxEnable Rx
Error Reset
Reset TxReset Rx
Ready
Reset TxEnable Rx
Started
Send NullEnable Rx
Connecting
Send Fct/NullEnable Rx
Run
Send AllEnable Rx
After 6.4 ɥs
A
fter 12.8 ɥs
[Link Start] Got Null
G
ot FC
T
Rx Err OR Credit Error
[Link Disabled]
A
fter 12.8 ɥs
Rx Err OR
Got FCTGot NChar
Rx Err OR
Got FCT
Got NChar
R
x Err O
RG
ot F
CT
Go
t NC
har
Rx Err
OR
After 1
2.8
ɥsG
ot N
Cha
r
ReceiverReceiver
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
Sys ClockSys Clock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start Link Start
State MachineState Machine
FIFOFIFORX CLOCKRX CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Tx ClockTx Clock
Link ReadyLink Ready
Layer 2 (Character Level) Network Port
TransmitterTransmitter
D1117 SpaceWire PortD1117 SpaceWire PortLVDS InterfaceLVDS Interface
LVDS Drivers
Din+
Din-
Sin+
Sin-
Dout+
Sout+
Sout-
Dout-
SpaceWire InterfaceSpaceWire Interface
• SpaceWire connectors are driven by Low Voltage Differential Signaling (LVDS) system (2.5 Volts).
• Signal conversion to LVDS is required.
• SpaceWire connectors are driven by Low Voltage Differential Signaling (LVDS) system (2.5 Volts).
• Signal conversion to LVDS is required.
Inner shieldDin+
Din- Sin- Sout+ Dout+
Sin+ Sout- Dout-
SpaceWire PinOut
Testing The CoreTesting The Core• Programming GR-RASTA Board (based on
VirtexII) with the SpaceWire Port’s Core.
• Programming GR-RASTA Board (based on VirtexII) with the SpaceWire Port’s Core.
• Connecting the RASTA-Board SPW interface to Gaisler’s GRESB SpaceWire Bridge.
• Connecting the RASTA-Board SPW interface to Gaisler’s GRESB SpaceWire Bridge.
• Verifying correctness of our core by sending megabytes of files between our port and the GRESB bridge and vice versa.
• Verifying correctness of our core by sending megabytes of files between our port and the GRESB bridge and vice versa.
iMPACTmonitoring
Project MilestonesFocus on the Router
Project MilestonesFocus on the Router
• Examination of several switching architectures.
• Designing the network configuration and layout.
• Implementation of the router core and supporting logics.
• Validating correctness of the router.
• Examination of several switching architectures.
• Designing the network configuration and layout.
• Implementation of the router core and supporting logics.
• Validating correctness of the router.