high speed digital design project
DESCRIPTION
High Speed Digital Design Project. SpaceWire Router. Midterm Presentation. By: Asaf Bercovich & Oren Cohen Advisor: Mony Orbach Semester: Winter 2007/2008 2-Semester Project Date: 7 January 2008. Project Goal. - PowerPoint PPT PresentationTRANSCRIPT
High Speed Digital Design ProjectHigh Speed Digital Design Project
SpaceWire RouterSpaceWire Router
By: Asaf Bercovich & Oren Cohen
Advisor: Mony Orbach
Semester: Winter 2007/2008
2-Semester Project
Date: 7 January 2008
Midterm Presentation
Project GoalProject Goal
• Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard.
• The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.
• Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A Standard.
• The design will be coded and simulated using Xilinx development enviroment and implemented onto a Xilinx VirtexII-Pro FPGA.
System TopologySystem Topology
RouterRouter
System TopologySystem Topology
RouterRouter
PORT
• Full duplex
• Low latency
• Point-to-point
• Wormhole Routing
• Asynchronous communication
• Automatic failover
• 800 Mb/s of Traffic Total
SpaceWire CharactersSpaceWire Characters
• There are only 5 Characters:• There are only 5 Characters:
FCT – “Flow Control Token"
ESC – “Escape”
FCT – “Flow Control Token"
ESC – “Escape”
EOP – “End Of Packet”
EEP – “End of Packet with Error”
EOP – “End Of Packet”
EEP – “End of Packet with Error”
NCHAR – “Normal Character”NCHAR – “Normal Character”
The SpaceWire PortThe SpaceWire PortEntityEntityArchitectureArchitecture
ReceiverReceiver
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
ClockClock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start /
Link Disable
Link Start /
Link Disable
State MachineState Machine
TX ClockTX
Clock
TransmitterTransmitter
FIFOFIFORX_CLOCKRX_CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
ReceiverReceiver
The SpaceWire PortThe SpaceWire PortArchitectureArchitecture
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
ClockClock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start /
Link Disable
Link Start /
Link Disable
State MachineState Machine
TX ClockTX
Clock
TransmitterTransmitter
FIFOFIFORX_CLOCKRX_CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Internal SignalsInternal SignalsTransmitterTransmitter
ReceiverReceiver
Port C
ontroller
(State M
achine)
Port C
ontroller
(State M
achine)
RESETSend NULLsSend FCTsSend N-CharsSend Time-Codes
GotFCT
Got Time-CodeGotN-CharGotNULLCreditErrorRX_Err
RESET
Port ControllerPort Controller
RX_Err
‘1’ D Q
Flip Flop
R
Synchronization ExampleSynchronization Example
Asynchronous Reset
D Q
Flip Flop
R
D Q
Flip Flop
R
Controller’s Clock
Synchronizer
Controller Logic
Controller Logic
ReceiverReceiver
The SpaceWire PortThe SpaceWire PortArchitectureArchitecture
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
ClockClock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start /
Link Disable
Link Start /
Link Disable
State MachineState Machine
TX ClockTX
Clock
TransmitterTransmitter
FIFOFIFORX_CLOCKRX_CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Shift Register
Shift Register
LogicLogic
Port Transmitter“The Factory”
Port Transmitter“The Factory”
ControllerController
DoutDout
SoutSout
SpaceWire Character
TX Clock
DS Encoder
DS Encoder
TX DATA
Control Signals
LogicLogic LogicLogic
ReceiverReceiver
The SpaceWire PortThe SpaceWire PortArchitectureArchitecture
Port Controller
Port Controller
DinDin
SinSin
DoutDout
SoutSout
ClockClock
ResetReset
RX DATA / ControlRX DATA / Control
TX DATA / ControlTX DATA / Control
Link Start /
Link Disable
Link Start /
Link Disable
State MachineState Machine
TX ClockTX
Clock
TransmitterTransmitter
FIFOFIFORX_CLOCKRX_CLOCK
FIFOFIFO
WriteWrite
ReadyReady
ReadyReady
ReadRead
ReadRead
ReadyReady
ReadyReady
WriteWrite
Port ReceiverPort Receiver
Shift Register
Shift Register
Sequence Detector + Data Extraction
Sequence Detector + Data Extraction
MEM
Error Reporting
RX_DATA to FIFO
RX Clock RecoveryRX Clock Recovery
DinDin
SinSin
Rx Clock
DinDin
RX Clock RecoveryRX Clock Recovery
D
SRX_CLOCK
Version I – XOR GateVersion I – XOR Gate
D
S
RX_CLOCK
RX Clock RecoveryRX Clock Recovery
S
RX_CLOCK
Version II - Quad Data Rate Flip FlopVersion II - Quad Data Rate Flip Flop
D
S
D Q RX_CLOCK
D
RX Clock RecoveryRX Clock Recovery
Version III – Three DDR Flip Flops & XOR GateVersion III – Three DDR Flip Flops & XOR Gate
S
RX_CLOCK
D
RX Clock RecoveryRX Clock RecoveryVersion III – Three DDR Flip Flops & XOR GateVersion III – Three DDR Flip Flops & XOR Gate
D
D Q
DDR FF
S
D Q
DDR FF
RX_CLOCK
D Q
DDR FF
betterRX_CLOCK
Project MilestonesProject Milestones
• 8-14/1/08 – Assimilation of FIFOs into Port’s architecture.
• 15-21/1/08 – Checking feasibility for 200 MHz work frequency (using
DCM module).
• 22/1–11/2/08 – Testing & Stabilization of Port’s final design.
• 12/2-25/2/08- Gathering information about routing with SpaceWire.
• 8-14/1/08 – Assimilation of FIFOs into Port’s architecture.
• 15-21/1/08 – Checking feasibility for 200 MHz work frequency (using
DCM module).
• 22/1–11/2/08 – Testing & Stabilization of Port’s final design.
• 12/2-25/2/08- Gathering information about routing with SpaceWire.
Semester Goal – Port Completion
ReferencesReferences
• ECSS-E-50-12A - 24 January 2003• ECSS-E-50-12A - 24 January 2003