Jack Erickson and Mark WarrenCadence Design Systems, Inc.IEDECMarch 4, 2013

Modern System-on-Chip Challenges Require New Skills in Electronic Engineering Graduates

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The design productivity gap

Design Productivity (20-25% CAGR)

Gates / cm2 Moore’s Law (59% CAGR)

0.35 μm 0.25μm 0.18μm 0.15μm 0.13μm 0.09 μm 0.065μm 0.045μm 0.032μm

Source: Semico Research Corp.

DesignGAP

Pro

du

ctiv

ity

/ Co

mp

lexi

ty

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One solution: more IP blocks

Source: IBS, Inc.

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Another solution: more engineers per project

Source: IBS, Inc.

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Abstraction must be raised to close the gap!Why hasn’t it happened yet?

10000

1000

100

10

1

20102000199019801970's

0.5 device~500K-1M gates

65nm device~50M-100M gates

Des

ign

Pro

duct

ivity

(ga

tes/

per)

RTL(Logic Synthesis)

Gates(Schematic

Capture)

Switches(SPICE)

System-Level(High LevelSynthesis)

GAP

Abstraction delivers designs more quickly, with less effort

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Cadence’s approach

Synthesize and verify entire design in IEEE SystemC with transaction-level models (TLM)

Embedded RTL Compiler synthesis and connected design, verification, and implementation to ensure closure

Extend metric-driven verification methodology to start at TLM

ECOAnytime

Incisive Metric-Driven Verification

SystemC

C-to-Silicon Compiler

SoC FPGA

RTL

Deliver the next quantum leap in productivity

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• SystemC is now an IEEE standard• Modern HLS supports the full datapath-control spectrum

Challenges in moving to higher-abstraction design and verification

Robust Design Support

• Embedded logic synthesis guides some HLS tools• Still work to do – physical, flow development, etc.

Quality of Results

• Multi-level metric-driven verification methodology• Adoption just starting – seeing good returns

Verification Methodology

• Rare combination of skills today• Need to develop new breed of engineerSkills

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New combination of skills required

Block Initial design

Refined design

Gain

ECC 17.637 mm2 1.035 mm2 17 X

Encoder 0.160 mm2 0.065 mm2 2.46 X

Decoder 17.477 mm2 0.970 mm2 18 X

SystemC Constraints

Hardware architecture designHardware micro-architecture for

QoRC++SystemCHLS tool operationRTL synthesis optimization

conceptsSource: ITRI, “Building a NAND flash controller with high-level synthesis”

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Difficult for engineers to find time for training in the commercial sector…

Source: IBS, Inc.

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Courses and curricula available today

11 © 2013 Cadence Design Systems, Inc. All rights reserved.

Courses and curricula available today

12 © 2013 Cadence Design Systems, Inc. All rights reserved.

Courses and curricula available today

13 © 2013 Cadence Design Systems, Inc. All rights reserved.

Resources availableEnabling HLS course development

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