High Current Density and High Power Density Operation of Ultra High Speed InP DHBTs

Mattias Dahlström1, Zach Griffith,

Young-Min Kim2, Mark J.W. RodwellDepartment of ECE

University of California, Santa Barbara, USA

mattias@ece.ucsb.edu 805-893-8044, 805-893-3262 fax

(1) Now with IBM Microelectronics, Essex Junction, VT(2) Now with Sandia National Labs, NM

Overview

• Fast devices and circuits need high current!– Current limited by

• Kirk current threshold

• Device heating

– Thermal resistance Device heating

• Design of low thermal resistance HBT

• High Current Devices with state of the art RF performance

The need for high current density

0

5

10

15

20

25

30

35

1010 1011 1012

Gai

ns (

dB)

Frequency (Hz)

ft = 370 GHz

fmax

= 459 GHzU

H21

MAG/MSG

Ajbe

= 0.6 x 7 um2

Ic = 35 mA

Jc = 8.3 mA/um2, V

cb= 0.35 V

bccexbcicjeiece

Bcb

bccexbcjec

Bcb

CRRCACAJqA

Tnk

f

CRRCCqI

Tnk

f

,,2

1

2

1

Scaling laws:Single HBT: f

-80

-70

-60

-50

-40

-30

-20

-10

0

50 55 60 65 70 75

Out

put P

ower

(d

Bm

)

frequency (GHz)

-80

-60

-40

-20

0

59.34 59.36 59.38 59.40 59.42

dB

m

GHz

divide by 2

Je=6.9 mA/m2

Output spectrum @ 59.35 GHz, fclk=118.70 GHz

. ...and

, , , , logiclogic

logiclogic

f

c

bb

c

ex

c

je

c

cb

IV

R

IV

RV

I

CV

I

C

Minimize capacitance charging times! Increase current density

Digital circuitKey performance parameters:

Je=8 mA/m2

0

20

40

60

80

100InPInAsInGaAsInAlAsInGaPGaAsSiSiNSiOpolyimid

(W

/Km

)

Material

InP

InAs

InGaAsInAlAs

InGaP

GaAs

Si (168)

SiN SiO polyimid

at 300 K

Thermal conductivity of common materials

Ternaries lattice matched to InP

HBT: Where is the heat generated?

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

50 100 150 200 250 300 350

E (

eV

)

Position (A)

Ec

EvEmitter

Collector

Base

InGaAs

InGaAs

InGaAs

InP

InP

InGaAlAs

Vbe = 0.95 V, Vce = 1.3 V

Power generation: JE x VCE=6 x 1.5 V=9 mW/m2

In the intrinsic collector

HBT: heat transport

Main heat transport is through the subcollector to the substrateUp to 30 % heat transport up through the emitter contact

Thermal resistance of materials in collector and subcollector critical

How to design a low thermal resistance HBT

A five step process

Identify high thermal resistance materials change them low thermal resistance materials Very simple!

SHBT: InGaAs collector

Design of low thermal resistance HBT:Initial design: InGaAs collector

SHBT: InGaAs collector, InP emitter

Design of low thermal resistance HBT:Emitter: InAlAsInP

DHBT: InGaAs/InP collector

Design of low thermal resistance HBT:InGaAs collector InP collector with InGaAlAs grade

DHBT: InGaAs/InP collector, InGaAs/InP subcollector

Design of low thermal resistance HBT:InGaAs subcollector InGaAs/InP composite subcollector

DHBT: InGaAs/InP collector, thin InGaAs/InP subcollector

Design of low thermal resistance HBT:Thick InGaAs in subcollector thin InGaAs in subcollector

Metamorphic-DHBT: InGaAs/InP collector, InGaAs/InP subcollector

Design of low thermal resistance Metamorphic HBT:InAlAs,InAlP, InGaAs buffersInP buffer

Young-Min Kim

CfixedIc

CE

BE

CfixedIc

CE

BEJA

CECJACECE

BEfixedIcBE

IV

V

IdV

dV

VIVdV

dP

dP

dT

dT

dVV

11

Experimental Measurement of Temperature Rise

Temperature rise can be calculated by measuring IC, VCE and VBE

BEV

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98

I c (A

)

Vbe

(V)

Meta run 11 (BCB)

E05B05

V3.1ceV

cI

V5.1ceV

No thermal instability as long as slope<∞each VBE gives a unique IC

Thermoelectric feedback coefficient (data from W. Liu)

0.0006

0.0008

0.001

0.0012

0.0014

0.0016

0.0018

0.002

0.0022

0.001 0.01 0.1 1 10

(V

/K)

Je (mA/m2)

Thermoelectric feedback coefficient from Liu et al.

Thermoelectric feedback coefficient for AlGaAs/GaAs HBTs 4 % smallerNot a large influence from material or structure variations

W. Liu: “Thermal Coupling in 2-Finger Heterojunction Bipolar Transistors”, IEEE Transactions on Electron Devices, Vol 42 No6, June 1995W. Liu: H-F. Chau, E. Beam, "Thermal properties and Thermal Instabilities of InP-Based Heterojunction Bipolar Transistors”, IEEE Transactions on Electron Devices, Vol 43 No3, March 1996

Compared to previous UCSB mesa HBT results:

• Thinner InP collector—decrease c

• Collector doping increased—increase JKirk

• Thinner InGaAs in subcollector—remove heat

• Thicker InP subcollector—decrease Rc,sheet

High f DHBT Layer Structure and Band DiagramVbe = 0.75 V, Vce = 1.3 V

Emitter

CollectorBase

InGaAs 3E19 Si 400 Å

InP 3E19 Si 800 Å

InP 8E17 Si 100 Å

InP 3E17 Si 300 Å

InGaAs 8E19 5E19 C 300 Å

Setback 3E16 Si 200 Å

InP 3E18 Si 30 Å

InP 3E16 Si 1030 Å

SI-InP substrate

Grade 3E16 Si 240 Å

InP 1.5E19 Si 500 Å

InGaAs 2E19 Si 125 Å

InP 3E19 Si 3000 Å

Thermal resistance results: lattice matched

0

0.5

1

1.5

2

2.5

3

3.5

4

05

10

15

20

25

30

10 15 20 25 30

25 nm InGaAs, polymimide Rth12.5 nm InGaAs, polymimide Rth12.5 nm InGaAs, BCB Rthnew

25 nm InGaAs, polymimide 12.5 nm InGaAs, polymimide 12.5 nm InGaAs, BCB

Th

erm

al r

esis

tanc

e (K

/mW

)

Te

mp

eratu

re rise (K

)

Base-Collector Area (m2)

Measured thermal resistances for lattice matched HBTs. Ic= 5 mA, Vce=1.5 V, P=7.5 mW

25 nm InGaAs

12.5 nm InGaAs

Device Buffer (m)

Tc (nm) Tsc InGaAs (nm)

Tsc InP (nm)

JA

K/mW

DHBT-M1 - 200 25 125 2.5

DHBT-19b - 150 12.5 300 1.8

DHBT-23 - 150 12.5 300 1.4

50 nm InGaAs 25 nm InGaAs: large improvement

Thermal resistance results: metamorphic

Measured thermal resistances for metamorphic HBTs. Ic= 5 mA, Vce=1.5 V, P=7.5 mW

25 nm InGaAsInP buffer

0

2

4

6

8

10

12

14

02

04

06

08

01

00

5 10 15 20 25 30 35

InAlP buffer, 25 nm InGaAs RthInP buffer, 25 nm InGaAs RthInP buffer, 12.5 nm InGaAs Rth

InAlP buffer, 25 nm InGaAsInP buffer, 25 nm InGaAsInP buffer, 12.5 nm InGaAs

Th

erm

al r

esis

tanc

e (K

/mW

)

Te

mp

eratu

re rise (K

)

Base-Collector Area (m2)

50 nm InGaAsInAlP buffer

InAlP InP buffer: large improvement50 nm InGaAs 25 nm InGaAs: small improvement

Device Buffer (m) Tc (nm) Tsc InGaAs (nm)

Tsc InP (nm)

JA

K/mW

M-HBT-1 InAlP 1.5 200 50 125 7.6

M-HBT-2 InP 1.5 200 50 125 3.3

M-HBT-11 InP 1.5 200 25 300 3.1

Device and circuit results

0

5

10

15

20

25

30

35

1010 1011 1012

Gai

ns (

dB)

Frequency (Hz)

ft = 370 GHz

fmax

= 459 GHzU

H21

MAG/MSG

Ajbe

= 0.6 x 7 um2

Ic = 35 mA

Jc = 8.3 mA/um2, V

cb= 0.35 V

Zach Griffith

Continuous operation at high current densities greater than peak rf performance (Je = 8 mA/m2)

0

2

4

6

8

10

12

14

0 0.5 1 1.5 2

J e (m

A/

m2 )

Vce

(V)

Ajbe

= 0.5 x 7 m2

Ib step

= 0.4 mA

Vcb

= 0 V

28 transistor static frequency divider @ fclk=118.7 GHz shownTo be reported, 150 GHz static divider using same Type 1 DHBT structure—chirped superlattice

Transistor operation at 13 mA/m2 150 nm InGaAs/InP collector

370 GHz ft at Jc>8 mA/m2

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0 50 100 150

Ou

tput

Sig

nal (

V)

time (ps)

-80

-70

-60

-50

-40

-30

-20

-10

0

50 55 60 65 70 75

Out

put P

ow

er (

dB

m)

frequency (GHz)

-80

-60

-40

-20

0

59.34 59.36 59.38 59.40 59.42

dB

m

GHz

divide by 2

Our Mesa DHBTs have Safe Operating AreaExtending beyond High-Speed Logic Bias Conditions

0

2

4

6

8

10

12

14

0 1 2 3 4 5 6 7 8

J e (m

A/

m2 )

Vce

(V)

Ajbe

=0.6 x 7 m2 Ib step

= 0.4 mA0.5 um X 0.7 um emitter junction0.5 um base contact width

~6.8 V low-currentBVCEO

0

2

4

6

8

10

12

0 1 2 3 4 5 6

device failure

18 mW/um2

design limit 10 mW/um 2

J max

(m

A/u

m2 )

Vce

(V)

8 m emitter metal length, ~0.6 m junction width

biased without failure (DC-IV)

No RF driftafter 3-hr burn-in ECL

bias points

Low-current breakdown is > 6 Volts

this has little bearing on circuit design

Safe operating area is > 10 mW/um2

these HBTs can be biased ....at ECL voltages

...while carrying the high current densities needed for high speed

0

2

4

6

8

10

12

14

0 0.5 1 1.5 2

J e (m

A/

m2 )

Vce

(V)

Ajbe

= 0.5 x 7 m2 Ib step

= 0.4 mA

Vcb

= 0 V

peak (f, f

max) bias

Conclusions

• DHBT design with InP subcollector very low thermal resistance

•Metamorphic DHBT with InP buffer low thermal resistance

•DHBT operation at Jc>13 mA/m2

•Optimal device and circuit performance at Jc up to 8 mA/m2

•HBT I-V operating area allows static frequency dividers operating at speeds over 150 GHz

Backup slides

HBT

Why is thermal management important?

• As J increases so does the power density. This will lead to an increase in the temperature.

TC JKirk Le

Å mAμm-2 μm

3000 1.0 81

2000 2.3 34

1500 4.1 19

1000 9.8 8.6

For VCE=1V PD=10.6mWμm-3

V=2V

80mA

For VCE=1V PD=98mWμm-3!!

Thermal Modeling of HBT (1)

• 3D Finite Element using Ansys 5.7• K (Thermal conductivity) depends temperature

• K depends on doping • For GaAs heavily doped GaAs 65% less than undoped GaAs

• Unknown for InP or InGaAs use GaAs dependency

n

T Tkk

300300

J.C.Brice in “Properties of Indium phosphide” eds S Adachi and J.Brice pubs INSPEC London p20-21S Adachi in “Properties of Latticed –Matched and strained Indium Gallium Arsenide” ed P Bhattacharya pubs INSPEC London p34-39“CRC Materials science and engineering handbook”, 2nd edition ,eds J.F Shackelford,A.Alexander, and J.S Park, pubs CRC press, Boca Raton, p270

Material K300 n K300(exp) Refs

InP 0.68 1.42 0.68-0.877 1

InGaAs 0.048 1.375 0.048-0.061 2

Au 3.17 - 3

Large uncertainty

in values

Validation of Model

0

5

10

15

20

25

30

35

40

-0.2 0 0.2 0.4 0.6 0.8 1 1.2

centerEdge

Tem

per

atu

re R

ise

(K)

Distance from substrate (m)

SC ES C B E E Metal

Caused by Low K

of InGaAs

Max T in Collector

Ave Tj (Base-Emitter) =26.20°CMeasured Tj=26°CGood agreement.

Advice Limit InGaAs Increase size of emitter arm

Ian Harrison

Analysis of 40,80,160 Gbit/s devices

• To obtain speed inprovements require to scale other device

parameters.Speed (Gbit/s) 40 80 160

Collector Thickness (Å) 3000 2000 1000

Base Sheet resistance () 750 700 700

Base contact resistance (-m2) 150 20 10

Base Thickness (Å) 400 300 250

Base Mesa width ( m) 3 1.6 0.4

Current Density (mA/m2) 1 2.3 9.8

Emitter. Junction Width ( m) 1 0.8 0.2

Emitter Parasitic resistivity (-m2) 50 20 5

Emitter Length ( m) 6 3.3 3.2

Predicted MS-DFF (GHz) 62 125 237

Ft (GHz) 170 260 500

Fmax (GHz) 170 440 1000

Tj (K) 7.5 14 28

TMax (K) 10 20 49

TMax (No Etch Stop layer) (K) 7.5 13 21

Conservative 1.5x bit rate

Reduction of parasitic CBC

Device parameters after Rodwell et al

When not switching values will double

V=0.3V

6mA

Ian Harrison

Mesa DHBT with 0.6 m emitter width, 0.5 m base contact width

Z. Griffith, M Dahlström

How we measure thermal resistance

Layout improvement: Emitter heat sinking

Emitter interconnect metal 2 μm to 7 μm~30 % of heat out through emitter Negligible increase in Cbe

Improved emitter heatsinking