hdth ktmt bang mophong logisim moi

I HC QUC GIA H NI TRNG I HC CNG NGH

KHOA CNG NGH THNG TIN

HNG DN THC HNH

KIN TRC MY TNH BNG M PHNG

TC GI PGS. TS. Nguyn nh Vit (ch bin) ThS. Lng Vit Nguyn KS. Nguyn Hoi Nam KS. Nguyn c Thin

H NI - 2010

------------------------------------------------------------------------------------------------------------------------------------ Gio trnh Hng dn thc hnh Kin trc my tnh, version-1.0 1

LI NI U


MC LC

GII THIU ................................................................................................ 8

BI 1 Hc s dng Logisim theo tr gip Help.................................. 9 1.1. Cc yu cu v ni dung chnh.................................................................................... 9 1.2. Ci t b m phng Logisim ..................................................................................... 9 1.3. Cc bc to mt mch logic s n gin .................................................................. 9 1.4. Bi tp (theo gio trnh Kin trc my tnh)................................................................ 9

BI 2 Hc s dng Logisim theo tr gip Help (tip) ...................... 11 2.1. Cc yu cu v ni dung chnh.................................................................................. 11 2.2. S dng th vin ca Logisim v thay i thuc tnh ca cc phn t logic............ 11 2.3. To v s dng cc mch con.................................................................................... 11 2.4. Tra cu theo cc menu............................................................................................... 11 2.5. Bi tp (theo gio trnh Kin trc my tnh).............................................................. 11

BI 3 Hc s dng Logisim theo tr gip Help (tip) ...................... 13 3.1. Cc yu cu v ni dung chnh.................................................................................. 13 3.2. To v s dng cc b dy ........................................................................................ 13 3.3. Phn tch cc mch t hp (Combinational circuits)................................................. 13 3.4. Bi tp (theo gio trnh Kin trc my tnh).............................................................. 13

BI 4 Hc s dng Logisim theo tr gip Help (tip) ...................... 15 4.1. Cc yu cu v ni dung chnh.................................................................................. 15 4.2. Cc thnh phn ca b nh........................................................................................ 15 4.3. Bi tp (theo gio trnh Kin trc my tnh).............................................................. 15

BI 5: Xy dng ALU-16bits .................................................................. 17 5.1. Cc yu cu v ni dung chnh.................................................................................. 17 5.2. Phn tch bi tan ...................................................................................................... 17 5.3. Xy dng ALU 1 bit .................................................................................................. 18 5.4. Xy dng ALU 8 bit .................................................................................................. 19 5.5. Xy dng ALU 16 bit hon chnh ............................................................................. 20 5.6. Bi tp (khng c trong gio trnh Kin trc my tnh) ............................................ 21


BI 6: Xy dng khi 16 thanh ghi........................................................ 22 6.1. Cc yu cu v ni dung chnh.................................................................................. 22 6.2. Phn tch bi tan ...................................................................................................... 22 6.3. Xy dng v m phng khi 16-Register.................................................................. 25

6.3.1 Xy dng khi 16-Register..............................................................................................25 6.3.2 M phng hot ng ca khi 16-Register......................................................................26

6.4. Bi tp (khng c trong gio trnh Kin trc my tnh) ............................................ 27

BI 7: Xy dng cc thnh phn cn li ca ng d liu.............. 28 7.1. Cc yu cu v ni dung chnh.................................................................................. 28 7.2. Xy dng v m phng s hot ng ca shifter ...................................................... 29

7.2.1 Phn tch ..........................................................................................................................29 7.2.2 Xy dng mch con shifter ..............................................................................................29 7.2.3 M phng hot ng ca shifter ......................................................................................31

7.3. Xy dng v m phng s hot ng ca cc thanh ghi cht A Latch v B Latch .. 31 7.3.1 Phn tch ..........................................................................................................................31 7.3.2 Xy dng thanh ghi cht..................................................................................................31 7.3.3 M phng hot ng ca thanh ghi cht (Latch Register) ..............................................32

7.4. Xy dng v m phng s hot ng ca AMUX.................................................... 32 7.5 Xy dng v m phng s hot ng ca MAR ........................................................ 32

7.5.1 Phn tch ..........................................................................................................................32 7.5.2 Xy dng thanh ghi MAR ...............................................................................................33 7.5.3 M phng hot ng ca MAR .......................................................................................33

7.6 Xy dng v m phng s hot ng ca MBR ........................................................ 34 7.6.1 Phn tch ..........................................................................................................................34 7.6.2 Xy dng thanh ghi MBR................................................................................................34 7.6.3 M phng hot ng ca MBR........................................................................................35

7.7. Bi tp........................................................................................................................ 36

BI 8: Xy dng Control Store, MIR v Micro Seq ca n v iu khin......................................................................................................... 37 8.1. Cc yu cu v ni dung chnh.................................................................................. 37 8.2. Xy dng v m phng s hot ng ca Control Store .......................................... 38

8.2.1 Phn tch ..........................................................................................................................38 8.2.2. Xy dng v np ni dung cho Control Store.................................................................38 8.2.3. M phng s hot ng ca Control Store .....................................................................44

8.2. Xy dng v m phng s hot ng ca MIR......................................................... 44 8.2.1 Phn tch ..........................................................................................................................44 8.2.2 Xy dng thanh ghi MIR .................................................................................................44 8.2.3 M phng hot ng ca thanh ghi MIR.........................................................................45


8.3. Xy dng v m phng s hot ng ca Micro Seq ............................................... 45 8.3.1 Phn tch ..........................................................................................................................45 8.3.2 Xy dng mch con Micro Seq .......................................................................................45 8.3.3 M phng hot ng ca Micro Seq................................................................................46

BI 9: Xy dng cc thnh phn cn li ca b iu khin ............... 47 9.1. Cc yu cu v ni dung chnh.................................................................................. 47 9.2. Xy dng v m phng hot ng ca thanh ghi MPC ............................................ 47

9.2.1 Phn tch ..........................................................................................................................47 9.2.2 Xy dng thanh ghi MPC ................................................................................................47 9.2.3 M phng hot ng ca thanh ghi MPC........................................................................48

9.3. Xy dng v m phng hot ng ca n v Increment ......................................... 48 9.3.1 Phn tch ..........................................................................................................................48 9.3.2 Xy dng mch con Increment ........................................................................................48 9.3.3 M phng hot ng ca Increment ................................................................................49

9.4. Xy dng v m phng hot ng ca n v Mmux............................................... 49 9.5. Xy dng v m phng hot ng ca decoder ........................................................ 49

9.5.1 Phn tch ..........................................................................................................................49 9.5.2 Xy dng mch con lm A, B decoder v m phng s hot ng ca n.....................49 9.5.3 Xy dng mch con lm C decoder v m phng s hot ng ca n..........................50

9.6. Xy dng v m phng hot ng ca Clock ........................................................... 51 9.6.1 Phn tch ..........................................................................................................................51 9.6.2 Xy dng mch con lm n v Clock ............................................................................52 9.6.3 M phng s hot ng ca Clock ..................................................................................53

BI 10: Xy dng vi kin trc y .................................................... 54 10.1. Cc yu cu v ni dung chnh................................................................................ 54 10.2. Lp ghp vi kin trc y ................................................................................... 54 10.3. B sung b nh chnh v lp ghp vi vi kin trc................................................. 55 10.4. Kim tra h thng my tnh ..................................................................................... 56

PH LC A: HNG DN S DNG LOGISIM ................................... 57 1. CH DN CHO NGI MI S DNG .................................................................. 58

1.1 Bc 0: T nh hng chnh bn thn bn .......................................................................59 1.2 Bc 1: Thm cc cng ......................................................................................................60 1.3 Bc 2: Thm dy ni ........................................................................................................62 1.4 Bc 3: Chn text ...............................................................................................................63 1.5 Bc 4: Kim tra mch.......................................................................................................64

2. TH VIN V CC THUC TNH.......................................................................... 65 2.1 Explorer pane......................................................................................................................66 2.2 Bng thuc tnh...................................................................................................................67


2.3 Thuc tnh ca cng c .......................................................................................................68 3. CC MCH CON........................................................................................................ 70

3.1 To mi cc mch...............................................................................................................70 3.2 S dng mch con...............................................................................................................71 3.3 Sa li cc mch con ..........................................................................................................73 3.4 Th vin Logisim................................................................................................................74

4. DY.............................................................................................................................. 75 4.1 To cc b...........................................................................................................................75 4.2 Dng c r nhnh................................................................................................................76 4. 3 Mu ca dy.......................................................................................................................77

5. PHN TCH TNG HP............................................................................................ 79 5.1 Cch m bng phn tch tng hp ......................................................................................79 5.2 Sa i bng chn l............................................................................................................80 5.3 To cc biu thc ................................................................................................................82 5.4 To mch.............................................................................................................................84

6. GII THIU CC MENU........................................................................................... 84 6.1 Menu File............................................................................................................................84 6.2 Menu Edit ...........................................................................................................................85 6.3 Menu Project.......................................................................................................................86 6.4 Menu Simulate....................................................................................................................87 6.5 Menu Window ....................................................................................................................88 6.6 Menu Help ..........................................................................................................................88

7. CC THNH PHN CA B NH ......................................................................... 88 7.1 Truy cp b nh ..................................................................................................................89 7.2 Pop-up menus and files.......................................................................................................89 7.3 Hex editor ...........................................................................................................................90

8. LOGGING.................................................................................................................... 91 8.1 Th la chn (the selection tab)..........................................................................................92 8.2 Th table .............................................................................................................................93 8.3 Th tp ................................................................................................................................94

9. APPLICATION PREFERENCES................................................................................ 95 9.1 Th Template ......................................................................................................................96 9.2 Th International.................................................................................................................96 9.3 Th Experimental................................................................................................................98 9.4 Ty chn Command-line ....................................................................................................99

10. PROJECT OPTION.................................................................................................. 100 10.1 Th Canvas .....................................................................................................................101 10.2 Th Simulation................................................................................................................103 10.3 Th Toolbar.....................................................................................................................104 10.4 Th Mouse ......................................................................................................................105

11. S TRUYN GI TR ............................................................................................ 106 11.1 S tr ca cng ...............................................................................................................106 11.2 Li dao ng ...................................................................................................................107 11.3 Hn ch ...........................................................................................................................108


PH LC B: P N MT S BI TP .............................................. 110 Bi s 5 ........................................................................................................................... 110


GII THIU


BI 1 Hc s dng Logisim theo tr gip Help

1.1. Cc yu cu v ni dung chnh Bit cch ci t v cho chy chng trnh m phng Bit cch s dng tr gip (Help) ca logisim Bit cc bc to mt mch logic s n gin Bit cch lu gi (save) cc mch in to ra vo file v m (open)

1.2. Ci t b m phng Logisim C th download cc bn logisim cho Windows, Linux, MacOS ti a ch sau:

http://sourceforge.net/projects/circuit/

Bn cho Windows ch gm c 1 file: logisim-win-2.3.5.exe (3.5 MB).

Bn cho MacOS l file: logisim-macosx-2.3.5.tar.gz.

Bn cho Linux (v nhiu OS khc) l: logisim-2.3.5.jar.

Chy logisim trong mi trng Windows: Nu my tnh ci t java, th c th chy logisim ngay, nh chy cc file chng trnh kh thi bnh thng khc. Nu cha, th phi ci java ri mi chy c logisim.

Chy logisim trong mi trng linux (ubuntu): Cn phi ci t java trc mi c th chy c logisim. Chng ti ci sun-java6-jre trong Ubuntu 10.04 v Ubuntu Remix v khng gp tr ngi no. C th dng Synaptic Package Manger tm v ci bn java ny.

Chy logisim nh sau: java jar logisim-2.3.5.jar [Enter]

1.3. Cc bc to mt mch logic s n gin Thc hin cc bc theo Help ca logisim (Help \ Tutorial \ Beginners Tutorial). Trong Bi thc hnh s 1, sinh vin cn c v lm theo 5 bc (step 0 step 4) ca mc Beginners Tutorial.

1.4. Bi tp (theo gio trnh Kin trc my tnh) Ch khi lm cc bi tp ca chng ny:

u ra ca 1 cng c th ni vi u vo ca 1 cng khc. i vi cc u vo/ra khng ni vi cc u vo/ra ca cc cng khc, mi u vo cn ni vi mt phn t input v mi u ra cn ni vi phn t output.


th li chc nng, s dng cng c poke tool tr vo cc phn t input v kch nt chut bn tri o gi tr ca input, ng thi quan st gi tr ca phn t output.

Sau khi to v th cc mch logic, cn save vo b nh ngoi ( a cng, a USB...), sau th open xem li. Tn file lu mch in theo cc hnh v trong gio trnh nn t theo tn hnh v cho d nh. Th d, vi mch in trn hnh 3-02, tn file nn t l hinh3-02.circ, hoc figure3-02.circ.

Bi tp:

1. M phng s hat ng ca cc cng logic n gin nht trn hnh 3-02.

Hnh 3-02 K hiu v hnh trng chc nng ca 5 cng c bn

2. To v m phng hat ng ca cc mch logic s nh trn Hnh 3-03, kim tra s tng ng ca chng.

Hnh 3-03 Cc mch logic c chc nng tng ng

3. To v m phng hat ng ca cc mch logic s nh trn Hnh 3-06.

Hnh 3-06 Bng chn l ca hm XOR v cc mch in thc hin hm ny


BI 2 Hc s dng Logisim theo tr gip Help (tip)

2.1. Cc yu cu v ni dung chnh Bit s dng th vin ca logisim Bit b sung cc mch con (subcircuit) m mnh to ra vo th vin To v m phng mt s mch in c trong gio trnh Kin trc my tnh. 2.2. S dng th vin ca Logisim v thay i thuc tnh ca cc phn t logic Thc hnh trn my theo Help ca logisim, xem mc Libraries and Attributes.

2.3. To v s dng cc mch con Thc hnh trn my theo Help ca logisim, xem mc Subcircuits.

2.4. Tra cu theo cc menu Thc hnh trn my theo Help ca logisim, xem mc Menu Reference.

2.5. Bi tp (theo gio trnh Kin trc my tnh) Ch :

Cc mch logic s sau y c trong th vin ca logisim, nhng sinh vin vn cn to ra chng bng cc phn t logic c bn hiu su v s hot ng ca chng.

Sinh vin nn ly t th vin mt phn t c chc nng tng t chc nng ca mch logic s m mnh va to ra so snh chc nng ca chng.

Sau ny, khi xy dng Micro Architecture (hnh 4-07, hnh 4-09), chng ta s s dng cc phn t c trong th vin.


Bi tp:

1. To v m phng hat ng ca multiplexer v demultiplexer trn Hnh 3-07.

Hnh 3-07 B dn knh v b phn knh

2. To v m phng hat ng ca b decoder 3 to 8 trn Hnh 3-08.

Hnh 3-08 Mch gii m 3 to 8

3. To v m phng hat ng ca b so snh 4 bit trn Hnh 3-09.

Hnh 3-09 B so snh 4 bit



3.1. Cc yu cu v ni dung chnh Bit to v s dng cc b dy (wire bundles) Bit phn tch, to v m phng cc mch t hp (combinational circuit) To v m phng c cc mch t c trong gio trnh Kin trc my tnh. 3.2. To v s dng cc b dy Thc hnh trn my theo Help ca logisim, xem mc Wire bundles.

3.3. Phn tch cc mch t hp (Combinational circuits) Thc hnh trn my theo Help ca logisim, xem mc Combinational analysis.

3.4. Bi tp (theo gio trnh Kin trc my tnh) Ch :

Mt s mch logic s sau y c trong th vin ca logisim, nhng sinh vin vn cn to ra chng bng cc phn t logic c bn hiu su v s hot ng ca chng.



Bi tp:

1. To v m phng hat ng ca b dch (shifter) trn Hnh 3-11. Thc tp s dng cc phn t Shifter v Shift Register c trong th vin ca logisim (trong cc nhm Arithmetic v Memory).

Hnh 3-11 B dch 1 bit sang tri/phi


2. To v m phng hat ng ca cc b cng (Haft-Adder v Full-Adder) trn Hnh 3-12. Thc tp s dng phn t Adder c trong th vin ca logisim (trong nhm Arithmetic).

Hnh 3-12 B cng

3. To v m phng hat ng ca b s hc l logic trn Hnh 3-13 (1-bit ALU). Lu (save) vo file ALU-1bit.circ s dng cho bi tp sau.

Hnh 3-13 B S hc v Logic (ALU) 1 bit

4. To v m phng hat ng ca mt ALU 8 bit t cc mch con l ALU 1 bit nh trn hnh 3-14 (s dng file ALU-1bit.circ).

Hnh 3-14 ALU 8-bit c to bi 8 mnh ALU 1-bit



4.1. Cc yu cu v ni dung chnh Bit c kh nng m phng b nh ca logisim. Bit to v m phng s hot ng ca cc phn t nh c bn. Bit s dng cc phn t nh c trong th vin ca logisim. 4.2. Cc thnh phn ca b nh Thc hnh trn my theo Help ca logisim, xem mc Memory.

Trong gi thc hnh c gio vin hng dn, nn tp trung thc hnh s dng cc thnh phn b nh sau:

D Flip-Flop S-R Flip-Flop Register 4.3. Bi tp (theo gio trnh Kin trc my tnh) Ch :

Mt s mch logic s sau y c trong th vin ca logisim, nhng sinh vin vn cn to ra chng bng cc phn t logic c bn hiu su v s hot ng ca chng.



Bi tp:

1. To v m phng s hot ng ca Thanh ghi cht n gin nht - thanh ghi cht RS, theo Hnh 3-16; sau lp li vic ny nhng s dng cc phn t NAND thay cho cc phn t NOR.

Hnh 3-16 a/ Thanh ghi cht dng cng NOR trng thi 0; b/ Thanh ghi cht dng cng NOR trng thi 1


2. To v m phng s hot ng ca Thanh ghi cht RS hot ng theo nhp xung ng h theo Hnh 3-17. Ch th tn hiu ng h (clock) theo 2 cch: 1/ s dng phn t input v dng phn t poke tool thay i gi tr ca input; 2/ s dng n v to tn hiu clock thuc nhm Base trong th vin ca logisim.

Hnh 3-17 Thanh ghi cht RS hot ng theo nhp xung ng h

3. To v m phng s hot ng ca Thanh ghi cht D hot ng theo nhp xung ng h (Hnh 3-18).

Hnh 3-18 Thanh ghi cht D hot ng theo nhp xung ng h

4. To v m phng s hot ng ca Phn t nh 1 bit ca b nh RAM tnh (SRAM) nh trn Hnh 3-19.

Hnh 3-19 Mch in ca mt phn t nh RAM tnh 1 bit Sij

Ch :

- S dng phn t Controlled Buffer thuc nhm Gates trong th vin lm b m 3 trng thi c u ra ni vi Dout.

- S dng phn t Buffer thuc nhm Gates trong th vin lm b m c u vo ni vi Din.

5. T c cc mc Logging; Application Referenes v Projection trong Help ca logisim.


BI 5: Xy dng ALU-16bits

5.1. Cc yu cu v ni dung chnh Xy dng v m phng s hot ng ca n v ALU ca vi kin trc c m t trn hnh 4-09. ALU ny c m t k ti mc 4.1.4 n v S hc-Logic v B dch v c minh ho trn hnh 4-04.

Hnh 4-04 a/ K hiu mt ALU; b/ K hiu mt Shifter

ALU ny thc hin mt trong 4 php tnh trn tan hng 16 bit, theo m php tan cha trong trng ALU (gm 2 bit F0 v F1) ca thanh ghi MIR cha vi ch th ang thi hnh:

ALU (= F0 F1) = 00: Cng 2 tan hng 16 bits 2 u vo, s nh a vo (carry-in) bng 0, s nh a ra c s dng to thnh cc tn hiu trng thi N v Z.

ALU (= F0 F1) = 01: AND 2 tan hng 16 bits 2 u vo. ALU (= F0 F1) = 10: Cho tan hng u vo bn tri (u vo A) i ra u ra,

khng thay i; cc bt trng thi N v Z c thit lp ph thuc vo kt qu u ra.

ALU (= F0 F1) = 11: o tan hng u vo bn tri (u vo A) v a ra u ra. 5.2. Phn tch bi tan ALU ny thc hin cc chc nng khng hon ton ging vi ALU hc v c

m t trn hnh 3-13. Tuy nhin, s khc nhau l khng nhiu. Chng ta ch phi to ra mt mch in thc s mi sinh ra tn hiu trng thi N v Z, theo nguyn tc sau:

N - ch bo rng kt qu ra ca ALU l m (Negative). Thc cht, bit N ch l copy ca bit c bc cao nht ca kt qu a ra.

Z - ch bo rng kt qu ra ca ALU bng khng (Zero). Thc cht, bit Z l NOR ca tt c cc bit ca kt qu a ra.

Khi xy dng ALU-16bits: Carry-in cho b cng 2 bit bc 0 c cho bng 0.


Carry-out ca b cng 2 bit bc cao nht (15) khng cn quan tm ( mch in v vic phn tch n khng qu phc tp).

vic xy dng mch in theo kiu m-un ha, chng ta s xy dng mch ALU 1 bit trc, lu vo file ALU-1bit.circ; sau s dng n xy dng ALU-8bits; cui cng xy dng ALU-16bits theo yu cu t 2 ALU 8 bit v mt s phn t mch in khc, th d mch to cc tn hiu trng thi N v Z.

Ch : Chng ta c th xy dng 1 ALU-16bits t 16 ALU-1bit, thm ch t cc phn t logic c bn. Tuy nhin, nu lm nh vy s khng th nhn thy ton b mch in trn mn hnh.

5.3. Xy dng ALU 1 bit Chy logisim; Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh,

hi tn m ta mun t cho mch in. Hy t tn l ALU-1bit, khng cn nh vo tn m rng lun c t mc nh l .circ. Trong ca s con gc trn bn tri, ngoi tn main, logisim hin tn mch con (subcircuit) m chng ta va to ra, l ALU-1bit.

Lu (save) mch in m chng ta to ra: vo menu File \ Save | Save As. Khi logisim hi tn m chng ta mun t, hy t tn l: Micro-Architecture-SVxx.circ. Trong , SVxx l m s sinh vin v .circ l tn m rng (mc nh). Trong thi gian thc hnh, hoc khi kt thc thc hnh, nn thng xuyn save.

Xy dng ALU 1 bit nh hnh di y. Ch :

1. Mch con ny s c chng ta s dng xy dng ALU-8bits.

2. Cc phn t input/output ca mch con nm hng no (North, South, East, West) ca mch in ny, th khi chng ta s dng mch con ny nh mt phn t ca th vin, cc u (chn) input/ouput ca phn t s c cng hng (North, South, East, West).

Kim tra s thc hin 4 chc nng ca ALU bng cch dng phn t poke tool thit lp cc gi tr khc nhau ca cc u vo: F0, F1, A, B v Carry-in; ng thi quan st gi tr trn cc u ra: Output v Carry-Out.


5.4. Xy dng ALU 8 bit Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta

mun t cho mch in. Hy t tn l ALU-8bits. Trong ca s con gc trn bn tri, ngoi tn main v ALU-1bit, logisim hin tn mch con (subcircuit) m chng ta va to ra, l ALU-8bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con ALU-8bits s c lu cng vi Micro-Architecture-SVxx.circ.

Xy dng ALU-8bits nh hnh di y. Ch : Hy s dng cc phn t ALU-1bit do chng ta to ra. Vic ny khng khc g so

vi vic s dng cc phn t c sn trong th vin ca logisim.

Cc phn t input c ghi nhn A (left input), B right input v phn t output c ghi nhn Output l 8 bits.

Mi phn t input/output 8 bits ni trn ni vi 1 u ca 1 b dy (gm 8 dy n), u kia ca b dy ni vi u 8 bits ca phn t Splitter thuc nhm Base c trong th vin ca logisim. Phn t Splitter ny c 8 u ra mi u ra l 1 dy in truyn 1 bit. (Chng ta c th thay i s u ra, tc l gp mt s dy vo 1 b dy hnh v khi qu ri mt).



5.5. Xy dng ALU 16 bit hon chnh Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta

mun t cho mch in. Hy t tn l ALU-16bits. Trong ca s con gc trn bn tri, ngoi tn main, ALU-1bit, ALU-8bits, logisim hin tn mch con (subcircuit) m chng ta va to ra, l ALU-16bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con ALU-16bits s c lu cng vi Micro-Architecture-SVxx.circ.

Xy dng ALU-16bits nh hnh di y. Ch : Hy s dng cc phn t ALU-8bits do chng ta to ra. Cc phn t input c ghi nhn To A-bus, To B-bus v phn t output c ghi

nhn ALU output l 16 bits.

u vo Carry_in ca ALU-8bits bn phi c ni vi phn t Constant thuc nhm Gates trong th vin ca logisim. Chng ta cn t thuc tnh cho phn t ny bng 0.



5.6. Bi tp (khng c trong gio trnh Kin trc my tnh) Hy s dng cc cc phn t Hex Digit Display v Splitter c c di dng s Hexa cc gi tr a vo ALU v kt qu nhn c u ra ALU.


BI 6: Xy dng khi 16 thanh ghi

6.1. Cc yu cu v ni dung chnh Xy dng v m phng s hot ng ca khi cc thanh ghi 16 Registers ca vi

kin trc c m t trn hnh 4-09 (trong gio trnh Kin trc my tnh, hoc c th xem trong Bi 8 Xy dng Control Store, MIR v Micro Seq ca n v iu khin). Khi ny gm 16 thanh ghi, mi thanh ghi c kch thc16 bits, th t cc thanh ghi t 0..15 l: PC, AC, SP, IR, TIR, 0, +1, -1, AMASK, SMASK, A, B, C, D, E, F.

Mi mt trong 16 thanh ghi ni trn c th c iu khin nhn d liu t Bus-C bng tn hiu t trng ENC trong thanh ghi MIR, vic nhn d liu t Bus-C ch c th xy ra trong chu k con th 4 ca tn hiu ng h. Vic chn 1 trong 16 thanh ghi thc hin bng C decoder, cn u vo 4 bit ca C decoder ni vi trng C ca thanh ghi MIR.

Mi mt trong 16 thanh ghi ni trn c th c iu khin ni dung ca n ra Bus-A, hoc Bus-B, hoc ng thi ra c Bus-A v Bus-B. Vic chn 1 trong 16 thanh ghi d liu ra bus A c thc hin bng A decoder. Vic chn 1 trong 16 thanh ghi d liu ra bus B c thc hin bng B decoder.

6.2. Phn tch bi tan Cch to khi cc thanh ghi ny ny c m t ti mc 4.1.1 Thanh ghi v mc 4.1.2 Bus v c minh ho trn hnh 4-02. Ch rng hnh 4-02a ny m t cc to 1 thanh ghi kch thc 8 bits t 8 thanh ghi 1 bit; hnh 4-02b m t cc bus v cc tn hiu ni vi thanh ghi 16 bits.


Hnh 4-02 a/ Thanh ghi 8 bit ni vi mt bus vo (input bus) v mt bus ra (output bus). b/ K hiu ca mt thanh ghi 16 bit vi mt bus vo v hai bus ra

Trong bi thc hnh ny chng ta s s dng phn t register thuc nhm Memory trong th vin ca logisim. Mt s thuc tnh ca phn t ny c th thay i c thng qua ca s Attribute Table gc di bn tri ca s chnh ca logisim. ngha ca cc thuc tnh nh sau:

Data bits: t 1 n 32, chng ta chn bng 16. Trigger: tn hiu ng h kch hot phn t nh (nhn input hoc a ni dung ra

output) (u vo c ghi hnh u mi tn), c th chn 1 trong 4 tn hiu:

Rising Edge: phn t nh b kch hot bng sn ln (dng) ca xung kch. Falling Edge: phn t nh b kch hot bng sn xung (m) ca xung kch. High Level: phn t nh b kch hot bng mc cao ca xung kch. Low Level: phn t nh b kch hot bng mc thp ca xung kch. Chng ta chn Rising Edge, v chng ta mun cc thanh ghi c kch hot ngay sn ln (u) ca xung ng h.

Label: nhn m chng ta mun t cho phn t nh. Chng ta c th t nhn khc nhau cho cc thanh ghi khc nhau, th d: thanh ghi c u en ni vi u ra 0 ca decoder nn gn nhn l PC, tng t: 1: AC, 2: SP, ...


Label Font: font ch v c ch ca nhn; Chng ta cn chn sao cho p, ch khng ln cc nt ca hnh v.

Cc u vo/ra ca phn t nh:

D (Data bits): u vo d liu (1..32 bits). Q (u ra d liu): c rng (s bit) bng u vo D. ^: u vo (1 bit) ca tn hiu ng h. en (Enable): tn hiu m chip cha phn t nh, tng t tn hiu CS (Chip Select)

hoc CE (Chip Enable) m chng ta gp khi phn tch mt s mch in trong Chng 3 Mc logic s.

0: u vo tn hiu xa (t gi tr 0) ni dung phn t nh.

Sau khi bit c cc thuc tnh v cc u vo/ra ca phn t nh Register, chng ta s thc hin xy dng khi 16 thanh ghi theo cch nh sau (Vic phn tch cn i chiu vi mt s hnh v trong gio trnh Kin trc my tnh):

u vo D (16 dy) ca c 16 thanh ghi ni chung li vi nhau (cc ng truyn bit 0 ni vi nhau, cc ng truyn bit 1 ni vi nhau,...) v s ni vi Bus-C thng qua phn t input 16 bit (Xem Hnh 4-02 v Hnh 4-07).


u ra Q (16 dy) ca mi mt trong s 16 phn t Register c ni vi 2 u vo ca 2 b m 3 trng thi (phn t Controlled buffer thuc nhm Gates), c th c iu khin d liu ra hoc Bus-A, hoc Bus-B hoc ng thi ra c 2 Bus-A v Bus-B. 16 u ra ca 16 b m 3 trng thi th nht ni vi nhau v ni vi mt phn t output d liu ra Bus-A; 16 u ra ca 16 b m 3 trng thi th hai ni vi nhau v ni vi mt phn t output d liu ra Bus-B. Phn t Controlled buffer c u ra ni vi Bus-A c iu khin bi tn hiu t mt trong cc u ra ca A-decoder. Tng t nh vy, phn t Controlled buffer c u ra ni vi Bus-B c iu khin bi tn hiu t mt trong cc u ra ca B-decoder (Xem Hnh 4-02 v Hnh 4-07). Cc phn t Controlled buffer ni trn u l 16 bits (chng ta t thuc tnh Data Bits ca chng bng 16).

u vo tn hiu ng h ^ ca tt c 16 thanh ghi c ni vi nhau (Xem Hnh 4-02).

Mi u vo en (Enable) ca mt trong 16 phn t register ni vi mt u ra ca C-decoder. Nh vy C-decoder s chn ly 1 trong 16 thanh ghi nhn d liu t Bus-C vo.

u vo tn hiu xa 0: trong cc bi thc hnh ny, chng ta cha s dng n nn h (khng ni i u c), tc l khng xa.

6.3. Xy dng v m phng khi 16-Register

6.3.1 Xy dng khi 16-Register

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l 16registers-block. Trong ca s con gc trn bn tri, ngoi tn main, ALU-1bit, ALU-8bits, ALU-16bits logisim hin tn mch con (subcircuit) m chng ta va to ra, l 16registers-block.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con 16register-block s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, chng ta to mt tp 16 thanh ghi nh hnh v di y.


6.3.2 M phng hot ng ca khi 16-Register Chng ta c th m phng xem n v 16-Registers m chng ta va to ra c thc hin ng cc chc nng nh thit k khng.

Chn 1 trong 16 thanh ghi nhn d liu vo t Bus-C:

1. t gi tr cho phn t input clock bng 1 (s dng poke tool).

2. t gi tr cho phn t input Input from C-bus bng mt gi tr nh phn no , chng hn bng 1111.0000.1100.1100.

3. t gi tr cho phn t input From C-decoder bng 0000.0000.0000.0001 chn thanh ghi PC, cho n nhn d liu t phn t input Input from C-bus. Nu thay i gi tr ny (ch : lun ch c 1 bit bng 1, cn cc bit khc bng 0) th mt trong 15 thanh ghi khc c chn.

Ch : Vi mch in v cc gi tr c thit lp nh trn, chng ta thng khng c c gi tr nh phn cha vo thanh ghi c chn. c th nhn thy, chng ta thc hin thm 2 bc nh sau:

4. t gi tr cho phn t input From B-decoder gi tr nh phn ging gi tr t cho phn t input From C-decoder.


5. Dng phn t poke took o gi tr ca phn t input clock 2 ln; chng ta s nhn thy gi tr m thanh ghi c chn nhn t Bus-C, nay truyn ra phn t output To B-bus.

6.4. Bi tp (khng c trong gio trnh Kin trc my tnh) Hy s dng cc cc phn t Hex Digit Display v Splitter c c di dng s Hexa cc gi tr a vo cc phn t ouput To A-Bus v To B-Bus.


BI 7: Xy dng cc thnh phn cn li ca ng d liu

7.1. Cc yu cu v ni dung chnh ng d liu (Data Path) c trnh by trong Chng 4 Mc Vi chng trnh v c minh ha trn hnh v bn (Hnh 4-07).

Trong 2 bi thc hnh trc, chng ta xy dng v m phng s lm vic ca 2 thnh phn l ALU-16bits v khi 16 thanh ghi.

Trong bi thc hnh ny, chng ta s xy dng v m phng s hot ng ca cc thnh phn cn li ca ng d liu, l:

Shifter A Latch, B Latch AMUX MAR MBR


7.2. Xy dng v m phng s hot ng ca shifter

7.2.1 Phn tch

Thanh ghi dch (Shifter) m chng ta cn xy dng thc hin 1 trong 3 thao tc (php tnh) theo tn hiu iu khin 2 bit c k hiu l S1S0.

S1S0 Thao tc

00 No Shift (khng dch bit)

01 Shift Left (dch tri 1 v tr bit)

10 Shift Right (dch phi 1 v tr bit)

11 Khng s dng gi tr ny

Khi dch tri/phi, gi tr 0 c a vo v tr bit 0/15. Bit 15/0 b bt ra khi dch tri/phi nhng (trong mn hc ny) chng ta khng cn quan tm.

u vo (16 bits) ca shifter ni vi u ra ca ALU-16bits. u ra (16 bits) ca shifter ni vi u vo ca MBR v C-Bus. iu ny c ngha l

kt qu c th a ra b nh chnh (Main memory) thng qua MBR, hoc a vo 1 trong 16 thanh ghi qua C-Bus n tham gia vo php tnh khc.

7.2.2 Xy dng mch con shifter

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Shifter-16bits. Trong ca s con gc trn bn tri, ngoi tn main, ALU-1bit, ALU-8bits, ALU-16bits, 16registers-block logisim hin tn mch con (subcircuit) m chng ta va to ra, l Shifter-16bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Shifter-16bits s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, chng ta xy dng Shifter-16bits nh hnh v di y.

Ngoi cc phn t input v output bit, chng ta s dng cc phn t shifter trong nhm Arithmetic v phn t MUX (Multiplexer) trong nhm Plexers ca th vin trong logisim.


Phn t shifter:

o S thuc tnh: 2, chng ta cn thit lp gi tr ca chng cho ph hp vi yu cu ca mnh:

Data Bits: 16 (c th nhn cc gi tr trong min 1..32) Shift Type: Logical Left (cc gi tr khc c th nhn l: Logical Right,

Arithmetic Right, Roll Left, Roll Right)

o S chn: 3 (2 chn cho tn hiu vo, 1 chn cho tn hiu ra): 1 chn vo cho data (16 bits): pha trn bn tri. 1 chn ra cho data (16 bits): bn phi, c nh du mi tn, hng mi tn

ty theo chng ta chn thuc tnh Shift Type l left hay right.

1 chn vo iu khin s v tr bit s dch, trn hnh c ghi nhn bits to shift. Nu chng ta thit lp Data Bits =16 (2^4) th u vo ny nht thit phi l 4 bit. Nu chng ta ch mun dch 1 bit, th thit lp gi tr cho phn t input ni vi u vo ny bng 0001.

Phn t MUX (Multiplexer): o S thuc tnh: 3, chng ta cn thit lp gi tr ca n cho ph hp vi yu cu ca

mnh:

Facing: East - hng u ra v pha ng (cc gi tr khc: West, North, South)

Select Bits: 2 (v chng ta cn chn 1 trong 3 kt qu a ra) Data Bits: 16

o S chn: 6 (5 chn cho tn hiu vo, 1 chn cho tn hiu ra): Chn vo s 0 (c k hiu 0): 16 bits cho gi tr no shift. Chn vo s 1 (bn di chn 0): 16 bits cho gi tr shift left.


Chn vo s 2: 16 bits cho gi tr shift right. Chn vo s 3: khng s dng n. Chn vo cho 2 bits iu khin: trn cnh bn ca hnh thang cn (k hiu

ca Multiplexer).

Chn ra: 16 bits, nm cnh y nh ca hnh thang cn, c gi tr bng 1 trong 3 u vo, c chn bng 2 bits iu khin.

7.2.3 M phng hot ng ca shifter Chng ta c th m phng xem n v shifter m chng ta va to ra c thc hin ng cc chc nng nh thit k khng. C th thc hin nh sau:

1. t gi tr cho phn t Input bng mt gi tr nh phn no , chng hn bng 1111.0000.1100.1100.

2. S dng phn t poke tool thit lp gi tr cho 2 bits iu khin (SH Controller) ln lt bng 00, 01 v 10. Nu chng ta xy dng ng, ti u ra Output chng ta s thy cc gi tr a ra ln lt l: 1111.0000.1100.1100, 1110.0001.1001.1000 v 0111.1000.0110.0110. chnh l kt qu no shift, shift left v shift right i vi d liu a vo.

7.3. Xy dng v m phng s hot ng ca cc thanh ghi cht A Latch v B Latch

7.3.1 Phn tch Thanh ghi cht m chng ta s xy dng lm A Latch v B Latch c chc nng rt n gin. N c u vo v u ra 16 bits, u vo iu khin 1 bit (L0 iu khin A Latch, L1 iu khin B Latch). Khi tn hiu trn u vo iu khin bng 1, gi tr 16 bits u s c nh v a ra u ra. Khi tn hiu iu khin t 1 tr v 0, gi tr trong thanh ghi (v u ra) khng thay i c na, d gi tr u vo c thay i.

7.3.2 Xy dng thanh ghi cht

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Latch-16bits. Trong ca s con gc trn bn tri, ngoi tn main, ALU-1bit, ALU-8bits, ALU-16bits, 16registers-block, Shifter-16bits logisim hin tn mch con (subcircuit) m chng ta va to ra, l Latch-16bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Latch-16bits s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, chng ta xy dng Latch-16bits nh hnh v di y. Tt c cc phn t cn s dng chng ta u bit.


7.3.3 M phng hot ng ca thanh ghi cht (Latch Register) Chng ta c th m phng xem n v latch m chng ta va to ra c thc hin ng cc chc nng nh thit k khng. C th thc hin nh sau:

1. Ban u, bit Clock bng 0 v t gi tr cho phn t Input bng mt gi tr nh phn no , chng hn bng 1111.0000.1100.1100.

2. Thit lp gi tr cho bit Clock bng 1, chng ta s thy u ra Output s c gi tr ng bng Input l: 1111.0000.1100.1100.

3. o bit Clock bng 0.

4. Thay i gi tr ca Input, chng ta s thy Output khng b thay i.

7.4. Xy dng v m phng s hot ng ca AMUX AMUX l mt b dn knh 2-to-1, chng ta s s dng phn t Multiplexer trong nhm Plexers c trong th vin ca logisim. Ngoi phn t ny, chng ta khng cn thm mt phn t chc nng no khc to nn AMUX.

7.5 Xy dng v m phng s hot ng ca MAR

7.5.1 Phn tch

Chc nng ca thanh ghi cht a ch b nh MAR c m t ti mc 4.1.6 B nh chnh ca gio trnh Kin trc my tnh. Trn hnh v minh ha ng d liu u Bi s 7 ny, tn hiu iu khin M0 tch cc (=1) lm cho MAR cht d liu u vo ni vi u ra B Latch ca n, khi M0 o gi tr (t 1 v 0), ni dung MAR khng thay i theo tn hiu vo v lun c truyn ra u ra (chnh l Address Bus, thuc bus h thng ca my tnh). iu ng lu khi khi thc hnh m phng l, u ra v u vo ca MAR u truyn gi tr 12 bits ch khng phi 16 bits. 12 bits a vo u vo ca MAR ly t 12 bits thp trong s 16 bits truyn t u ra ca B Latch. Vic tch 12 bits ny chng ta s thc hin bng phn t splitter thuc nhm Base c trong th vin ca logisim, khi chng ta lp ghp ton b vi kin trc.


Ngoi tn hiu iu khin M0 ni trn phi c mc tch cc, chng ta bit rng, MAR ch c cht d liu trong chu k con th 3 ca n v ng h (vn ny c phn tch trong mc 4.2.3 Vic nh thi vi ch th, gio trnh Kin trc my tnh). Tm li, c 2 tn hiu iu khin MAR cht d liu, mt l tn hiu ly t bit MAR trong thanh ghi MIR (chnh l M0 trong hnh v u bi thc hnh ny); hai l tn hiu ly t ng chu k con th 3 ca n v ng h.

7.5.2 Xy dng thanh ghi MAR

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l MAR-16bits. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l MAR-16bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con MAR-16bits s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, chng ta xy dng MAR-16bits nh hnh v di y. Tt c cc phn t cn s dng chng ta u bit.

7.5.3 M phng hot ng ca MAR Chng ta c th m phng xem thanh ghi cht MAR va to ra c thc hin ng cc chc nng nh thit k khng. Vic thc hin tng t nh i vi thanh ghi cht trnh by ti mc 7.3.3 M phng hot ng ca thanh ghi cht, ch c mt s khc nhau nh, l c 2 tn hiu iu khin MAR. Cc bc thc hin nh sau:

1. Ban u, bit Clock v Mo bng 0, chng ta t gi tr cho phn t Input bng mt gi tr nh phn no , chng hn bng 1111.0000.1100.1100.

2. Thit lp gi tr cho bit Clock v Mo ng thi bng 1, chng ta s thy u ra Output s c gi tr ng bng Input l: 1111.0000.1100.1100. Hy th ch cho mt trong 2 tn hiu Clock v Mo bng 1, gi tr cn li bng 0, chng ta s thy thanh ghi khng th nhn gi tr Input.

3. o bit Clock bng 0.


4. Thay i gi tr ca Input, chng ta s thy Output khng b thay i.

7.6 Xy dng v m phng s hot ng ca MBR

7.6.1 Phn tch

Chc nng ca thanh ghi m d liu b nh MBR c m t ti mc 4.1.6 B nh chnh v mc 4.2.1 ng d liu (Data path)ca gio trnh kin trc my tnh.

Trn hnh v minh ha ng d liu u Bi thc hnh s 7 ny, chng ta thy c 3 tn hiu iu khin MBR:

M1: iu khin vic np ca MBR t u ra ca Shifter (M1 =1: np). Trong Hnh 4-09 S y ca mt vi kin trc, M1 c ni vi bit MBR ca MIR.

M2: iu khin vic c b nh, M2 c ni vi bit RD ca MIR. Khi c, d liu t b nh c cha vo MBR v truyn ra mt trong 2 u vo ca AMUX. D liu t u vo ny c th c iu khin i ra u ra v np vo u vo bn tri ca ALU.

M3: iu khin vic ghi b nh, M3 c ni vi bit WR ca MIR. Khi ghi, d liu ang cha trong MBR c a ra bus d liu ni vi Main memory ca MBR (bus bn tri MBR).

Ngoi 3 tn hiu iu khin ni trn, chng ta bit rng, MBR ch c cht d liu vo hoc a d liu ra trong chu k con th 4 ca n v ng h (vn ny c phn tch trong mc 4.2.3 Vic nh thi vi ch th, gio trnh Kin trc my tnh).

7.6.2 Xy dng thanh ghi MBR

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l MBR-16bits. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l MBR-16bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con MBR-16bits s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, chng ta xy dng MBR-16bits nh hnh v di y. Tt c cc phn t cn s dng chng ta u bit.

Ch :

Bus d liu ni MBR vi Main memory l bus 2 chiu; tuy nhin v logisim khng c phn t no va c th l input va c th l output, cho nn chng ta nh phi to ra 2 bus mt chiu thay th.


7.6.3 M phng hot ng ca MBR Chng ta c th m phng xem thanh ghi MBR m chng ta va to ra c thc hin ng cc chc nng nh thit k khng. Vic thc hin c nhiu bc tng t nh i vi thanh ghi cht (latch) v thanh ghi MAR.

M phng vic cha d liu t Bus-C vo MBR theo cc bc nh sau:

1. Ban u, cn thit lp gi tr cho:

MBR, RD, WR v Clock: 0 (c th chn t menu: simulate\Reset Simulation).

Input (Connect to C-bus): mt gi tr nh phn no , chng hn bng 1111.0000.1100.1100.

2. Thit lp gi tr cho bit MBR bng 1; sau o gi tr bit Clock t 0 thnh 1, chng ta s thy u ra Output s c gi tr ng bng Input l: 1111.0000.1100.1100.

M phng vic cha d liu t b nh vo MBR (c b nh) theo cc bc nh sau:

1. Ban u, trnh nhm ln, nn reset li m phng (menu: simulate \ Reset Simulation).

2. Thit lp gi tr cho phn t input From Main Memory: mt gi tr nh phn no , chng hn bng 1111.0000.1100.1100.

3. Thit lp gi tr cho bit MBR bng 1; sau o gi tr bit Clock t 0 thnh 1, chng ta s thy u ra Output s c gi tr ng bng Input l: 1111.0000.1100.1100.


M phng vic a d liu t MBR ra b nh (ghi b nh):

Sau vic m phng trn (cha d liu t b nh vo MBR), phn t Output ang cha gi tr 1111.0000.1100.1100, cn phn t output To Main Memory cha tng c gn gi tr nn c logisim coi l cha gi tr khng xc nh v hin th ni dung phn t ny bng 16 k t x.

Chng ta thc hin m phng vic ghi b nh theo nh sau:

Thit lp gi tr cho bit MBR bng 0 v bit WR bng 1, chng ta s thy u ra To Main Memory s c gi tr ng bng Output l: 1111.0000.1100.1100.

7.7. Bi tp Vi mch con MBR-16bits nh chng ta xy dng, vic ghi b nh ch i hi bit iu khin WR bng 1, ch khng cn Clock (subcycle 4) bng 1. Hy sa li mch con sao cho d liu t MBR ch a ra c bus d liu ni vi Main Memory khi bit iu khin Clock (subcycle 4) bng 1.


BI 8: Xy dng Control Store, MIR v Micro Seq ca n v iu khin

8.1. Cc yu cu v ni dung chnh n v iu khin CU (Ctrol Unit) c gii thiu khi qut trong mc 2.1 Kin trc chung ca my tnh in t; Ti chng 2, chng ta bit rng CU thc hin vic iu khin s hot ng ca tt c cc n v to nn h thng my tnh theo chng trnh trong b nh chnh.

CU c nghin cu su hn trong chng 4, ti cc mc 4.2.2 Vi ch th - microinstruction, 4.2.3 Vic nh thi vi ch th, 4.2.4 S nh trnh t cc vi ch th,...Trong s khi y ca mt vi kin trc di y, chng ta thy CU bao gm cc n v sau: Control Store, MIR, Micro Seq, MPC, Increment, Mmux, A Decoder, B decoder, C decoder v n v to tn hiu ng h - Clock.

Hnh 4-09 S khi y ca mt vi kin trc

Trong Bi thc hnh s 8, chng ta s xy dng v m phng s hot ng ca 3 trong s 9 n v cu thnh CU, l: Control Store, MIR v Micro Seq.


Control Store: phi cha c ton b vi chng trnh thc hin thng dch cc lnh ly v t b nh chnh (Main memory).

u vo: C 1 u vo a ch 8 bits ni vi u ra ca MPC. a ch ny dng chn 1 trong s 2^8 vi ch th cha trong Control Store.

u ra: C 1 u ra 32 bits ni vi u vo ca MIR. MIR: nhn ch th a ra t Control Store v duy tr ni dung trong thi gian thi hnh. Micro Seq: sinh ra tn hiu Mmux quyt nh chn vi ch th tip theo, cn c vo cc

tn hiu trng thi N, Z v tn hiu iu khin COND.

8.2. Xy dng v m phng s hot ng ca Control Store

8.2.1 Phn tch

V nguyn tc, Control Store c th l ROM hoc RAM. Trong bi thc hnh ny, chng ta s s dng phn t ROM c trong th vic ca logisim lm Control Store. L do: Trong bi thc hnh s 10, chng ta s to ra v m phng hot ng ca b nh chnh (Main memory), ch c th s dng phn t RAM. Nh vy chng ta s dng c 2 loi phn t nh trong thc hnh.

Kch thc: Trong mc 4.4 Th d v mt vi chng trnh, chng ta phn tch k lng mt vi chng trnh gm 79 vi ch th, mi vi ch th di 32 bit. Nh vy kch thc ca Control Store ti thiu l 79x32 bit. Tuy nhin, c th m rng c, yu cu sinh vin thit k Control Store c kch thc 256x32 bits.

T kch thc 256x32 dn n vic mt s trong cc thuc tnh ca phn t ROM lm Control Store bt buc phi c gi tr nh sau:

Address Bit Width: 8 ( c th chn 1 trong 256) Data Bit Width: 32 (kch thc 1 vi ch th)

Ni dung (Contents): Chnh l vi chng trnh c trnh by ti mc 4.4.2 Th d v mt vi chng trnh, sinh vin cn np vo phn t ROM, sau khi chuyn t dng MAL sang dng nh phn.

8.2.2. Xy dng v np ni dung cho Control Store

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Control-Store-256x32bits. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l Control-Store-256x32bits.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Control-Store-256x32bits s c lu cng vi Micro-Architecture-SVxx.circ.


Trong ca s con Canvas Window ca logisim, vic xy dng Control-Store-256x32bits ht sc n gin:

Ly mt phn t ROM trong nhm Memory t vo Canvas Window.

Thit lp gi tr cho cc thuc tnh ca n nh phn tch trn (Address Bit Width: 8; Data Bit Width: 32).

np ni dung cho phn t nh Control-Store, hy kch nt chut bn phi, logisim hin ln mt danh sch cc la chn. Hy chn Edit Contents..., logisim s hin ln mt ca s Logisim: Hex Editor ngi s dng np ni dung cho phn t nh Control-Store.

Vic np ni dung cho Control-Store tuy n gin, nhng mt nhiu thi gian v i

hi tuyt i chnh xc. Hnh v trn l ni dung Control-Store c np 79 (4FH = 4*16 + 15) words di dng s hexa, mi word 32 bits l mt vi ch th ca vi chng trnh lm nhim v thng dch.


Vi chng trnh c np vo Control Store

a ch

Statement

(Ch th ngn ng MAL)

A

M

U

X

C

O

N

D

A

L

U

S

H

M

B

R

M

A

R

R

D

W

R

E

N

C

C

B

A

A

D

D

R

Ch th (Hexa)

0 (00h) mar := pc; rd 0 00 00 00 0 1 1 0 0 0000 0000 0000 0000.0000 00.C0.00.00 1 (01h) pc := pc+1; rd; 0 00 00 00 0 0 1 0 1 0000 0110 0000 0000.0000 00.50.60.00 2 (02h) ir := mbr; if n then goto 28; 1 01 10 00 0 0 0 0 1 0011 0000 0000 0001.1100 B0.13.00.1C

3 (03h) tir :=lshift(ir+ir); if n then goto 19; 0 01 00 10 0 0 0 0 1 0100 0011 0011 0001.0011 24.14.33.13

4 (04h) tir := lshift(tir); if n then goto 11; 0 01 10 10 0 0 0 0 1 0100 0000 0100 0000.1011 34.14.04.0B

5 (05h) alu := tir; if n then goto 9; 0 01 10 00 0 0 0 0 0 0000 0000 0100 0000.1001 30.00.04.09 6 (06h) mar := ir; rd; 0 00 00 00 0 1 1 0 0 0000 0011 0000 0000.0000 00.C0.30.00 7 (07h) rd; 0 00 00 00 0 0 1 0 0 0000 0000 0000 0000.0000 00.40.00.00 8 (08h) ac := mbr; goto 0 1 11 10 00 1 0 0 0 1 0001 0000 0000 0000.0000 F1.11.00.00 9 (09h) mar := ir; mbr := ac; wr; 0 00 10 00 1 1 0 1 0 0000 0011 0001 0000.0000 11.A0.31.00

10 (0Ah) wr; goto 0; 0 11 00 00 0 0 0 1 0 0000 0000 0000 0000.0000 60.20.00.00 11 (0Bh) alu := tir; if n then goto 15; 0 01 10 00 0 0 0 0 0 0000 0000 0100 0000.1111 30.00.04.0F 12 (0Ch) mar := ir; rd; 0 00 00 00 0 1 1 0 0 0000 0011 0000 0000.0000 00.C0.30.00 13 (0Dh) rd; 0 00 00 00 0 0 1 0 0 0000 0000 0000 0000.0000 00.40.00.00


14 (0Eh) ac := mbr + ac; goto 0; 1 11 00 00 1 0 0 0 1 0001 0001 0000 0000.0000 E1.11.10.00

19 (13h) tir := lshift(tir); if n then goto 25; 0 01 10 10 0 0 0 0 1 0100 0000 0100 0001.1001 34.14.04.19

25 (19h) alu := tir; if n then goto 27; 0 01 10 00 0 0 0 0 0 0000 0000 0100 0001.1011 30.00.04.1B 26 (1Ah) pc := band(ir, amask); goto 0; 0 11 01 00 0 0 0 0 1 0000 1000 0011 0000.0000 68.10.83.00

a ch (Hexa)

Statement

(Ch th ngn ng MAL)

A

M

U

X

C

O

N

D

A

L

U

S

H

M

B

R

M

A

R

R

D

W

R

E

N

C

C

B

A

A

D

D

R

Ch th (Hexa)

(Cc vi ch th di y thy Vit cha kim tra li bng vic cho thc hin) a ch (Hexa) Ch th MAL Ch th (nh phn) Ch th (Hexa) 0E ac := mbr + ac; goto 0; 1110.0000.0001.0001.0001.0000.0000.0000 e0.11.10.00 0F mar := ir; rd; 0001.0000.1100.0000.0011.0000.0000.0000 10.c0.30.00 10 ac := ac + 1; rd; 0000.0000.0101.0001.0110.0001.0000.0000 00.51.61.00 11 a := inv(mbr); 1001.1000.0001.1010.0000.0000.0000.0000 98.1a.00.00 12 ac := ac + a; goto 0; 0110.0000.0001.0001.0101.0001.0000.0000 60.11.51.00 13 tir := lshift(tir); if n then goto 25; 0011.0100.0001.0100.0000.0100.0001.1001 34.14.04.19 14 alu := tir; if n then goto 23; 0011.0000.0000.0000.0000.0100.0001.0111 30.00.04.17 15 alu := ac; if n then goto 0; 0011.0000.0000.0000.0000.0001.0000.0000 30.00.01.00 16 pc := band(ir, amask); goto 0; 0110.1000.0001.0000.1000.0011.0000.0000 68.10.83.00 17 alu := ac; if z then goto 22; 0101.0000.0000.0000.0000.0001.0001.1000 50.00.01.18 18 goto 0; 0110.0000.0000.0000.0000.0000.0000.0000 60.00.00.00 1B ac := band(ir, amask); goto 0; 0110.1000.0001.0001.1000.0011.0000.0000 68.11.83.00


1C tir := lshift(ir+ir); if n then goto 40; 0010.0100.0001.0100.0011.0011.0010.1000 24.14.33.28 1D tir := lshift(tir); if n then goto 35; 0011.0100.0001.0100.0000.0100.0010.0011 34.14.04.23 1E alu := tir; if n then goto 33; 0011.0000.0000.0000.0000.0100.0010.0001 30.00.04.21 1F a := ir + sp; 0000.0000.0001.1010.0010.0011.0000.0000 00.1a.23.00 20 mar := a; rd; goto 7; 0111.0000.1100.0000.1010.0000.0000.0111 70.c0.a0.07 21 a := ir + sp; 0000.0000.0001.1010.0010.0011.0000.0000 00.1a.23.00 22 mar := a; mbr := ac; wr; goto 10; 0111.0001.1010.0000.1010.0001.0000.1010 71.a0.a1.0a 23 alu := tir; if n then goto 38; 0011.0000.0000.0000.0000.0100.0010.0110 30.00.04.26 24 a := ir + sp; 0000.0000.0001.1010.0010.0011.0000.0000 00.1a.23.00 25 mar := a; rd; goto 13; 0111.0000.1100.0000.1010.0000.0000.1101 70.c0.a0.0d 26 a := ir + sp; 0000.0000.0001.1010.0010.0011.0000.0000 00.1a.23.00 27 mar := a; rd; goto 16; 0111.0000.1100.0000.1010.0000.0001.0000 70.c0.a0.10 28 tir := lshift(tir); if n then goto 46; 0011,0100.0001.0100.0000.0100.0010.1110 34.14.04.2e 29 alu := tir; if n then goto 44; 0011.0000.0000.0000.0000.0100.0010.1100 30.00.04.2c 2A alu := ac; if n then goto 22; 0011.0000.0000.0000.0000.0001.0001.0110 30.00.01.16 2B goto 0; 0110.0000.0000.0000.0000.0000.0000.0000 60.00.00.00 2C alu := ac; if z then goto 0; 0101.0000.0000.0000.0000.0001.0000.0000 50.00.01.00 2D pc := band(ir, amask); goto 0; 0110.1000.0001.0000.1000.0011.0000.0000 68.10.83.00 2E tir := lshift(tir); if n then goto 50; 0011.0100.0001.0100.0000.0100.0011.0010 34.14.04.32 2F sp := sp + (-1); 0000.0000.0001.0010.0111.0010.0000.0000 00.12.72.00 30 mar := sp; mbr := pc; wr; 0001.0001.1010.0000.0010.0000.0000.0000 11.a0.20.00 31 pc := band(ir, amask); wr; goto 0; 0110.1000.0011.0000.1000.0011.0000.0000 68.30.83.00 32 tir := lshift(tir); if n then goto 65; 0011.0100.0001.0100.0000.0100.0100.0001 34.14.04.41 33 tir := lshift(tir); if n then goto 59; 0011.0100.0001.0100.0000.0100.0011.1011 34.14.04.3b 34 alu := tir; if n then goto 56; 0011.0000.0000.0000.0000.0100.0011.1000 30.00.04.38 35 mar := ac; rd; 0001.0000.1100.0000.0001.0000.0000.0000 10.c0.10.00 36 sp := sp + (-1); rd; 0000.0000.0101.0010.0111.0010.0000.0000 00.52.72.00 37 mar := sp; wr; goto 10; 0110.0000.1010.0000.0010.0000.0000.1010 60.a0.20.0a 38 mar := sp; sp := sp + 1; rd; 0000.0000.1101.0010.0010.0110.0000.0000 00.d2.26.00


39 rd; 0000.0000.0100.0000.0000.0000.0000.0000 00.04.00.00 3A mar := ac; wr; goto 10; 0111.0000.1010.0000.0001.0000.0000.1010 70.a0.10.0a 3B alu := tir; if n then goto 62; 0011.0000.0000.0000.0000.0100.0011.1110 30.00.04.3e 3C sp := sp + (-1); 0000.0000.0001.0010.0111.0010.0000.0000 00.12.72.00 3D mar := sp; mbr := ac; wr; goto 10; 0111.0001.1010.0000.0010.0001.0000.1010 71.a0.21.0a 3E mar := sp; sp := sp + 1; rd; 0000.0000.1101.0010.0010.0110.0000.0000 00.02.26.00 3F rd; 0000.0000.0100.0000.0000.0000.0000.0000 00.40.00.00 40 ac := mbr; goto 0; 1111.0000.0001.0001.0000.0000.0000.0000 f0.11.00.00 41 tir := lshift(tir); if n then goto 73; 0011.0100.0001.0100.0000.0100.0100.0110 34.14.04.46 42 alu := tir; if n then goto 70; 0011.0000.0000.0000.0000.0100.0100.0110 30.00.04.46 43 mar := sp; sp := sp + 1; rd; 0000.0000.1101.0010.0010.0110.0000.0000 00.d2.26.00 44 rd; 0000.0000.0100.0000.0000.0000.0000.0000 00.40.00.00 45 pc := mbr; goto 0; 1111.0000.0001.0000.0000.0000.0000.0000 f0.10.00.00 46 a := ac; 0001.0000.0001.1010.0000.1010.0000.0000 10.1a.0a.00 47 ac := sp; 0001.0000.0001.0001.0000.0010.0000.0000 10.11.02.00 48 sp := a; goto 0; 0111.0000.0001.0010.0000.1010.0000.0000 70.12.0a.00 49 alu := tir; if n then goto 76; 0011.0000.0000.0000.0000.0100.0100.1100 30.00.04.4c 4A a := band(ir, smask); 0000.1000.0001.1010.1001.0011.0000.0000 08.1a.93.00 4B sp := sp + a; goto 0; 0110.0000.0001.0010.1010.0010.0000.0000 60.12.a2.00 4C a := band(ir, smask); 0000.1000.0001.1010.1001.0011.0000.0000 08.1a.93.00 4D a := inv(a); 0001.1000.0001.1010.0000.1010.0000.0000 18.1a.0a.00 4F a := a + 1; goto 75; 0110.0000.0001.1010.0110.1010.0100.1011 60.1a.6a.4b

(Ch : du . c vit thm vo gia cc nhm 4 bit nh phn v cc nhm 2 s hexa cho d c; khng np chng vo Control-Store)


8.2.3. M phng s hot ng ca Control Store Vi cch xy dng Control Store ch gm 1 phn t ROM ly trong th vin ca logisim, chng ta ch c th m phng s hot ng ca n khi lp ghp y cc thnh phn ca vi kin trc. Vic thc hnh m phng Control Store s c thc hin trong Bi thc hnh s 10.

8.2. Xy dng v m phng s hot ng ca MIR

8.2.1 Phn tch

Kch thc: 32 bits (cha c 1 vi ch th). u vo: C 1 u vo 32 bits ni vi u ra ca Control Store. u ra: 32 bit c nhm thnh 13 nhm tn hiu, mi nhm tn hiu hoc iu

khin mt n v thnh phn nh trc no ca ng d liu (th d: ALU, SH,...), hoc a vo mt n v thnh phn nh trc no thuc CU iu khin mt n v thnh phn nht nh thuc CU (th d: Micro Seq, Mmux, ) hoc ng d liu (th d: cc decoders).

8.2.2 Xy dng thanh ghi MIR

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l MIR. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l MIR.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con MIR s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, xy dng MIR nh hnh v sau:


Ch : Cc phn t reg lm 16 thanh ghi trn c u vo en c logisim t gi tr mc nh bng 1 (active), v vy chng ta khng cn ni 16 u en ca 16 thanh ghi li vi nhau v truyn vo gi tr 1.

8.2.3 M phng hot ng ca thanh ghi MIR M phng vic a d liu t Input (ni vi Control-Store) vo MIR:

Thit lp gi tr cho phn t Input, th d bng: 1111.0000.1111.0000.1111.0000.1111.0000.

S dng phn t poke tool o gi tr ca phn t input Clock t 0 ln 1, chng ta s thy phn t Output nhn gi tr bng gi tr ca phn t Input.

8.3. Xy dng v m phng s hot ng ca Micro Seq

8.3.1 Phn tch

Mmux = LRN LRZ LR RN LZ LR+ + = + + Chng ta s xy dng mch sinh tn hiu Mmux = LR+ZRL+RNL cho d hiu hn. 8.3.2 Xy dng mch con Micro Seq

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Micro-Seq. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l Micro-Seq.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Micro-Seq s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, xy dng Micro-Seq nh hnh v sau y:


8.3.3 M phng hot ng ca Micro Seq M phng hot ng ca mch con Micro-Seq: Thit lp gi tr cho phn t input COND ln lt bng: 00, 01, 10 v 11, kim tra gi tr ti u ra MMUX ph thuc vo N v Z nh th no:

COND = 00: MMUX lun bng 0, khng ph thuc vo N v Z. COND = 01: MMUX bng 1 nu N = 1 (N v Z khng bao gi ng thi bng 1). COND = 10: MMUX bng 1 nu Z = 1. COND = 11: MMUX lun bng 1, khng ph thuc vo N v Z.


BI 9: Xy dng cc thnh phn cn li ca b iu khin

9.1. Cc yu cu v ni dung chnh Trong bi thc hnh ny, chng ta s to ra v m phng s hot ng ca cc n v cn li ca CU, bao gm cc n v sau:

MPC: con tr vi ch th. Increment: nhn input t MPC ri cng thm 1 v a ra u ra truyn ti Mmux. Mmux: B dn knh 2-to-1, rng cc ng vo/ra l 8 bits. A Decoder, B decoder v C decoder A v B decoder l cc b gii m a ch 4-to-16 thng thng. C decoder: ngoi chc nng gii m thng thng nh A v B decoder, C decoder

cn phi c 1 c im khc na: 1 trong 16 u ra c chn ch c truyn mc logic 1 ra ngoi khi v ch khi ENC=1 ng thi tn hiu ng h u ra subcycle 4 c mc 1.

Clock: n v to tn hiu ng h c 4 u ra cng tn s do chng ta chn, nhng lch pha nhau 90 .

9.2. Xy dng v m phng hot ng ca thanh ghi MPC

9.2.1 Phn tch Nh c th thy trn Hnh 4-09 S khi y ca mt vi kin trc trong Bi thc hnh s 8, MPC c:

1 u vo d liu 8 bits ni vi u ra ca n v Mmux, y chnh l a ch ca vi ch th trong Control Store cn a ra MIR thc hin.

1 u ra d liu 8 bits a vo Control Store. 1 u ra d liu 8 bits a vo n v Increment lm tng ln 1. 1 u vo iu khin ni vi u ra tn hiu chu k con th 4 (subcycle 4) ca n v

Clock, ch khi tn hiu ny bng 1 th MPC mi cht gi tr u vo (ngha l gi tr u ra nhn gi tr ca u vo), cn khi tn hiu ny bng 0 th gi tr cha trong MPC (v gi tr u ra) khng thay i.

9.2.2 Xy dng thanh ghi MPC

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l MPC. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l MPC.


Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con MPC s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, xy dng MPC nh hnh v sau y:

9.2.3 M phng hot ng ca thanh ghi MPC M phng vic a d liu t Input from MMUX vo MPC:

Thit lp gi tr nh phn 8 bits cho phn t Input from MMUX, th d bng: 1111.0000.

S dng phn t poke tool o gi tr ca phn t input subcycle 4 t 0 ln 1, chng ta s thy phn t output to MIR nhn gi tr bng gi tr ca phn t Input from MMUX.

9.3. Xy dng v m phng hot ng ca n v Increment

9.3.1 Phn tch Vi yu cu nu trong mc 9.1 th y l b cng, tan hng vo th nht l d liu ra t MPC (chnh l a ch ca ch th a ra thi hnh); tan hng vo th 2 l hng +1. Kt qu ca php cng s a tr li 1 trong 2 u vo ca Mmux.

9.3.2 Xy dng mch con Increment

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Increment. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l Increment.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Increment s c lu cng vi Micro-Architecture-SVxx.circ.


Trong ca s con Canvas Window ca logisim, xy dng Increment nh hnh v sau y:

9.3.3 M phng hot ng ca Increment M phng vic thc hin chc nng cng 1 ca Increment:

Thit lp gi tr nh phn 8 bits cho phn t Input (from MPC), th d bng: 1111.0000.

Quan st phn t Output (to Mmux) chng ta s thy gi tr va a vo tng thm 1, bng 1111.0001.

9.4. Xy dng v m phng hot ng ca n v Mmux y l mt b dn knh 2-to-1 thng thng, tng t Amux m chng ta tm hiu, xy dng v m phng trong bi thc hnh s 7 (mc 7.4). iu khc nhau duy nht l vi Mmux, cc ng d liu vo/ra l 8 bits ch khng phi 16 bits nh vi Amux.

9.5. Xy dng v m phng hot ng ca decoder

9.5.1 Phn tch

A v B decoders: y l cc decoder 4-to-16 thng thng. C decoders: theo cc yu cu trnh by mc 9.1, mi mt trong s 16 u ra ca

C decoder phi i qua mt b m 3 trng thi (trong logisim l phn t controlled buffer) c iu khin bi tn hiu l kt qu and logic ca ENC v (Clock subcycle 4).

9.5.2 Xy dng mch con lm A, B decoder v m phng s hot ng ca n

Chng ta c th s dng phn t Decoder trong nhm Plexers trong th vin ca logisim, hoc chng ta s dng cc phn t c b sung thm mt s phn t khc mch con m chng ta xy dng trng gn gng hn, nh s thc hin di y.

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Decoder-A&B. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l Decoder-A&B.


Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Decoder-A&B s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, xy dng Decoder-A&B nh hnh v sau y:

Ch :

Nu chng ta ch dng 1 phn t Decoder trong th vin ca logisim, th chng ta khng cn phi dng thm n 3 phn t, l:

Phn t input 4-bit input Phn t output 16 parallel line output Phn t Splitter chp 16 dy ra t decoder thnh 1 b dy cho gn. M phng vic thc hin chc nng ca Decoder-A&B:

Thay i tng dn gi tr ca phn t 4-bit input t 0000 n 1111. Quan st phn t 16 parallel line output chng ta s thy gi tr nh phn 16 bit thay

i, bit c gi tr 1 chuyn t v tr 0 n v tr 15, trong khi cc bit cn li bng 0.

9.5.3 Xy dng mch con lm C decoder v m phng s hot ng ca n

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Decoder-C. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l Decoder-C.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Decoder-C s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, xy dng Decoder-C nh hnh v sau y:


M phng vic thc hin chc nng ca Decoder-C: Thc hin tng t nh khi m phng Decoder-A&B, nhng thc hin 2 ln:

Ln th nht thit lp gi tr cho ENC v CLOCK sao cho ENC.CLOCK bng 1. Ln th hai thit lp gi tr cho ENC v CLOCK sao cho ENC.CLOCK bng 0. 9.6. Xy dng v m phng hot ng ca Clock

9.6.1 Phn tch y l n v khng b iu khin bi bt c n v no khc trong vi kin trc. Nhim v ca n l sinh ra 4 tn hiu in lch pha nhau iu khin s phi hp cng vic nhp nhng gia cc thnh phn thuc ng d liu v thuc n v iu khin CU.


Vi vi kin trc c nghin cu trong mn hc Kin trc my tnh, tr cc ch th Read v Write, cc ch th c thi hnh trong thi gian nh nhau v c gi l 1 chu k ng d liu. Nh vy, cc tn hiu ng h c coi l lch pha nhau 900.

9.6.2 Xy dng mch con lm n v Clock

Vo menu Project \ Add Circuit, logisim s hin ln mt ca s nh, hi tn m ta mun t cho mch in. Hy t tn l Clock-4-subcycles. Trong ca s con gc trn bn tri, ngoi tn main v tn cc mch con m chng ta to ra t trc, logisim hin tn mch con (subcircuit) m chng ta va to ra, l Clock-4-subcycles.

Lu (save) mch in m chng ta to ra vo file (Micro-Architecture-SVxx.circ): vo menu File \ Save. Mch con Clock-4-subcycles s c lu cng vi Micro-Architecture-SVxx.circ.

Trong ca s con Canvas Window ca logisim, xy dng Clock-4-subcycles nh hnh v sau y. V trong th vin ca logisim ch c 1 loi phn t clock 1 pha, cho nn chng ta bt buc phi s dng thm mt s phn t khc na to 4 tn hiu ng h c cng tn s nhng lch pha nhau 900. Cc phn t c s dng xy dng mch con ny bao gm:

Clock: ly trong th vin ca logisim. S thuc tnh ca n c th thay i c l 5, ngha cc thuc tnh rt d hiu. Ngoi ra khi m phng hot ng ca clock, chng ta c th thay i c:

+ Tn s: t 0.25 Hz n 4096 Hz (vo Menu: Simulate \ Tick Frequency).

+ Cch chy ng h: 1/ Tick One ( debug); 2/ Tick Enable ( chy bnh thng).

Counter: phn t m c trong th vin. Counter c cc thuc tnh sau:

+ Data bits (1..32): ln ca s m Counter s m. Chng ta cn t bng 2 Counter m t 0 n 3.

+ Maximum value: gii hn s cao nht m Counter m, phi t khng ln hn gi tr cha c trong Data bits.


+ Action on Overflow: 1/ Wrap around (m vng li t s b nht); 2/ Stay at value (dng m) ...

+ Trigger: 1/ Rising Edge (kch hot vic m bi sn dng); 2/ Falling Edge (kch hot vic m bng sn m).

+ Label: nhn do chng ta t.

+ Label Font: kiu v c font ch ca Label.

Trn hnh v, Counter c tt c 7 chn vo/ra. Trong Canvas Window, khi chng ta di con tr n cc chn ny, logisim s hin mt dng gii thch:

+ ^: Clock: value may update on trigger. Khi tn hiu (xung ng h) t vo y thay i t mc thp ln mc cao, s lm thay i gi tr cha trong counter 1 n v. S thay i c th l tng hoc gim ph thuc vo mt s tn hiu iu khin khc, s c m t di y.

+ 0: Clear: clear, when 1 resets to 0 asynchronously. Gi tr mc nh u vo ny l 1, chng ta c th trng chn ny.

+ ct: Count, when 1, counter increments (or decrement if load =1). Nu a gi tr 1 vo y, counter s m tin.

+ D: value to load into counter. y l u vo cho gi tr ban u (nhiu bit) m chng ta mun np cho counter.

+ Q: Output: current value of counter. y l u ra cho gi tr hin thi ca counter.

+ u vo trn cng bn tri (khng c k hiu): Load: when 1, loads from data input (if Count =0) or decrements.

Decd (Decoder): y l phn t gii m thng thng, c sn trong th vin. 4 phn t output c ghi nhn 1, 2, 3, 4 tng ng vi 4 u ra truyn tn hiu

ca 4 chu k con.

9.6.3 M phng s hot ng ca Clock Hy chn Tick Enable hoc chn Tick Once nhiu ln, chng ta s nhn thy ni dung phn t counter thay i tng dn t 0 n 3 v vng li gi tr 0.

C th thay i tn s ng h thay i tc m (Simulate \ Tick Frequency).


PH LC A: HNG DN S DNG LOGISIM

Logisim c cc hng dn rt tt; khi ang chy logisim, c th m Help xem cc ti liu hng dn sau:

- The Guide to Being a Logisim User

- Beginners tutorial

- Library Reference

Sau y l bn dch ti liu The Guide to Being a Logisim User ca mt nhm sinh vin K53CA, chun b cho bo co seminar ca nhm thuc mn hc Kin trc my tnh. Bn dch ny cn mt s li v thiu st, nhng c th dng tm c nu ngi c ngi c bn ting Anh.

Logisim l mt cng c gio dc dng cho vic thit k v m phng cc mch lgc s. Vi giao din n gin dng thanh cng c v vic m phng cc mch ging nh mch c xy dng, s rt d dng n gin ha vic hc nhng t tng c bn nht lin quan n mch logic. Vi chc nng xy dng cc mch ln t cc mch con nh hn v v cc b dy ch vi mt c r chut, Logisim c th c s dng( v ang c s dng) thit k v m phng ton b cc CPU cho mc ch gio dc.

Sinh vin cc trng i hc v cao ng trn ton th gii s dng Logisim cho rt nhiu mc ch, trong c:

Mt mun trong tng quan khoa hc my tnh i cng


Mt n v hc trnh trong kha hc t chc h thng my tnh ca sinh vin nm th hai

Trong sut hc k ca kha hc kin trc my tnh mc chuyn su. Hng dn s dng Logisim m bn ang c l ti liu tham kho chnh thc cho cc tnh nng ca Logisim. Phn th nht ca ti liu l mt chui cc mc gii thiu nhng phn chnh ca Logisim. Cc mc ny c vit sao cho chng c c k cng hc tt c nhng tnh nng quan trng nht ca Logisim.

Nhng mc cn li l mt tp hp ca cc t liu tham kho v ch thch ca mt vi kha cnh nh hn ca Logisim.

1. CH DN CHO NGI MI S DNG

Cho mng bn n vi Logisim

Logisim cho php bn thit k v m phng mch cc k thut s. N c nh hng nh mt cng c gio dc, s dng gip cho vic hc cc mch hot ng nh th no.

To practice using Logisim, let's build a XOR circuit - that is, a circuit that takes two inputs (which we'll call x and y) and outputs 0 if the inputs are the same and 1 if they are different. The following truth table illustrates.

tp s dng Logisim, chng ta s xy dng mt mch XOR- mt mch ly 2 gi tr u vo ( x v y) v cho gi tr u ra l 0 nu x v y ging nhau, 1 nu x v y khc nhau. Bng chn l sau y th hin.

Chng ta nn thit k mch nh vy trn giy.


Tuy nhin bi v mch c v trn giy khng c ngha mch l chnh xc. xc minh mch , chng ta s c n trn Logisim v kim tra. Nh mt li th thm na, chng ta s c mt mch p hn ci m ta s c nu v bng tay.

Enjoy your circuit-building!

1.1 Bc 0: T nh hng chnh bn thn bn

Khi khi ng Logisim, bn s thy mt ca s gn ging hnh bn di. Mt vi chi tit c th khc nhau mt cht v bn c th s dng h thng khc so vi ca ti.

Logisim c chia thnh 3 phn, explorer pane, attribute table ( bng thuc tnh) v canvas. Bn trn 3 phn ny l thanh menu ( menu bar ) v thanh cng c ( toolbar).

Chng ta c th nhanh chng b qua explorer pane v attribute table: chng ta s khng kim tra chng trong khun kh bn hng s dng dn ny v bn chi c th b qua chng. Cng vi , menu bar s c cc bn t khm ph.


Cn li toolbar v canvas. Canvas l ni bn c th v mch ca minhf v toolbar bao gm cc cng c m bn s s dng hon thnh n.

1.2 Bc 1: Thm cc cng

Hy nh li rng chng ta ang c gng xy dng mch sau trn Logisim.

Ti khuyn co vic xy dng mch bng cch chn cc cng vo trc ging nh s sp xp khung xng v sau mi lin kt chng li bng dy ni. Vic trc tin ta s lm l chn thm 2 cng AND. Kch chut vo cng c AND ( AND tool) trn thanh cng c. Sau kch chut vo ni m bn mun cng AND th nht i n. Hy chc chn rng bn dnh ch cho phn bn tri. Sau bn tip tc kch chut vo AND tool mt ln na v t cng AND th hai bn di cng th nht.

n 5 du chm pha bn tri ca cng AND. Chng l nhng im m dy ni c th c gn. Tnh c chng ta s ch dng 2 trong s chng cho mch XOR ca chng tam tuy nhin i vi cc mch khc, bn s nhn ra rng c nhiu hn 2 dy trong mt cng AND l hu dng,

By gi, thm 1 cng khc vo mch. Kch vo OR tool ( ); , sau kch vi ni bn mun t n v t 2 cng NOT trn bn v s dng NOT tool ( ).


Ti dnh 1 t khong trng gia cc cng NOT v cc cng AND, nu bn mun, bn c th t chng ngc nhau v tit kim cng sc lin kt chng li vi nhau bng dy ni sau ny.

By gi chng ta mun thm 2 gi tr u vo x v y vo bn v. Chn Input tool ( ) v ng cc cht xung. Bn cng nn t mt cht u ra bn cnh cng u ra ca OR bng cch dng Output tool ( ). ( Mt ln na, ti cha li mt cht khong trng gia cng OR v cht u ra, nhng bn nn t chng ngay bn cnh nhau).

Nu bn khng thch ni m bn t phn t no , bn c th chn n bng Edit tool ( ) v th n vo phn bn v. Hoc bn c th xa hon ton phn t bng cch chn Delete trn bng chnh sa ( Edit menu ) hoc n phm Delete.

Khi bn t bt c thnh phn no ca mch, bn s nhn thy rng ngay khi thnh phn c t vo, Logisim quay li Edit tool th nn bn c th di chuyn thnh phn mi c t vo hoc kt ni n vi cc thnh phn khc bng cch to ra cc dy ni. Nu nh bn mun thm vo mt bn sao ca thnh phn mi thm vo, mt phm tt l t hp Ctrl + D nhn i thnh phn c chn. ( Mt vi my tnh s dng


phm khc cho menus, v d nh Command key trn my Macintoshes. Bn c th bm phm vi phm D ).

1.3 Bc 2: Thm dy ni

Sau khi c tt c cc thnh phn c thit lp trn bn v, bn c th bt u thm cc on dy ni. Chn Edit Tool ( ). Khi con tr trn im c th ni dy, mt vng trn nh mu xanh s bao quanh im . Nhn chut im v ko dy n ni bn mun.

Logisim kh thng minh trong vic chn dy ni. Bt c khi no mt dy kt thc trn dy khc, Logisim s t ng ni chng li vi nhau. Bn cng c th ko di hoc thu gn mt dy ni bng cch ko mt trong hai u ca dy, s dng writing tool.

Dy ni trong Logisim ch c th nm ngang hoc dc. c th ni u vo trn vi cng NOT v cng AND, ti cn dng thm 3 dy khc nhau.

Logisim t ng ni cc dy vi cc cng v cc dy vi nhau. Trong gm c vic t ng v chm trn phn giao nhau hnh ch T ca cc dy nh trn hnh, th hin rng cc dy c ni vi nhau.

Khi v cc dy ni, bn c th thy mt vi dy mu xanh da tri hoc dy mu xm. Mu xanh da tri th hin rng gi tr mt im

hdth ktmt bang mophong logisim moi

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