thi nghiem ktmt - bai-3

Bi th nghim Kin trc my tnh 3

2010

Bi 3. Hot ng ca b m, ti u ha b m(Bi th nghim ny c bin son da trn bi th nghim mn hc K thut my tnh ca F. Lundevall, Khoa cng ngh thng tin v truyn thng, Hc vin cng ngh Hong gia, Thy in [1])

1 Mc chTrong bi th nghim ny sinh vin s tm hiu b m trong b x l MIPS v hc cch ti u ha cc tham s b m, hoc cch thay i cu trc chng trnh c c hiu sut tnh ton cao hn.

2 Cng cBi th nghim s dng b phn mm MIPSIT [1] m phng hot ng ca mt h thng my tnh da trn b x l MIPSIT.

3 L thuytSinh vin cn nm r v b m; cc tham s ca b m m c nh hng n hiu sut tnh ton ca b x l. Ngoi ra sinh vin cn c kin thc v cch sp xp cc lnh my v cc bin trong b nh (eng. memory mapping). (bi ging chng 2, chng 3). Sch tham kho [3]. Sinh vin cn hiu cc khi nim trong b m nh: t l trng (eng. hit rate), tn hao trt (eng. miss penalties), thi gian truy cp (eng. access time), b m nh x trc tip (eng. direct mapped cache), b m kt hp ton phn (eng. fully associative cache), b m kt hp k ng (eng. kway associative cache).

4 Thc hin4.1 Ci t v lm quen vi phn mm4.1.1 Ci t Ti b cng c MIPSIT t a ch: https://sites.google.com/site/fethutca/my-forms/MipsICT.zip?attredirects=0&d=1. Gii nn tp MipsICT.zip v chy tp nhn c MipsICT.exe phm mm t gii nn vo th mc: C:\MipsIT. Trong b phn mm MIPSIT, ta s s dng 2 phn mm MIPSITStudio (xem bi th nghim s 2) v Mips Simulator. 4.1.2 Gii thiu MIPSITStudio

Mipsitstudio l phn mm m phng hot ng ca h thng my tnh da trn b x l MIPS. Gi chng trnh bng cch chy tp C:\MipsIT\bin\Mips.exe (Hnh 1). Phm mm m phng vic thc hin mt chng trnh (c bin dch bng MIPSITStudio) trn mt h thng my tnh gm: 1. 2. 3. 4. 5. B x l MIPS (CPU) B m lnh (I-Cache) B m d liu (D-Cache) B nh chnh (RAM) Ca s console (Console)

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6. Thit b ngoi vi (I/O) Ca s hin th trng thi ca cc khi trong h thng ni trn c m bng cch bm vo cc khi tng ng trn s khi Hnh 1.

Hnh 1. Chng trnh m phng h thng my tnh dng CPU MIPS.

Hnh 2. Ca s hin th trng thi ca b x l (Register), b nh chnh (Memory), vo ra (Input&Output), v ca s Console.

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Trng thi ca CPU l gi tr ca cc thanh ghi hin th trong ca s thanh ghi (Hnh 2). Trng thi ca RAM l ni dung cc nh (Hnh 2). Trng thi ca Console l ca s hin th ni dung c chng trnh ghi ra bng cu lnh in ra mn hnh v d nh printf (Hnh 2). Trng thi ca I/O l ca s hin th ni dung cc cng iu khin n LED ra v cc cng tc vo (Hnh 2). Ca s D-Cache v I-Cache hin th cu trc b m (nh x trc tip, kt hp ton phn, hay kt hp k ng) v ni dung lu trong b m (Hnh 3).

Hnh 3. Ca s hin th trng thi b m lnh (I-Cache) v b m d liu (D-Cache). 4.1.3 Thit lp tham s b m

Trc khi thc hin m phng, cc tham s ca b m cn c thit lp bng cch la chn menu Edit->Cache/Mem Config. Trong cc tab Inst. Cache v Data Cache ca ca s thit lp (Hnh 4), cc tham s cu trc ca b m lnh v b m d liu nh kch thc b m (eng. size), kch thc ng/khi (eng. block size), s lng ng/khi trong tp (eng. blocks in sets). (Cn ch s lng ng s xc nh loi b m: nh x trc tip, kt hp ton phn hoc kt hp k ng). Ngoi ra, vi b m d liu, ta c th thit lp chnh sch thay th (eng. Replacement policy), v chnh sch ghi (eng. Write policy). Ta c th v hiu ha (loi b) b m khi h thng bng cch chn Disable. Tn hao trt b m (thi gian truy cp b nh chnh) s khng c tnh n khi m phng nu chn Disable penalty.

Hnh 4. Ca s thit lp cc tham s cu trc b m I-Cache, D-Cache.

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Tn hao trt ph thuc vo thi gian truy cp b nh chnh. Cc tham s ny c thit lp bng tab Memory (Hnh 5). Thi gian c v ghi b nh chnh c xc nh bng s chu kz xung nhp ca CPU. y c gi tr mc nh l 50 chu kz. Cc tham s ny ph thuc vo cng ngh ch to b nh chnh, c xc nh da trn cc tham s thi gian ca RAM (Tham kho [4]).

Hnh 5. Thit lp thi gian truy cp b nh chnh. 4.1.4 Thc hin m phng

Chng trnh sau khi c bin dch thnh tp thc thi s c np vo b nh h thng m phng t phn mm MIPSITStudio bng cch la chn menu Build->Upload->To Simulator hoc bng phm tt F5. Phn mm m phng s thc hin chng trnh c np bng cch bm nt cng c. trn thanh

Cc kt qu m phng nh s ln trng, trt b m, t l trng, s chu kz thc hin chng trnh c hin phn Cache Statistics bn di phi ca ca s I-Cache, D-Cache. thc hin mt ln m phng mi, h thng cn c khi to li (eng. reset) bng menu CPU>Reset. Sau khi khi to li, v b m v b nh s tr v trng thi mc nh, cc tham s b m, b nh phi c thit lp li. Thm vo , chng trnh c bin dch cn c np li t MIPSITStudio.

4.2 Ti u b m lnh cho chng trnh copy chui4.2.1 Bc 1: Chun b chng trnh C. To mt n C(minimal)/Assembler trong mi trng MIPSITStudio. t tn n ny l Bai3-1. Chn th mc lu l C:\MipsIt\Projects\Bai3-1. To mt tp chng trnh C vi tn bai3-1.c. Son tho on m C vo tp chng trnh nh Hnh 6. Bin dch n bng cch la chn menu Build -> Build Bai3-1 hoc phm F7.

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1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25.

/* strcpy.c */ #include #include /* C stringcopy */ static void str_cpy( char *to, const char *from) { while( *from) { *to++ = *from++; } *to = '\0'; } int main() { static char* hello = "Hello"; static char to[4711] = "Function str_cpy"; int Time; printf("String before copy: %s\n", hello); flush_cache(); /* khi to li cc b o b m */ timer_start(); /* bt u tnh thi gian thc hin hm str_cpy*/ str_cpy( to, hello); Time = timer_stop(); /* kt thc tnh thi gian thc hin hm str_cpy*/ printf("Time to copy: %d\n",Time); /* In ra tng thi gian copy */ printf("String after copy: %s\n", to); }

Hnh 6. Chng trnh bai3-1.c 4.2.2 Bc 2: M phng.

Chy phn mm m phng C:\MipsIT\bin\Mips.exe. Quay v phn mm MIPSITStudio, np chng trnh bin dch vo phn mm m phng (phm tt F5). Chng trnh c cu lnh in ra thi gian thc hin hm str_cpy tnh bng s chu kz ng h. Tr li cc cu hi: Cu 1. Thc hin m phng xc nh cc kt qu: s ln trng, s ln trt b m, t l trng, s chu kz thc hin chng trnh thng k bi phn mm m phng (eng. Cycle count) v s chu kz tnh bi chng trnh (eng. Time to copy). Hit count = . Miss count = . Hit rate = . Cycle count=.. Time to copy= Tnh ton ch s CPI khi h thng thc hin hm str_cpy (ch thi gian thc t thc hin hm copy khc thi gian thng k bi phn mm m phng, y ta dng thi gian thng k bi phn mm m phng) CPI=..

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Cu 2. Thay i chui hello trong chng trnh bng cc gi tr Hello!, Hello!!, Hello!!!, Hello!!!! trong di ca chui tng ln lt thm 1 k t. Bin dch li chng trnh bng MIPSITStudio, np li vo phn mm m phng v m phng li. Xc nh cc kt qu cho mi ln m phng v in vo bng di y. (S lnh l tng ca s ln trng v s ln trt ca b m lnh). TT 1 2 3 4 5 Chui Hello Hello! Hello!! Hello!!! Hello!!!! Hit count Miss count Number of instructions Hit rate Cycle count Time to copy CPI

Bng 1. Kt qu m phng chng trnh copy cc chui c di khc nhau. Cu 3. Khi ta thm 1 k t vo chui cn copy nh trong th nghim Cu 2, s lng lnh c thc hin tng tng ng vi s lnh trong vng lp t dng 7 n dng 10 Hnh 6. T Bng 1 hy xc nh s lnh trong vng lp ca hm copy chui str_cpy. . . . . . . Cu 4. So snh kch thc b m lnh v s lnh trong vng lp xc nh Cu 3 v gii thch ti sao t l trng ca b m lnh trong Bng 1 li thp. . . . . . . 4.2.3 Bc 3: Ti u ha b m lnh

Trong phn ny, ta thc hin m phng vi cc tham s b m lnh khc nhau tm ra tham s b m lnh ti u khi thc hin chng trnh str_cpy. Cu 5. Thc hin bi m phng mt cch c h thng: thay i tham s kch thc, kch thc khi, kt hp ca b m lnh v tin hnh m phng li v xc nh cc kt qu m phng in vo bng di y. (Tham s v thi gian truy cp b nh chnh c cho trc). Ch trc khi thc hin ln m phng mi, cn khi to li CPU, thit lp cc tham s b m v np chng trnh t MIPSITStudio vo h thng.

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Kch thc 16 16 16 32 64

Kch thc khi 2 4 2 2 2

kt hp 1 1 2 1 1

Thi gian truy cp 50 35 50 50 50

Cycle count

CPI

I-Cache hit rate

I-Cache miss count

Dcache hit rate

D-cache miss count

Bng 2. Kt qu m phng thc hin chng trnh copy chui khi thay i cu trc b m lnh. Cu 6. Gii thch ngha kt qu m phng trong Bng 2. T rt ra tham s b m ti u cho vic thc thi chng trnh str_cpy. . . . . . .

4.3 Ti u cho chng trnh cng ma trn4.3.1 Bc 1: Chun b chng trnh C. To mt n C(minimal)/Assembler trong mi trng MIPSITStudio. t tn n ny l Bai3-2. Chn th mc lu l C:\MipsIt\Projects\Bai3-2. To mt tp chng trnh C vi tn bai3-2.c. Son tho on m C vo tp chng trnh nh Hnh 7. Chng trnh bai3-2.c. Bin dch n bng cch la chn menu Build -> Build Bai3-2 hoc phm F7. Trc khi bin dch, thit lp mc ti u bin dch (eng. Optimization level) l High nh Hnh 8 bng cch chn menu Project->Settings.

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1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35.

/* matris.c */ #include #include #define MATRIXSIZE 16 #define MATRIXSIZE_ROWS 16 #define MATRIXSIZE_COLS 16 /* Cng 2 ma trn */ void matrisadd( int res[MATRIXSIZE_ROWS][MATRIXSIZE_COLS], int a[MATRIXSIZE_ROWS][MATRIXSIZE_COLS], int b[MATRIXSIZE_ROWS][MATRIXSIZE_COLS] ) { int i,j; for(j=0; j < MATRIXSIZE; ++j) /* xt tng ct */ for(i=0; i < MATRIXSIZE; ++i) /* xt tng hng */ res[i][j] = a[i][j] + b[i][j]; } int main() { static int a[MATRIXSIZE_ROWS][MATRIXSIZE_COLS]; static int b[MATRIXSIZE_ROWS][MATRIXSIZE_COLS]; static int res[MATRIXSIZE_ROWS][MATRIXSIZE_COLS]; int i,j, Time; /* khi to 2 ma trn */ for( i=0; iD-Cache Stats (Hnh 9).

Hnh 9. Ca s thng k b m. Tr li cc cu hi: Cu 7. Thc hin m phng xc nh cc kt qu: s ln trng, s ln trt b m, t l trng, s chu kz thc hin chng trnh thng k bi phn mm m phng (eng. Cycle count). in vo bng di y.

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TT 1 2 3 4 5

Cycle count Number of instructions I-Cache hit rate I-Cache miss count D-Cache hit rate D-Cache miss count

Hit count

Bng 3. Kt qu m phng chng trnh cng 2 ma trn. Cu 8. Ti sao trong Bng 3 ta thu c t l trng b m lnh cao? Ti sao t l trng b m d liu li thp?. . . . . . . 4.3.3 Bc 3: Ti u ha b m d liu

Trong phn ny, ta thc hin m phng vi cc tham s b m d liu khc nhau tm ra tham s b m lnh ti u khi thc hin chng trnh cng ma trn. Trong phn ny hy thit lp tham s cho b m lnh nh x trc tip nh sau: Size = 32 words; Block size = 2 words, Blocks in Sets = 1. Vi b m d liu t gi tr chnh sch ghi: Write Policy = Write back. Cu 9. Thay i cc gi tr kch thc b m d liu vi cc gi tr 16, 32, 64, 128, 256, 512, 1024. t gi tr tham s Block size = 2 words; Blocks into sets = 1. Thc hin m phng v in kt qu vo bng di y. Cache Size D-Cache Hit rate Cycle count Bng 4. Kt qu m phng chng trnh matrisadd khi thay i kch thc b m d liu Cu 10. Ti sao t l trng ca b m d liu li thp? Bt u t kch thc no ca b m d liu th t l trng bt u tng? Ti sao? . . . . . . . 16 32 64 128 256 512 1024

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. . . . . Cu 12. Thay i gi tr kt hp (eng. associativity) ca b m d liu (tham s blocks in sets) vi cc gi tr 1, 2, 4. t kch thc b m d liu Size = 128 words; Block size = 4 words. Tham s chnh sch thay th l LRU. Thc hin m phng v in vo bng di y. Associativity D-Cache Hit rate Cycle count Bng 5. Kt qu m phng thc hin chng trnh matrisadd khi thay i kt hp b m d liu. Cu 13. Thay i gi tr kch thc khi ca b m d liu (tham s block size) vi cc gi tr 1, 2, 4. t kch thc b m d liu Size = 128 words; Blocks in sets = 1 words. Thc hin m phng v in vo bng di y. Block size D-Cache Hit rate Cycle count Bng 6. Kt qu m phng thc hin chng trnh matrisadd khi thay i kch thc khi b m d liu. Cu 14. T kt qu trong Bng 4, Bng 5 v Error! Reference source not found. hy xc nh tham s ti u cho b m d liu. . . . . 4.3.4 Bc 4: Ti u ha chng trnh. 1 2 4 1 2 4

Trong phn ny, ta thc hin thay i chng trnh nhm tm hiu cu trc chng trnh ti u. Thay i vng lp dng 13-15 ca chng trnh Hnh 7 vic cng c thc hin cho tng hng trc nh sau:13. 14. 15. for(i=0; i < MATRIXSIZE; ++i) /* xt tng hng */ for(j=0; j < MATRIXSIZE; ++j) /* xt tng ct */ res[i][j] = a[i][j] + b[i][j];

M phng vi cc tham s b m d liu khc nhau tm ra tham s b m lnh ti u khi thc hin chng trnh cng ma trn. Trong phn ny hy thit lp tham s cho b m lnh nh x trc tip nh sau: Size = 32 words; Block size = 2 words, Blocks in Sets = 1. Vi b m d liu t gi tr chnh sch ghi: Write Policy = Write back.

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Cu 15. Thay i cc gi tr kch thc b m d liu vi cc gi tr 16, 32, 64, 128, 256, 512, 1024. t gi tr tham s Block size = 2 words; Blocks into sets = 1. Thc hin m phng v in kt qu vo bng di y. Cache Size D-Cache Hit rate Cycle count Bng 7. Kt qu m phng chng trnh matrisadd v.2 khi thay i kch thc b m d liu Cu 16. Bt u t kch thc no ca b m d liu th t l trng bt u tng? Ti sao? So snh vi kt qu Cu 10. . . . . . . . . . . . . Cu 17. Thay i gi tr kt hp (eng. associativity) ca b m d liu (tham s blocks in sets) vi cc gi tr 1, 2, 4. t kch thc b m d liu Size = 128 words; Block size = 4 words. Tham s chnh sch thay th l LRU. Thc hin m phng v in vo bng di y. Associativity D-Cache Hit rate Cycle count Bng 8. Kt qu m phng thc hin chng trnh matrisadd v.2 khi thay i kt hp b m d liu. Cu 18. Thay i gi tr kch thc khi ca b m d liu (tham s block size) vi cc gi tr 1, 2, 4. t kch thc b m d liu Size = 128 words; Blocks in sets = 1 words. Thc hin m phng v in vo bng di y. Block size D-Cache Hit rate Cycle count 1 2 4 1 2 4 16 32 64 128 256 512 1024

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Bng 9. Kt qu m phng thc hin chng trnh matrisadd v.2 khi thay i kch thc khi b m d liu. Cu 19. T kt qu trong Bng 7, Bng 8 v Bng 9 hy xc nh tham s ti u cho b m d liu. . . . .

5 Ti liu tham kho[1] Ola Bergqvist and Georg Fischer. A Simulation and Development Environment Using Animation for Computer Architecture Education. Version 1.3.0, 1999. http://www.imit.kth.se/courses/IS1200/2008-2009/labcache/manual.html http://www.bostream.nu/mats.brorsson/mipsit/ [2] Mats Brorsson. MipsIt - A Simulation and Development Environment Using Animation for Computer Architecture Education. Proceedings of The workshop on Computer architecture education. 2002. http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.6.7683. [3] David A. Patterson and John L. Hennessy. Computer Organization and Design, Fourth Edition: The Hardware/Software Interface. In The Morgan Kaufmann Series in Computer Architecture and Design. Nov 10, 2008. [4] Kris Boughton and Rajinder Gill. Everything You Always Wanted to Know About SDRAM (Memory): But Were Afraid to Ask. Aug. 2010. http://www.anandtech.com/show/3851/everythingyou-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask.

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