hb0400: corejesd204btx v3.0 handbook - fpga & …2. this control over the ila sequence is used...

HB0400

CoreJESD204BTX v3.0

50200400-5/11.16

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Revision History

Revision 5 3

1 Revision History

The revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.

1.1 Revision 5.0Updated changes related to CoreJESD204BTX v3.0. SAR (83378): Add support for 8 lanes.

1.2 Revision 4.0Updated changes related to CoreJESD204BTX v3.0.



1.5 Revision 1.0Revision 1.0 was the first publication of this document. Created for CoreJESD204BTX v2.0.

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 JESD204BTX Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2.1 Alignment Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2.2 ILA Sequence Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2.3 SYNC Signal Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2.4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2.5 8B10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2.6 TX Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2.7 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Core Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Supported Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6 Device Utilization and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1 Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 JESD204B Sub-classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.1 Sub-class 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.2 Sub-class 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.3 Sub-class 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 SERDES Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.1 Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.1 License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1.1 RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2 SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3 Configuring CoreJESD204BTX in SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.4 Simulation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.5 Synthesis in Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6 Place-and-Route in Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.1 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Revision 5 4

7.3 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.4 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.5 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5.1 Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5.2 My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5.3 Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Revision 5 5

Revision 5 6

Figures

Figure 1 CoreJESD204BTX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 2 Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 3 CoreJESD204BTX I/O Signal Diagram (4 lanes) with Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 4 CoreJESD204BTX I/O Signal Diagram (4 lanes) without Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 5 CoreJESD204BTX Full I/O View (4 lanes) with Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 6 CoreJESD204BTX Full I/O View (4 lanes) without Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 7 CoreJESD204BTX SmartDesign Configuration GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 8 CoreJESD204BTX User Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Revision 5 7

Tables

Table 1 CoreJESD204BTX Utilization for Data Width 16 With Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 2 CoreJESD204BTX Utilization for Data Width 32 With Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 3 CoreJESD204BTX Utilization for Data Width 64 With Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 4 CoreJESD204BTX Utilization for Data Width 16 Without Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 5 CoreJESD204BTX Utilization for Data Width 32 Without Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 6 CoreJESD204BTX Utilization for Data Width 64 Without Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 7 CoreJESD204BTX Parameters and Generics Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 8 CoreJESD204BTX I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Introduction

2 Introduction

2.1 OverviewCoreJESD204BTX is the transmitter interface of the JEDEC JESD204B standard. This specificationdescribes a high speed serial interface for data converters.

Figure 1 shows the CoreJESD204BTX block diagram of a single lane.

Figure 1 • CoreJESD204BTX Block Diagram

2.2 JESD204BTX BlocksCoreJESD204BTX consists of the blocks described below:

2.2.1 Alignment Character GeneratorThis block generates the alignment characters and frame position signals.

During a synchronization request this block generates the K28.5 (/K/) characters used during code groupsynchronization (CGS) state. The receiver device aligns its bit boundaries to these /K/ characters andwhen it detects four or more consecutive /K/ characters it will no longer request synchronization. AfterCGS this block monitors the frame position and asserts the SOF and SOMF outputs to indicate when theframe is at the start of a frame or multi-frame.

After the Initial Lane Alignment (ILA) sequence frame alignment is monitored via alignment characters.The Alignment Character Generator (ACG) replaces octets under certain conditions at the end for aframe with these alignment characters. The alignment character K28.7 (/F/) is used to mark end-of-frameand the alignment character K28.3 (/A/) is used to mark end-of-multi-frame. When the receiver devicedetects one of these alignment characters it reconstructs the octet back into its original value, thereforeno extra bandwidth is required for frame alignment. Replacement characters are generated based on theconfiguration of scrambling as enabled (SCR=1) or disabled (SCR=0). When scrambling is disabled ACGreplaces the user data with an alignment character when the last octet in the current frame equals thelast octet in the previous frame, but only if character replacement did not occur in the previous frame or ifthe current frame is the end of a multi-frame. When scrambling is enabled ACG replaces the user datawith the alignment character /F/ when the last scrambled octet in the current frame equals 0xFC but onlyif the character replacement did not occur in the previous frame and it is not the end of a multi-frame. Ifthe last scrambled octet of the current frame equals 0x7C and is the end of a multi-frame the user data isreplaced with the alignment character /A/ and will make this replacement even if character replacementoccurred in the previous frame.

Note: Refer to section 5.3.3.4 of the JESD204B.01 specifications for more details.

Single Lane

TX Controller Initial Lane Alignment Sequence Generator

Alignment Character Generator

Scrambler

8B10B Encoding

SYNC Signal

Decoding

Clock Generator

MUX

To SERDES

From DAC

To/From DAC

User Data

Revision 5 8

Introduction

2.2.2 ILA Sequence GeneratorThis block generates the initial lane alignment (ILA) sequence.

The first control symbol of every multi-frame in the ILA sequence is K28.0 (/R/) which indicates the startof the subsequence. The last control symbol of every frame in the ILA is /A/ which indicates the end ofmulti-frame. The receiver lane(s) align to the first /R/ symbol during initialization. The second frame of themulti-frame has the link configuration data. The control symbol K28.4 (/Q/) indicates that the next octet isthe start of the link configuration data. The parameters in the link configuration data are used to indicateto the receiver device how the transmitter is configured. The parameter 'L' is set by lane number. Forsubclass 2 the adjustment information is calculated and send in PHADJ, ADJDIR and ADJCNTparameters of the link configuration data. Although the JESD204B.01 specification indicates that thechecksum (FCHK) in the link configuration mapping is the sum of all the fields and not the sum of all theoctets created by the mapping some data convertor manufactures have the checksum as the sum of allthe octets. To cover both checksum types the parameter/generic FIELD_OCTET can select which type ofchecksum to calculate.

When the SYNC Signal Decoding block detects a synchronization request the Alignment CharacterGenerator block will transmit a stream of consecutive K28.5 (/K/) characters until the synchronizationrequest has been completed and the TX Controller is ready to send the ILA sequence. When thesynchronization request has been completed the TX Controller will start the ILA sequence at the start ofthe next frame clock boundary for subclass 0 and at the start of the next LMFC boundary for subclasses1&2. This control over the ILA sequence is used for lane alignment and the receiver device uses thisinformation to align its lanes. Since subclasses 1&2 start the ILA sequence at the start of the next LMFCboundary only the four multi-frames in the ILA sequence are required to align the receiver device lanes.However, since Subclass 0 starts the ILA sequence at the start of the next frame clock boundaryadditional alignment frames may be required for lane alignment. The parameter/generic ILA_MFSindicates the number of multi-frames in the ILA sequence (default is 4). If any addition, alignment framesare required this parameter can be configured up to 256. The additional alignment frames will havecontrol characters K28.7 (/F/) at the end of each frame and K28.3 (/A/) control characters at the end ofeach multi-frame.

Note: Refer to 5.3.3.5, 8.2 and 8.3 of the JESD204B.01 specifications for details.

2.2.3 SYNC Signal DecodingThis block controls the sync request by decoding the SYNC_N signal.

At reset or power-on the transmitter goes through initialization and synchronization request is sent to theTX Controller. TX Controller will instruct the Alignment Character Generator to transmit K28.5 (/K/)characters during a synchronization request. When SYNC_N de-asserts the synchronization request iscomplete, but transmission of /K/ characters will continue to the start of the next frame clock boundary forsubclass 0 and to the start of the next LMFC boundary for subclasses: 1 and 2. If SYNC_N is asserted foranother 4 consecutive rising edge of the frame clock a re-initialization request is triggered and the sameprocess as above is executed.

Note: Refer to section 8.4 of the JESD204B.01 specifications for details on SYNC signal decoding.

2.2.4 Clock GeneratorThis block generates the internal LMFC and frame clock. When subclass 1 is selected it also generatesSYSREF_OUT output and monitors SYSREF_IN input for deterministic latency.

Note: More information can be found in the JESD204B.01 specifications. See Annexure G for clock generation information and section 6 for deterministic latency.

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Introduction

2.2.5 8B10B EncoderThis block encodes data using 8B10B encoding techniques. The ENCODER_EN parameter is used toenable or disable the 8B10B encoder, fourth generation families require it to be enabled while PolarFirerequires it to be disabled since this family of devices has a hard 8B10B encoder in the transceiver block.

The 8B10B encoder is a marriage of two sub-blocks, the 5b6b and the 3b4b encoders. It provides DC-balance, bounded disparity and clock recovery for the receiver. The purpose of the encoders is to convert8-bit data into a 10-bit code. The 10-bit code contains an equal number of 0’s and 1’s. In addition, thecode is built so that no more than five consecutive 0’s or 1’s is ever transmitted, if the parameter/genericSERDES_MODE is set to 1 each lane has a 20-bit output, which will have two 10-bit codes. IfSERDES_MODE is set to 2 each lane has a 10-bit output, which will have one 10-bit.

2.2.6 TX ControllerThis block controls the triggering of the ILA sequence, generation of alignment characters, and the datapresented to the 8B10B encoder.

During a synchronization request this block will control the Alignment Character Generator (ACG) and itwill transmit a stream of continuous K28.5 /K/ characters. The ACG data path is selected on the MUXand goes through to the 8B10B Encoder. The minimum generation of /K/ symbols is 1 frame and 9octets. Once the receiver device aligns its bit boundaries to these /K/ characters the synchronizationrequest will de-assert (that is, SYNC_N goes HIGH). Then this block will control the ILA SequenceGenerator and trigger the ILA sequence at the start of the next frame clock boundary for subclass 0 andto the start of the next LMFC boundary for subclasses 1 and 2. The ILA Sequence Generator data path isselected on the MUX and goes through to the 8B10B Encoder. When the ILA sequence has complete theILA Sequence Generator informs this block and now user data can be transmitted so the data pathchanges the back to the ACG data.

This block also controls the character replacement. The behavior of the character replacement dependson if scrambling is enabled or disabled and is described below.

When scrambling is disabled, when the last octet in the current frame, not coinciding with the end of amulti-frame, equals the last octet in the previous frame, the transmitter will replace the current last octetand encode it as control character K28.7 (/F/). However, if an alignment character was alreadytransmitted in the previous frame, the original octet will be encoded. When the last octet in the currentframe at the end of a multi-frame equals the last octet in the previous frame, the transmitter will replacethe current last octet and encode it as control character K28.3 (/A/), even if a control character wasalready transmitted in the previous frame.

When scrambling is enabled, when the last scrambled octet in a frame, but not at the end of a multi-frame, equals 0xFC, the transmitter will encode it as a control character /F/. When the last scrambledoctet in a multi-frame equals 0x7C, the transmitter will encode it as a control character /A/.

Note: Refer to section 8.1 of the JESD204B.01 specifications for details.

2.2.7 ScramblerThis block scrambles data based on the polynomial 1 + x14 + x15.

Scrambling is enabled by setting parameter/generic SCR to 1. Scrambling must only be enabled if thereceiver has descrambling enabled or the receiver can enable scrambling based on the link configurationparameters in the ILA sequence. Scrambling of data is used to avoid electromagnetic compatibility andinterface problems in sensitive application. Spectral peaks are produced when the same data pattern isrepeated over a period of time. This polynomial offers a period of 32,767 which is long enough to meetthe spectral requirements of sensitive application. The scrambler is self-synchronous and also allows thedescrambler in the receiver to synchronize within two octets. The reason scrambling is optional isbecause the digital operations of the interface cause switching noise which makes scrambling adisadvantage for some applications. Switching noise causes current spikes which cause sensitiveanalogue portions of the design to degrade or even malfunction.

More information can be found in the JESD204B.01 specifications. Refer to section 5.2 for informationabout scrambling and view Figure D.4 for the scrambler implementation.

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Introduction

2.3 FeaturesCoreJESD204BTX implements the transmitter interface of the JESD204B standard and has the followingfeatures:

• Supports 1 to 8 lanes• Performs user-enabled scrambling• Generates an initial lane alignment sequence• Performs alignment character generation• Sources link configuration data with user selected parameter values during initial lane

synchronization sequence• Performs the alignment character generation• Performs user-enabled 8B10B encoding• Supports Subclasses 0, 1, and 2• Internal clock generation• Sync~ signal decoding• Supports data width of 16, 32, or 64 bitsNote: Octet to Frame Stream conversion is not performed by the core.

2.4 Core VersionThis handbook is for CoreJESD204BTX version 3.0.

2.5 Supported Families• PolarFire• RTG4™• SmartFusion®2• IGLOO®2

2.6 Device Utilization and PerformanceCoreJESD204BTX has been implemented in the following Microsemi device families. A summary of theimplementation data for CoreJESD204BTX is provided in Table 1.

Note: Data in this table were achieved using synthesis and layout settings optimized from speed. The following parameters/generics were set: L=3, F=256, K=4,ENCODER_EN = 1 & D_WIDTH=16.

Table 1 • CoreJESD204BTX Utilization for Data Width 16 With Encoder

Family

Tiles Utilization

Performance (MHz)Sequential Combinatorial Total Device Total %

RTG4 1749 1988 3737 RT4G150 2.46 178

SmartFusion2 1867 2015 3882 M2S150T 2.66 247

IGLOO2 1867 2015 3882 M2GL150T 2.66 247

PolarFire 1868 1982 3851 PA5M500 0.7 273

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Introduction

Note: Data in this table were achieved using default synthesis and layout settings. The following parameters/generics were set: L=3, F=256, K=4, ENCODER_EN = 1 & D_WIDTH=32.






Family

Tiles Utilization


RTG4 3239 3458 6697 RT4G150 4.41 144

SmartFusion2 3394 3517 6911 M2S150T 4.73 200

IGLOO2 3394 3517 6911 M2GL150T 4.73 200

PolarFire 3396 3509 6905 PA5M500 1.24 273


Family

Tiles Utilization


RTG4 6120 6129 12249 RT4G150 8.07 77

SmartFusion2 6450 7226 13676 M2S150T 9.36 163

IGLOO2 6450 7226 13676 M2GL150T 9.36 163

PolarFire 6843 7388 14231 PA5M500 2.56 217

Table 4 • CoreJESD204BTX Utilization for Data Width 16 Without Encoder

Family

Tiles Utilization Performance (MHz)Sequential Combinatorial Total Device Total %

PolarFire 953 1085 2038 PA5M500 0.37 321


Family

Tiles Utilization


PolarFire 1535 1680 3215 PA5M500 0.58 262


Family

Tiles Utilization


PolarFire 3090 3604 6694 PA5M500 1.11 207

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Functional Description

3 Functional Description

CoreJESD204BTX, shown in Figure 2, consists of optional scrambling, ILA sequence/alignmentcharacter generation, SYNC_N signal decoding, optimal 8B10B encoding, and clock generation.

3.1 Data Link LayerCoreJESD204BTX implements the JEDEC JESD204B transmitter interface.

Figure 2 • Data Link Layer

Figure 2 shows the data link layer of CoreJESD204BTX. Code Group Synchronization (CGS) is triggeredwhen the receiver issues a synchronization request via the synchronization interface. During asynchronization request the transmitter emits a continuous stream of K28.5 (/K/) control symbols. Thereceive will then align its bit boundaries to this symbol and will deactivate the synchronization requestwhen it receives at least four successive /K/ symbols. Then the Initial Lane Alignment (ILA) sequence istransmitted. The first control symbol of every multi-frame in the ILA sequence is K28.0 (/R/) whichindicates start of the subsequence.

The last control symbol of every frame in the ILA is K28.3 (/A/) which indicates the end of multi-frame.The receiver lane(s) align to the symbol during initialization. The second frame of the multi-frame has thelink configuration data. The control symbol K28.4 (/Q/) indicates that the next octet is the start of the linkconfiguration data. The receiver compares its parameters to the parameters received in the linkconfiguration data or configure it to these values. Subclass 0 support addition, alignment frames, if moreframes are required for alignment. The additional alignment frames will have K28.7 (/F/) symbols at theend of the frame and /A/ symbols at the end of multi-frame. After alignment completes the user data canbe transmitted.

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Functional Description

3.2 JESD204B Sub-classesCoreJESD204BTX supports sub-class 0, 1, and 2. A summary of each subclass is given below.

3.2.1 Sub-class 0Sub-class 0 allows the device to be backward compatible with the JESD204A standard. It offers nosupport for deterministic latency.

3.2.2 Sub-class 1Subclass 1 offers support for deterministic latency using SYSREF signaling.

During a synchronization request SYSREF_OUT will only assert at the start of a LMFC period and whenSYNC_N is asserted. The assertion of SYSREF_OUT indicates to the receiver when the start of a LMFCperiod occurs. The receiver has the option to shift the phase of its internal clocks based onSYSREF_OUT assertion. The minimum duration SYSREF_OUT will assert for is a quarter of a LMFCperiod.

The assertion of SYSREF_IN input indicates the start of a LMFC period in the transmitter. During asynchronization request the receiver asserts SYNC_N and when SYSREF_IN asserts it will cause LMFCand frame clock to phase shift to sync to the receivers LMFC period for deterministic latency support.When SYNC_N is de-asserted any assertion of SYSREF_IN will be ignored so that the LMFC and frameclock positions are locked.

3.2.3 Sub-class 2Sub-class 2 is similar to sub-class 1 except it offers support for deterministic latency using SYNC~sampling.

The de-assertion of SYNC_N is synchronous to the internal frame clock and will only occur at the LMFCboundary. This control means that the LMFC phase information is sent to the transmitter device throughthe SYNC interface. The de-asserts of SYNC_N relative to its LMFC and the correction information shallbe contained in PHADJ, ADJDIR and ADJCNT parameters on the link configuration data. Theadjustment resolution is set to 1 clock tick (that is, two octets) in the transmitter and is stored in ADJCNT.When PHADJ is set (= 1) a phase adjust has been requested by the transmitter. ADJDIR value indicatesan advance (= 0) or delay (= 1) adjustment. Since The receiver device has the option to makeadjustments based on the adjustment information received in the link configuration data. If the receiver isa logic device, there are no requirements to adjust the LMFC phase, but if the receiver is a convertordevice, it shall be able to adjust its LMFC phase when PHADJ is set (=1) and will make the adjustmentsbased of the information in ADJDIR and ADJCNT.

Note: More information about deterministic latency can be found in section 6 of the JESD204B.01 specifications.

3.3 SERDES InterfaceFor fourth generation family devices CoreJESD204BTX will be connected to the transmitter lanes of theSERDES interface macro. The SERDES interface will be in EPCS mode because this macro will be usedas a standalone SERDES. EPCS mode has two default data rates: 1.25 Gbps and 2.5 Gbps per lane.This means 10 Gbps can easily be achieved across the 4 lanes of CoreJESD204BTX. The SERDESinterface can be reconfigured through the APB interface to allow EPCS mode to achieve higher datarates.

For PolarFire family devices the SERDES has a hardened 8B10B encoder which meansCoreJESD204BTX can be configured with its encoder removed (that is, ENCODER_EN = 0).CoreJESD204BTX will connect to the 8B10B interface on the SERDES. The PolarFire SERDES can beconfigured up to 64bit data width (8 octets) and CoreJESD204BTX supports this data width which meansup to 12.5Gbps data rate is achievable per lane.

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Interface

4 Interface

4.1 Configuration ParametersCoreJESD204BTX has parameters (Verilog) or generics (VHDL) for configuring the RTL code, described in Table 7. All parameters and generics are integer types.

Table 7 • CoreJESD204BTX Parameters and Generics Descriptions

Name Range Default Value Description

CF 0 to 32 0 Number of control words per frame clock period per link. CF== L shall always be encoded as 31: control words on all lanes. CF==31 can only occur when L==31

CS 0 to 3 0 Number of control bits per sample

F 2 to 256 2 Number of octets per frame

HD 0 to 1 0 High density format

JESDV 0, 1 1 JESD204 version

0: JESD204A

1: JESD204B

K 4 to 32 9 Number of frames per multi-frame

L 0 to 7 0 Number of lanes per converter device (link)

Note: L+1= No. of lanes

M 1 to 256 1 Number of converters per device

N 1 to 32 16 Converter resolution

N’ 1 to 32 16 Total number of bits per sample

S 1 to 32 2 Number of samples per converter per frame cycle

SCR 0 to 1 1 Scrambling enabled

SUBCLASSV 0 to 2 0 Device subclass version

0: Subclass 0

1: Subclass 1

2: Subclass 2

ILA_MFS 4 to 256 4 Initial lane alignment, multi-frame size. Minimum size is 4; however, more frames may be needed for the receive to align its lane(s).

FIELD_OCTET 0 to 1 1 Configuration Options parameter which selects how the FCHK (checksum) of the link configuration parameters will be calculated

0: Field addition 1: Octet addition

SERDES_MODE 1 to 2 1 Configuration Options parameter which selects the width of the input data1 : ((D_WIDTH/8) * 10)2 : 10bit (when ENCODER_EN = 1), : 8bit (when ENCODER_EN = 0)

Note: When SERDES_MODE=2 LANE_CLK is a slower frequency than EPCS Tx Clock.

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Interface

Note: A multiframe is defined as a group of K successive frames, which are made up of F successive octets, where K is valid from 4 to 32 and F is valid from 2 and 256, such that the number of octets per multiframe is between 18 and 1024.

4.2 I/O SignalsThe port signals for the CoreJESD204BTX macro are shown in Figure 3 and Figure 4.

Figure 3 • CoreJESD204BTX I/O Signal Diagram (4 lanes) with Encoder

Figure 4 • CoreJESD204BTX I/O Signal Diagram (4 lanes) without Encoder

D_WIDTH 16, 32, or 64

16 Configuration Options parameter which selects the user data width.0 : 16bit (2 octet)1 : 32bit (4 octet)2 : 64bit (8 octet)

ENCODER_EN 0 to 1 1 Configuration Options parameter which includes or removes the encoder from the core.0 : Removed1 : Included

Table 7 • CoreJESD204BTX Parameters and Generics Descriptions

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Interface

Table 8 • CoreJESD204BTX I/O Signal Descriptions

Name Width Direction Description

RESET_N 1 In This active low reset will reset the core to its initial state.

External PCS Transmitter Interface

EPCS_[n]_TX_CLK 1 In This is the clock for lane [n].

Note: [n] = 0 to 7

EPCS_[n]_TX_DATA 10, ((D_WIDTH/8)*10) Out EPCS transmitter channel [n] data. This output should match with the width of the EPCS receiver channel on the SERDES.

If SERDES_MODE = 2 then Width = 10If SERDES_MODE = 1 then Width = (D_WIDTH/8)*10When ENCODER_EN=0 this signal is tied low.

Note: [n] = 0 to 7

8B10B Encoder Interface

TX_DATA_[n] 8, D_WIDTH Out 8b10b data for channel 0 data. This output should match with the width of the 8b10b encoder on the SERDES.

If SERDES_MODE = 2 then Width = 8If SERDES_MODE = 1 then Width = D_WIDTHWhen ENCODER_EN=1 this signal is tied low.

Note: [n] = 0 to 7

TX_K_[n] 1, (D_WIDTH/8) Out 8b10b K control for channel 0 data.

If SERDES_MODE = 2 then Width = 1If SERDES_MODE = 1 then Width = D_WIDTH/8When ENCODER_EN=1 this signal is tied low.

Note: [n] = 0 to 7

JESD204B Tx Interface

DATA_IN_[n] D_WIDTH In This is the input data to be transmitted on lane [n].

Note: [n] = 0 to 7

SYSREF_IN 1 In This is the sysref input signal used by JESD204B subclass 1.

SYSREF_OUT 1 Out This is the sysref output signal generated from inside the core. This or an external sysref signal is tied to SYSREF of the receiver or it can be used to loopback into the SYSREF_IN of the transmitter on a number of factors. (Subclass 1 only).

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Interface

Note: Different combinations of these IO's will be exposed depending on ENCODER_EN value.

LANE_CLK 1 In This is the clock all lanes will sync to internally in the IP core. Only when parameter/generic SERDES_MODE = 2 is when it differs from EPCS_*_TX_CLK.When SERDES_MODE = 2, EPCS_*_TX_CLK to LANE_CLK ratio's are as follows.2:1 when D_WIDTH = 16bit4:1 when D_WIDTH = 32bit8:1 when D_WIDTH = 64bitWhen SERDES_MODE = 1, EPCS_*_TX_CLK to LANE_CLK ratio is 1:1

SYNC_N 1 In When asserted, the transmitter goes into its initial state and will start the ILA sequence.

Note: The "_N" in the name represents active low and not the negative of a differential. When connecting to a differential input this signal must be connected to the positive rail on to the Y output of a INBUF_DIFF macro.

TX_STATE 2 Out Monitors the current state of the transmitter.

SYNC_STINIT_LANE_STDATA_ENC_STInvalid state

SOF (D_WIDTH/8) Out Monitors when start-of-frame occurs on all lanes.

SOMF (D_WIDTH/8( Out Monitors when start-of-multi-frame occurs on all lanes.

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Tool Flow

5 Tool Flow

5.1 LicenseCoreJESD204BTX is license free.

5.1.1 RTLComplete register transfer level (RTL) source code is provided for the core and testbenches.

5.2 SmartDesignCoreJESD204BTX is pre-installed in the SmartDesign IP deployment design environment.

The core should be configured using the configuration GUI within the SmartDesign tool, as shown inFigure 7. For information on using SmartDesign to instantiate and generate cores, refer to the LiberoSoC Online Help for instructions on obtaining IP documentation.

Figure 5 • CoreJESD204BTX Full I/O View (4 lanes) with Encoder

Figure 6 • CoreJESD204BTX Full I/O View (4 lanes) without Encoder

CoreJESD204BTx is license locked with a RTL license.

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http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=132044

http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=132044

Tool Flow

5.3 Configuring CoreJESD204BTX in SmartDesignThe core can be configured using the configuration GUI within SmartDesign. An example of the GUI forthe SmartFusion2 family is shown in Figure 7.

Figure 7 • CoreJESD204BTX SmartDesign Configuration GUI

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Tool Flow

5.4 Simulation FlowsThe User Testbench for CoreJESD204BTX is included in all releases.

To run simulations, select the User Testbench flow within the SmartDesign CoreJESD204BTXconfiguration GUI, right-click the canvas, and select Generate Design.

When SmartDesign generates the design files, it installs the user testbench files.

To run the user testbench, set the design root to the CoreJESD204BTX instantiation in the Libero SoCdesign hierarchy pane and click Simulation in the Libero SoC Design Flow window. This invokesModelSim® and automatically runs the simulation.

5.5 Synthesis in LiberoAfter setting the design root appropriately for your design, click Synthesis in the Libero SoC software.The Synthesis window appears, displaying the Synplicity® project. Set Synplicity to VHDL 2008standard if VHDL is being used. To run Synthesis, click Run.

5.6 Place-and-Route in LiberoAfter setting the design root appropriately for your design, and running Synthesis, click Layout in theLibero SoC software to invoke Designer. CoreJESD204BTX requires no special place-and-routesettings.

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Testbench

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6 Testbench

CoreJESD204BTX user testbench gives an example of how to use the core.

Figure 8 • CoreJESD204BTX User Testbench

The simulation testbench shown in Figure 8 includes an instantiation of the CoreJESD204BTX macro,data generation, data monitor, and checker. Because the data on the output of the CoreJESD204BTXcore is 8B10B encoded and scrambled, the user testbench is only used to test the core in a fixedconfiguration for each sub-class. The purpose of the testbench is to test the functionality of the core byinputting known data, monitoring the output, and checking for expected results.

User Testbench

Data Generator

(UUT)CoreJESD204BTX Monitor Checker

Product Support

7 Product Support

Microsemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.

7.1 Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.

From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913

7.2 Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.

7.3 Technical SupportFor Microsemi SoC Products Support, visit http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.

7.4 WebsiteYou can browse a variety of technical and non-technical information on the Microsemi SoC ProductsGroup home page, at http://www.microsemi.com/products/fpga-soc/fpga-and-soc.

7.5 Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.

7.5.1 EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.

The technical support email address is [email protected].

7.5.2 My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to MyCases.

7.5.3 Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email([email protected]) or contact a local sales office. Visit About Us for sales office listings andcorporate contacts.

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http://www.microsemi.com/soc/mycases/

http://www.microsemi.com/soc/mycases/



http://www.microsemi.com/salescontacts


Product Support

7.6 ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in ArmsRegulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yesin the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR webpage.

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hb0400: corejesd204btx v3.0 handbook - fpga & …2. this control over the ila sequence is used...

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