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respective owners. © 2013 Freescale Semiconductor, Inc.

Confidential and Proprietary

Aashish Sharma(FSL)

Akhil Arora (CDNS)

Amitav Halder(FSL)

Arun Jain(FSL)

18th Oct 2013

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG,

PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor,

Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready

Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their


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MSIE Introduction Requirement

Solution

Flow

MSIE Configurations Incremental-Instantiates-Primary Mode

Primary-Instantiates-Incremental Mode

Parallel Instantiation Mode

MSIE Implementation Guidelines Sharable snapshot libraries

Defparams, Macros, Hrefs , SDF annotation

Results for RTL & GLS Simulation

Advantages

Limitations

Scope for future work

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Snapshot

Library

.pak library

database file

Compilation

of source code

Elaboration To generate the

snapshot

Simulation

10% 40%

50%

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Elaboration: It is the step which creates the simulatable model

of the complete design and testbench environment called Snapshot

Snapshot Is optimized monolithic view of the design

Contains all hierarchy

Contains all collapsed networks as well as information to get

uncollapsed information (for driver tracing, pli access, etc)

Contains binding information

Contains the timing information

Contains process state information for all processes in the

model

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As the complexity and size of the SoCs increases, the elaboration time

also goes up

Minor change in the snapshot requires re-elaboration of complete

environment, which is significant time

Productivity barrier for test developers

Productivity barrier for SoC integrators

There is a need to reduce the re-build time to increase the productivity

and efficiency

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Cadence® Incisive simulator provides – Multi-snapshot

Incremental Elaboration (MSIE)

Creates pre-elaborated, primary snapshot Primary snapshot has the part of the design which is stable and is

not expected to change very often.

Frequently changing part which is expected to be the smaller

portion of complete environment, is elaborated as Incremental

snapshot. Incremental snapshot is passed to the simulator

It is combined with the primary snapshot(s) for execution

Rebuilds is extremely fast when change happens to incremental

portion of the code

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Traditional Way

of

Running a Testcase

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Compilation

of source code

Elaboration To generate the

snapshot Simulation

10% 40%

50%

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New Way of Running a

Testcase using MSIE

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Compile source files

for stable

portion[DUT] of the

design

Elaborate once to

create Primary

snapshot

Primary Snapshot

Compile source files

for changing

portion[TB] of the

design

Elaborate to

create Incremental

snapshot

Incremental

Snapshot

Specify the incremental

snapshot for simulation

FIRST RUN

SECOND RUN

Saving of

~50% Time

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Incremental-Instantiates-Primary Mode

Primary-Instantiates-Incremental Mode

Parallel Instantiation Mode

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Testbench

module tb_top();

module test (

<interface ports>

);

Packages

Interfaces

DUT

DUT is in primary partition

The testbench is in the incremental partition.

Primary partition is instantiated within the incremental partition.

IRUN Commands

% irun –mkprimsnap -name DUT

% irun tb_top.v –primname DUT

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The primary partition includes the top level of the testbench The primary partition contains an unconnected instantiation. The incremental partition contains the missing instance.

Primary Partition

DUT

Testbench

module tb_top();

Packages

Interfaces

IRUN Command

% irun tb_top.v –mkprimsnap -name tb_top

-incrtop test

% irun test.v -primname tb_top

Incremental Partition

module test (

interface ports);

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Neither partition is instantiated within the other. The primary partition contains the top level of the design The incremental partition contains another top-level module or package.

Primary Partition

DUT

Packages

Incremental

Partition

Test controller

module test();

Testbench

module tb_top();

Using IRUN

% irun tb_top.v -mkprimsnap -name tb_top

% irun test.v -primname tb_top

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Incremental instantiates primary configuration used

Primary Snapshot (Dut_Top) is fixed and is re-elaborated only when there is

change in DUT RTL/configuration

Testbench is the Incremental part and can be re-elaborated without the

elaboration of DUT thus resulting in Elab time saving

DUT

VIP_1

MONITOR

TESTBENCH

VIP_4 VIP_2

VIP_3

Primary Snapshot Incremental Snapshot

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By default both snapshots, primary and incremental are generated in same

library (*.pak file)

To enable multiple users to share the primary snapshot, create Separate

libraries for the primary and incremental snapshots

Every user maintains his own incremental snapshot

Also reduces the disk space requirement per user

If required incremental can also be shared (users can share snapshot

to run simulations by changing the runtime arguments).

DUT

source

code

TB source

code

Primary

snap

Library

Incremental

snap library

Simulation of

combined

snapshot

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Overriding DUT parameters in TB

Parameter values are resolved at elaboration phase

Primary snapshot is elaborated before incremental, thus defparam

statements in TB cannot override the DUT params.

Pass all the defparam statements at primary elaboration

Either as part of source code

Or from tool command line

Macros/Compiler directive used in primary snapshot should

be visible during primary compilation

If defined in incremental portion, pass these macros on the command

line during primary snapshot generation

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Handling external references

Referred to as hrefs in MSIE (sometimes referred to colloquially as

OOMRs)

Hrefs from incremental to primary partition require special access

permissions at the time of primary snapshot generation

Autohref.txt file created during incremental build if missing hrefs

-genhref flow allows href file to be created without full elaboration; use

this for primary generation

-genhref should be first step before primary and incremental snapshot

generation

TB

DUT Block 1 DUT Block n

reg a;

VE

Incremental on Top

assign test.dut_n.u3.a = x;

-href “@dut.u3.a W”

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Annotating SDF

$sdf_annotate task is being used in TB to annotate timing to the DUT

$sdf_annotate("../Sdf_Files/dut.sdf“ , testbench.top ,,,"MAXIMUM");

SDF annotation can’t cross partition boundaries because annotation

happens at elab time of primary snapshot(DUT)

Call $sdf_annotate in the primary partition

Dut_top is the top level of primary

Change the scope in $sdf_annotate task

$sdf_annotate("../Sdf_Files/dut.sdf“ , Dut_top ,,,"MAXIMUM");

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MSIE was deployed on a SoC in AISG group

Steps Time ( in sec)

Traditional Incremental

NcVLog 107.1 22.6

NcElab 361.0 57.6

NcSim 218.2 287.1

Total 686.3 367.3

Time ( in sec) Memory

Usage

NcVLog 43.7 320.4M

NcElab 337.4 2338.6M

NcSim --- ---

Memory Usage ( in M)

Traditional Incremental

569.9 366.8

2794.7 2329.2

2607.2 2678.1

Primary

Elaboration

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Re-elaboration time of the incremental portion as compared to the

complete SoC env is significantly less

Elaboration time saving : 6.26x

MSIE affects the simulation time due to

The stitching of the snapshots which happens at zero simulation time

Hrefs used in the incremental portion

Overall gain achieved for the complete re-elab + simulation cycle :

1.87x

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Steps Time ( in sec) Memory Usage ( in M)

Traditional Incremental Traditional Incremental

NcVLog 143.7 21.1 631.3 431.1

NcElab 1119.82 205.8 10147.7 8961

NcSim 818.3 950.6 9222.8 9264.2

Total 2081.8 1177.5

Memory Usage Time (in sec)

NcVLog 498.1M 135.5

NcElab 9833.1M 957.8

NcSim --- ---

Primary

Elaboration

Elaboration time saving : 5.44x

Overall gain achieved for the complete re-elab + simulation cycle :1.76x

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Significant time saving in the re-elaboration of the

verification env

Reduction in debug cycle time

Primary snapshot of the DUT can be shared between

multiple users

Disk space saving since multiple user just needs to

maintain only the smaller incremental snapshot

Overall increase in the efficiency and productivity as the

complete compile+elab+simualtion cycle time shortens

due to saving in re-elab time

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Low Power simulations are not supported

Will be supported by Q2 2014

Addition of hrefs in the incremental partition

requires re-elab of both primary and incremental

partition

This becomes more challenging in case of multiple users

adding hrefs in TB when sharing the same primary

snapshot

Tran network connections across the partitions are

not supported

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• Verification cycle is always a long-pole for entire design

cycle

− Debugging and Re-running of testcases is the most frequent

activities

− This solution targets to minimize the duration of verification

cycle

Divide & Conquer

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Use multiple primary snapshot for the

emulation device configuration

Target to reduce the incremental portion in

the env, by bringing the VIP and other UVM

infrastructure into the primary partition

This should further reduce the re-elab time

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