FPGA Implementation of Embedded Controller for IC EngineMTP Presentation by R.A.S.Jagadish (05323001)Under Guidance of

Prof. Kavi Arya and Prof. Shashikanth SuryanarayananIDP in System and Control Engineering IIT Bombay, India July 20071

Outlinez z z z z z z

Introduction Problem Statement Theory Experimental Work Results and Conclusion Future Work References2

What is Embedded System?z

Embedded system composed of Hardware and Software components are designed to interact with a physical environment in real-time in order to fulfill control objectives and design specifications.

z

A system designed to perform a single well defined function life-long.3

ControllerzController

is a mechanism that interacts with part of the world (the

plant) by measuring certain variables and exerting some influence in order to steer it toward desirable states. Timing Diagram

The execution of a control program with a period T 4

Engine Controller Unitz The

ECU is essentially a control device that given information about the status of an engine can determine what to do and when to do it.

5

Engine Sensors and Actuators:Inputs to the System M.A.P Crank Shaft Diaphragm-based Manifold Air Pressure sensor Variable Reluctance ( Inductive Coupling) sensor

Outputs of system Spark Ignition Driver Fuel Injection driver To give the signal to ignition driver relative to the crank position To give the signal to fuel injection driver relative to the crank position6

Problemsz z z z

z z

Identify 45 BTDC from crank position sensor using Hardware Calculation of Engine Speed (RPM) Spark Advance Table (Using interpolator) Ignition Time Calculation (Ignition Driver) Fault detection Operate in Synchrony7

Block Diagram of EMSManifold Air Pressure (MAP) Sensor

Fuel Injector

IC EngineCrank Position Sensor Spark Ignition Driver

FPGA Boardwith ADC/DAC

Fuel Pump

DRIVER INPUT (On/Off) 8

Digital Controller (2nd order)b0 + b1 z 1 + b2 z 2 Y ( z ) C ( z) = = 1 2 1 + a1 z + a2 z X ( z)

Y ( z )(1 + a1 z 1 + a2 z 2 ) = X ( z )(b0 + b1 z 1 + b2 z 2 ) y (n) = a1 y (n 1) a2 y (n 2) + b0 x(n) + b1 x(n 1) + b2 x(n 2)

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Implementation of Discrete time Controller

b0 + b1 z + ... Y ( z) C ( z) = = 1 2 1 a1 z a2 z ... U ( z ) Y ( z )(1 a1 z 1 a2 z 2 ...) = U ( z )(b0u (k ) + b1 z 1 + ...) y (k ) = a1 y (k 1) + a2 y (k 2) + ... + b0u (k ) + b1u (k 1) + ...Algorithm : 1.Read u(k) 2.Calculate y(k) = bo*u(k) + history 3.Output y(k) 4.Calculate history for the next cycle

1

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What is FPGAz

The innovative development of FPGAs whose configuration could be re-programmed an unlimited number of times

z

a new field in which many different hardware algorithms could execute

z

on a single device, just as many different software algorithms can run on a conventional processor.

z

The speed advantage of direct hardware execution on the FPGA routinely 10X to 100X the equivalent software algorithm

z

FPGA can be configured to contain exactly and only those operations that appear in the algorithm.

FPGA Architecture

P RO GRAM M ABLE IN T ERCO N N E CT

I/O BLO CK

C O N F IG U R A B LE LO G IC B LO CK ( CLB) So u r c e : X ilin x

Field Programmable Gate Array (FPGA) devices feature a reconfigurable digital circuit architecture with a matrix of Configurable Logic Blocks (CLBs) surrounded by a periphery of I/O Blocks. Signals can be routed within the FPGA matrix in any arbitrary manner by Programmable Interconnect switches and wire routes.

Using a Von-Neumann M/C for Computing 1. Algorithmic Description : Using High level programming Languages 2. Compilation : Extracting local parallel, resource usage optimization. Generate the final program to be executed. 3. Execution - Execute the program on processor

An Alternative path : The FPGA- An array of Programmable logic gates -programmable interconnect Which allows the direct-mapping of an arbitrary logic circuit. wire to wire, Logic gate to logic gate

Using FPGA for Computingz

Express the algorithm as a logic circuits. -Need good tools to convert high level algorithm descriptions to logic circuit equivalents.

z

Map the circuit to the FPGA - synthesis, placement and routing problems need to be solved. Stimulate the mapped circuit in real time to execute the algorithm.program + circuit = circuit

Capability ComparisonFPGA & Von-Neumann processors are equivalent - Because Von-Neumann process is a logic circuit - Because a logic circuit can be simulated by a VonNeumann processor. Thus the FPGA or Von-Neumann processor decision is driven by "Optimality" Criteria -Size of problem -Performance requirements -Cost/Energy budget

Advantages of Von-Neumann Processor1.

Highly optimized data paths which are heavily utilized

2.

Easy to scale to large problem by using more memory

3. 4.

Well understood, optimized computation flow Multi-processing on a chip promises unlimited performance scaling

Drawbacks of Von-Neumann1.

Communication between operation is often expensive i.e implemented through memory energy/delay inefficient.

2.

Difficult to exploit parallelism - Pipeline is effective, but not scalable beyond a limit. Overloads of instruction fetching/decoding - Memory bottlenecks - Fixed memory architecture ( Caching methods, Interleaving Memory) Fixed nature of architecture

Advantages of FPGAs1.

Circuits can be customized to the algorithm eg. Choice of operations, storage architecture

2.

Direct communication is possible Parallelism can be exploited to "an arbitrary degree" - provided that the algorithm has it and enough recourses available.

3.

Flexible memory architecture

But some draw backsz

Area Efficiency is poor - Programmable logic & interconnect occupy more space

z

Delay efficiency is poor - Delay of a programmable gate/ wire is higher.

z

Unpredictable wire delays - Due to unfavorable placement

Where can the FPGA fit?In highly parallel problems with bit-level operations In signal processing problems To overcome memory bottle necks For energy efficiency

Challenges in system designz Multiple

levels of abstraction: logic to

CPUs.z Multiple

and conflicting constraints: low cost and high performance design time: Late products are often irrelevant.

z Short

The system design processz Part

of larger product design. levels of abstraction:

z Major

specification; architecture; logic design; circuit design; layout.FPGA-based system design

Dealing with complexityz

Divide-and-conquer: limit the number of components we deal with at any one time. Group several components into larger components: transistors form gates; gates form functional units; functional units form processing elements; etc.

z

Levels of abstractionz Specification: z Architecture: z Logic:

function, cost, etc.

large blocks.

gates + registers. transistor sizes for speed,

z Circuits:

power.z Layout:

determines parasitics.

Design abstractionsEnglish Executable program

specification behaviorregistertransfer Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns

function

Sequential machines Logic gates transistors rectangles

cost

logic circuit layout

Why do we care about layout?z Need

not design layout. determines:

z Layout

Logic delay. Interconnect delay. Energy consumption.z Need

to understand sources of FPGA characteristics.

FPGA Design Flow

Block Diagram of A/F injection controller

FPGA Based controller Implementation

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Controller Building Block in System generator

data_width = 12; data_binary_pt = 11; coef_width = 12; coef_binary_pt = 10;

Fs = 1;

1 1.6929 z 1 + z 2 Y ( z) C ( z) = = 1 2 1 + 1.2591z + 0.825 z X ( z)

b0 = 1; b1 = -1.6929; b2 = 1; a1 = 1.2591;

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Step ResponsesMatlab simulation

Xilinx System Generator Simulation

Comparison of Frequency ResponcesFor Stepped Sine wave input

z Peak

error : 6.8738e-2 units z Error Variance : 2.0988e-3 units

Actual Transfer Function in simulink

FPGA transfer function using system generator33

Input Signal to the controllerSensor signal from Inductive couplingSparking (before TDC) 5V

TDC

0v

45 BTDC

45 BTDC

BDC

Approach To DesignFor Hardware Synthesis ApproachBrain Body

Path Conditional Signals/ Data dependency signals Eg : over_flow, err Control Signals Eg: enable_timer, load_counter35

Main Blocks for Spark Ignition control (open loop)Top level View

Ignition puls width Edge detectors and Measuring time of inductive sensor Ignition time calculation Ignition signal duration calculation

Inductive couple sensor o/p

45 BTDC detector

Positive level count

RPSTime to frequency converterNegative level count

Look up Table Spark RPS vs Spark advanceConverts spark advance Advance In clocks angle

Signal to Ignition Actuator

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System Decompositionz

Decompose the System into Modules z Further decompose the each module in to Data path and Control path Advantages 1. IP reusable 2. Scalable / Generic 3. Easy to Debug / Verification37

Spark Ignition System Decompositionz Synchronizer z InterpolatorRelation between the RPM and spark advance angel

( 45 BTDC finder)

Counts no. pulses in terms of high frequency clock

z Ignition

Driver

To calculate Time of Ignition and Duration of Ignition

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Synchronizer Data Path Synthesis

Counter

Register

Generated from VHDL code in Xilinx Integrated Simulation Environment39

Control Path for Synchronizer

InputsSensor1 Count_overflow Clk Reset

OutputsCount_enable Reg_enable Counter_reset 40 Reg_reset

State Diagram for Ignition Driver

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How to Find RPM?

0v

45 BTDC

45 BTDC

BDC

f = 20MHz t = 50 nsec 1 rev = 1000 clocks 1 rev = 50 ms ? = 60 sec 1200 RPM Accuracy

If count = 1000

For 360 degrees 1000 clocks 1 degree = 2.5 clocks As the frequency increases accuracy increases

Modified Block Diagram (Data Path)

FF

counter

Interpolater

Ignitio

sensor1

signal

adder Driver FF adjustment counter

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Plot between RPM vs. Spark advance

Matching 96.64% Where x is rpm

Some Issues in Implementingz

When inferring hardware from HDL, it is important to keep in mind the type of hardware you want.

Ex. On the same signal we cant detect both edges --*as the CoolRunner-II FPGA is the only device that has dual-edge triggered flip-flops.z

How to communicate between two different state diagrams?

Sol : Include wait states in both state diagrams on condition of other state.z

Setup and hold timing requirements to be satisfied

Ref: http://support.xilinx.com/support/software_manuals.htm45

Reset Statez

Basically reset is to initialization- To bring the system to a known state - Although reset is asynchronous signal it should be released synchronously

Q reset Q clock

To ckt1

To ckt2

Fail-safe ECU System using Dynamic Reconfiguration z When

the system has many real-time controllers is a demand for improved circuit reliability fail-safe system is defined as

z There

z The

-To allow functional degradation after a fault, but it prevents the system from suffering fatal problems.

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ECU Under Normal Operations

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ECU in case of a fault engine controller

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Watch Dog Timers ArchitectureInput 1

Input 2

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Design validationz Checked

at every step that errors havent been introduced-the longer an error remains, the more expensive it becomes to remove it. checking: compared results of less- and more-abstract stages.

z Forward

ResultsSimulation Results of Level 1 and level 0 counter

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Simulation results of 45BTDC detector

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Synchronizer Control Path in Xilinx ISE Synthesis tool for Spartan 3 (XC3S200FT256) board

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Synchronizer Data Path in Xilinx ISE Synthesis tool for Spartan 3 (XC3S200FT256) board

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Conclusionz

Second order controller implemented using direct form 1, simulated and verified in Matlab

z

45 BTDC Detector, Ignition time calculator simulated, functionally verified and synthesized

z

Proposed Fail-safe ECU architecture using Dynamic Reconfiguration FPGA

Future Workz z z z z z z z

Integration of all blocks and Synthesis Timing Verification of controller Testing on the IC engine Implementation of Fail safe controller using dynamic reconfigurable FPGA Test the over all controller on the IC engine Variable Valve Timing (VVT) controller Knock detection algorithm implementation using Fuzzy logic Transmission Control system, A/C control

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Bibliography1. 2. 3. 4.

5.

Clive Max Maxfield Design Warriors guide to FPGA , Elsevier publications 2004. Allan W. M. Bonnick, Automotive Computer Controlled Systems 2001. William B. Ribbens, Understanding Automotive Electronics Fifth Edition 1998. CARROLL DASE, JEANNIE SULLIVAN FALCON, and BRIAN MACCLEERY Motorcycle Control Prototyping Using an FPGA-Based Embedded Control System OCTOBER 2006 IEEE CONTROL SYSTEMS MAGAZINE. A. ebi, L. Gven At all, A Low Cost, Portable Engine Electronic Control Unit Hardware-in-the-Loop Test System, IEEE ICSE June 2005.58

Thank You Questions? Suggestions?

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Conversion floating math to fixed pointC N = 1.4 RN 1.12 RN 1 + 1.6CN 1 0.6CN 2In order to represent 1.4 or 1.12, we must scale integers and use fixed-point math Since these constants less than 2 (most of z-functions consts.) Scale maximum value of the P constant to 2. if 16-bit

Division can be executed with a shift right of 14 places. To accelerate execution, we can also shift it left 2 places and take the most significant word