flipflops[1]

8/18/2019 Flipflops[1]

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Combinational

circuitMemory

elements

OutputsInputs

Next

state Presentstate

Clock

Clock

a periodic external event (input)

Clock

a periodic external event (input)



Comparision b/w combinational &sequential logic circuits.

combinational sequential

The output variables are at alltimes dependent on thecombination of inputvariables

The output variablesdependent not only on presentinput variables but also

depend upon the pastinformation

Memory unit is not required Memory unit is required tostore the past information

Faster in speed , because thedelay b/w input & output isdue to propagation delay of

logic gates

lower than the combinationalcircuits

These are easy to design These circuits arecomparatively harder todesign

!t does not have a cloc" signal !t may or may not have a cloc"

signal . Most sequentialcircuits have a cloc" signal



Classication of sequential logic circuits-depending on timing of their signals

Synchronous Asynchronous

The change in input signalcan eect memoryelement upon activation

of cloc" signal

The change in input signalcan eect memoryelement at any instant of

time.Memory elements arecloc"ed *ip+*ops

Memory elements areeither uncloc"ed *ip+*opsor time delay elements

The ma0imum operatingspeed of cloc" depends ontime delays involved

1ecause of absence ofcloc" asynchronouscircuits operate fasterthan synchronous circuits

#asier to design More di2cult to design



•Memory elements are either latches or *ip+*ops.

• The main dierence b/w latches & *ip+*ops is in

the method used for changing their state.

•Flip+*op is a logic circuit used to store one bit of

binary information.

•3atch is an uncloc"ed *ip+*op.

Types$

4

(

56

T



+4 3atch with 784s

1 1

1 0

0 1

0 0

S R Q Q’

0 1

1 0 Set

1 0 Stable

0 1 Reset

0 0 Undefined

• S-R latch made from cross-coupled NORs

• If Q = 1, set state

• If Q = 0, reset state• Usually S=0 and R=0

• S=1 and R=1 generates unpredcta!le results

R (reset)

Q

Q

S (set)



4 3atch %nalysis

Consider the four possible cases$

a 9 :, 4 9 ;

b 9 ;, 4 9 :

c 9 ;, 4 9 ;

d 9 :, 4 9 :



4 3atch %nalysis

a S = 1, R = 0:

b S = 0, R = 1:

R

S

Q

Q

N1

N"

0

1

1

00

0

0

0

1

1

then Q 9 : and Q 9 ;

R

S

Q

Q

N1

N"

1

0

0

10

1

0

0 1

1

then Q 9 ; and Q 9 :



4 3atch %nalysis

c# S = 0, R = 0:

d# S = 1, R = 1:

R

S

Q

Q

N1

N"

1

1

0

00

0

We got Memory!

Invali state: " #$%Q

R

S

Q

Q

N1

N"

0

0

1

01

0

R

S

Q

Q

N1

N"

0

0

0

10

1

Q prev

= 0 Q prev

= 1

0

then Q 9 Q prev

and Q 9

Q prev

0 1

1

1

1 0

0

0

00

0

then Q 9 ; and Q 9;



I#&'%S &resent

state

#e(t state S%A%)

4 <n <n=: <n=:>

; ; ; ; : 78

C?%7@#: : ;

; : ; ; :4##T

: ; :

: ; ; : ; #T: : ;

: : ; ; ; !7(#T#4M!7%T#

: ; ;

%R'%* %A+)



S-R Latch ith !"!#s("C$%&' L):

4

<

<>

0 0

0 1

1 0

1 1

S R Q Q’

0 1

1 0 Set

1 0 Store

0 1 Reset

1 1 Disallowed

• $atch made from cross-coupled N%N&s

• Sometmes called S'-R' latch

• Usually S=1 and R=1

• S=0 and R=0 generates unpredcta!le results



% 9;, 49:

#T

1 9:, 49;4##T



C 9:, 49: -78

C?%7@#

( 9;, 49;-A48?!1!T#(



in-uts &resentstate

#e(t state

S%A%) 4 <n <n=: <n=:>

; ; ; : : !7(#T#4M!7%T#

: : :

; : ; : ;#T

: : ;

: ; ; ; : 4##T

: ; :

: : ; ; : 78C?%7@#

: : ;



S.R atches



S-R Latch ith !"!#s("C$%&' *%+*):

S R S/ R/ / S%A%)

; ; : : < <> 78

C?%7@#; : : ; ; : 4##T

: ; ; : : ; #T

: : ; ; : : !7(#T#4

M!7%T#



S-R $atch (th control nput



1 9;, 49:

-4##T



C 9:, 49;

-#T



( 9:, 49:

-A48?!1!T#(



Triggering in *ip*ops

3evel triggering -in latches

Aositive level triggering

7egative level triggering

Flip*ops$

Aulse triggering -=ve & +ve#dge triggering -=ve & +ve

Lo-*iLo-*i ede*i-Lo*i-Lo ede



%bstract 4epresentations

# Q

C

# Q

C

# Q

C

# Q

C

&-$atch

)*ost+e $e+el rggered#

&-$atch

)Negat+e $e+el rggered#

&-lp lop

)Rsng .dge rggered#

&-lp lop

)allng .dge rggered#



/loced SR lp-lop



$R.$* $"/L'

$2enable

3

S R n n41 S%A%)

; ' ' ' <n nochange

: ; ; ; ; nochange

: : :: ; : ; ;

4##T: : ;

: : ; ; :#T: : :

: : : ; 0 !7(#T#4M!7%T

#: : 0



o dra( (a+eforms for flp flops you need to !egn (th an ntal condton at Q, mar the

area (here the cloc nput s asserted and then dra( the output response $et's use an

ntal condton of Q =0

SR Flip Flop Waveform Diagrams :

Set

Reset

/loc

S

R

Q

Q

Clk

he ntal condton Q =0 smared as a dot on the output

(a+eform dagram

he flp flop has a negat+e edge

trggered cloc he cloc s

asserted (hen /l maes a

transton from 1 to 0 he

asserted 2one s mared off n

yello(

Untl the cloc changes from 1 to 0 t s NO asserted

hus Q holds at 0

%naly2e the (a+eform and dra(

Q

On ths negat+e edge S=R=03 No /hange 4ode

hus Q holds at 0 No analyss s re5ured untl ne6t

negat+e edge

On ths negat+e edge S=1 and R=03 S. 4ode

hus Q sets to 1 No analyss s re5ured untl the ne6t

negat+e edge



C*"R"C$'R%S$%C $"/L'

'C%$"$%!2"33L%C"$%! $"/L'

n n41 S R

; ; ; '

; : : ;

: ; ; :

: : ' ;

S R n41

; ; <n; : ;

: ; :

: : B

R

SR00 01 11 10

0 0 7 1

1 0 7 1

0

1

Q)t #

S

/haracterstc .5uaton3

Q8 = S 8 R' Q

( 3 t h



C D Q0 x No change

1 0 0

1 1 1

(+3atch

• %dvantages over +4 3atch

9 ingle input to store : or ;

9 %void spurious input of 9: and 49:



( 3atch Timing (iagram

output 4ollos input in here

clock ena5les input to 5e 6seen7

clock

#

Q



/loced & lp-lop

• Stores a +alue on the post+e edge of C

• Input changes at other tmes ha+e no effect on output



&

/*

Q

Q’

:

;

<

1

"

Cloc"ed ( Flip+Flop



$R.$* $"/L'

$2enabl

e3

5 n n41 S%A%)

; ' ' <n nochang

e

: ; ; ;

4##T: : ;

: : ; :#T

: : :

'C%$"$%!2"33L%C"$%! $"/L'

n n41 5

; ; ;

; : :

: ; ;

: : :

C*"R"C$'R%S$%C $"/L'

5 n41

; ;: :

&

0 1

0 1

Q8 = &

0 1

0

1

Q



/loced -> lp lop



RU? %@$.

$ 6 n n41

n41/

S%A%)

; ' ' ' <n <n> nochange

: ; ; ; ; : nochange

: : : ;: ; : ; ; :

4##T: : ; :

: : ; ; : ;#T: : : ;

: : : ; : ; T8@@3# T%T#

: : ; :



C*"R"C$'R%S$%C $"/L'

'C%$"$%!2"33L%C"$%! $"/L'

n n41 6

; ; ; '; : : '

: ; ' :

: : ' ;

6 n41

; ; <n; : ;

: ; :

: : <n>0 0 1 1

1 0 0 1

00 01 11 10

>

>

Q

Q8 = & = Q 8 >Q

0

1

Cl k d 8 9li 9l



Clocked 8- 9lip 9lop

• (o data nputs, and >

• -A set, > -A reset, f =>=1 then toggle output

Characteristic $a5le



$ 6 n m s

; ; ; ; 7C

; 7C ;

: : 7C

: 7C :

; : ; ; 7C

; 7C ;

: ; 7C

: 7C ;

$R.$* $"/L'



$

6 n m s

: ; ; : 7C

; 7C :

: : 7C

: 7C :

: : ; : 7C

; 7C :: ; 7C

: 7C ;



%iming iagram 7or master.slave JK



g g J

FLIPFLOP

%iming iagram 7or master.slave JK



g g J

LATCH



%iming iagram 7or a master.slave

SR 8i-.8o-



%iming iagram 7or a master.slaveSR LATCH



Clocked $- 9lip 9lop

$ l 9li 9l



Q

$ole 9lip-9lops

Q

Q>

cl

Q

Q

$R.$* $"/L'



$

% n n41 n41/ S%A%)

; ' ' <n <n> nochang

e

: ; ; ; : nochang

e: : : ;

: : ; : ; T8@@3#: : ; :C*"R"C$'R%S$%C $"/L'

% n41

; <n

: <n>

'C%$"$%!2"33L%C"$%! $"/L'

n n41 %

; ; ;; : :

: ; :

: : ;Q(t1) = $;Q(t) $Q;(t)

= $ Q(t)

"s<nchronous %nputs



"s<nchronous %nputs

D 5, 6 are synchronous in-uts

o #ects on the output are synchroniEed with the CLK input.

• Asynchronous in-uts operate independently of thesynchronous inputs and cloc"

o et the FF to :/; states at any time.

"s<nchronous %nputs



"s<nchronous %nputs



Master.Slave )ge.%riggere 9li-.9lo-



g gg - -

• Can connect two level+sensitive latches in Master+lave conguration to form edge+triggered *ip+*op

• Master latch catchesG value of (G at <MG when

C36 is low

• lave latch causes <G to change only at rising edge

of C36 C36

( <

(

<M

C36

Master3atch

lave3atch

<M

H 0 I 9 :J Transistors

<

C36



9li-.8o- timings



9li- 8o- timings1)Setup tie: It is the minimum time 7or hich thecontrol levels nee to be maintaine constant on

the in-ut terminals o7 the 8i-.8o-, -rior to thearrival o7 the triggering ege o7 the cloc; -ulse, inorer to enable the 8i-.8o- to res-on reliably<

>)*old tie: It is the minimum time 7or hich the

control levels nee to be maintaine constant onthe in-ut terminals o7 the 8i-.8o-, a7ter thearrival o7 the triggering ege o7 the cloc; -ulse, inorer to enable the 8i-.8o- to res-on reliably<

?)3ropaation #ela<: It is the time interval beteenthe time o7 a--lication o7 the triggering ege orasynchronous in-uts an the time at hich theout-ut actually ma;es a transition<

•t&* : It is measure 7rom the triggering ege o7

cloc; -ulse 2or -reset in-ut3 to the $W to *I*

Setu- an *ol %imes



Setu- an *ol %imesSetup me3 ?o( long a sgnal must !e sta!le

precedng the cloc edge

/l

&

setup

tme

hold

tme

& Q

/l

& Q

?old me3 ?o( long a sgnal must !e sta!le after the

cloc edge

Setup3 *ass

?old3 *ass

Setup3 al

?old3 *ass

Setup3 *ass

?old3 al

Setup3 al

?old3 al

Setu- an *ol times: 9li- 9lo-s



D<$SD< *ost+e

.dge rggered

& lpflop

• Setup tme 9 "0ns

• ?old tme 9 :ns

• *ropagaton delays - $o( to ?gh 9 "; ns ma6, 1; ns typ

- ?gh to $o( 9 <0 ns ma6, ": ns typ

&

/l

"0ns :ns "0ns :ns

Q

";C1;ns <0C":ns

&ro-agation 5elays in an SR



atch

• Aropagation delay the time it ta"es achange in an input signal to produce a

change in an output

$#>)RSI$# $9 9I&9$&S



1#SR $I*$O* O &-$I*$O*3

I#&'%253

&R)S)#%S%A%)2n

3

#)?%S%A%)2n4

13

9I& 9$&I#&'%S

S R

; ; ; ; :

; : : : ;: ; ; : ;

: : : ; :

S=#

R=D’



"#SR-$I*$O* O >-$I*$O*3

6 n n41 S R

; ; ; ; ; 0: : 0 ;

; : ; ; ; 0

: ; ; :

: ; ; : : ;: : 0 ;

: : ; : : ;

: ; ; :

R

S

Q

Q

>Q

Qcl

R = Qn

S = 8 Qn;

3) !lip!lop to "# $lip%$lop



6 n n41 5

; ; ; ; ;

: : :

; : ; ; ;

: ; ;

: ; ; : :

: : :

: : ; : :

: ; ;

# = ; Qn 8 Qn;

!lip!lop to "# $lip%$lop



(

3atch

C36

<

<

5

6

LToggle Flip+Flop from (+*ip*op



• Toggles stored value if T 9 : when

C36 is high

(3atch

C36

<

T

% n n41 5

; ; ; ;

: : :: ; : :

: ; ;

# = $ Q(t)

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