engr-43 lec-07c sp12 sequenial-logic flipflops

W A T K I N S - J O H N S O N C O M P A N Y Semiconductor Equipment Group

Bruce Mayer, PELicensed Electrical & Mechanical [email protected] 43Sequential (FlipFlop) Logic

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisBut First WhiteBoard WorkFor the Truth Table Shown at rightConstruct the Karnaugh MapWrite The Minimized Function Q(A,B,C,D)Draw the Logic CircuitNotice 1s in Rows1, 5, 9, 13, 14, 15Need only put 1s in these locations; other cells Assumed to be Zero

RowABCDQ000000100011200100300110401000501011601100701110810000910011101010011101101211000131101114111011511111BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisBlank Map (NonStretching)AB\CD00011110000111110AB\CD0001111000ABCDABCDABCDABCD01ABCDABCDABCDABCD11ABCDABCDABCDABCD10ABCDABCDABCDABCDBMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisCan TYPE in cells on Both MapsStretchable Blank Map

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisMore WhiteBoard WorkImplement This Function using ONLY NAND Gates

An Example of NAND-Gate SynthesisNANDS are easier to construct than ANDs, ORs, NORs NANDs are the preferred gate for logic circuits

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisMemory Filled LogicThe Invert/AND/OR Combinatorial Logic Circuits depended ONLY on the Current Inputs; previous states did Not affect the Current StateCombinatorial Logic is MEMORYLESSIn SEQUENTIAL Logic the Circuit Output CAN Depend on the Previous condition of the CircuitSequential Logic has [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisSequential CircuitA sequential circuit consists of a feedback path, and employs some memory elements

[Sequential circuit] = [Combinational logic] + [Memory Elements]

Combinational logic Memory elements Combinational outputs Memory outputs External inputs [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisSynchronous vs AsynchronousAlmost all Logic Chips Include a ClockThe Clock helps to Synchronize the Operation of the Circuits.The Clock is simply a very regular Hi/Lo Pulse train Logic Forms are divided into two groups:SYNCHRONUS Depend on ClockAsynchronous NO Clock-Dependency

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisAsynchronous S-R FlipFlopCross-coupled NOR gates

Similar to inverter pair, with capability to force Q to 0 (reset=1) or 1 (set=1)

RSQQ'

RSQ0101

RSQQ'1010

RSQQ'n-100n-1

RSQQ'[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisNOR: Any-HIGH input => LOW output; else-HIGHNAND based SR FlipFlopCross-coupled NAND gates

Similar to inverter pair, with capability to force Q to 0 (reset=0) or 1 (set=0)

R'S'Q

QQ'S'R'NOR notesAny HI input LO outputAny HI LOAll LO inputs HI outputAll LO HIAny LO input HI outputAny LO HIAll HI inputs LO outputAll HI LONAND [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisNAND: ANY-Low => HIGH; else LowState Behavior of SR FlipFlopTransition Table

Sequential (output depends on history when inputs R=0, S=0) but asynchronous

RSQQ'SRQn-1Qn 000000110100011010011011110X111Xholdresetsetnot allowedcharacteristic equationQn = S + RQn-1

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisSR FlipFlop Timing Behavior

ResetHoldSetSetResetRaceRSQQ100

RSQQ'Races Produce UnPredictable OutPutsAny HI input LO outputAny HI LOAll LO inputs HI outputAll LO [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisShaded areas have R=S=Hi, and Q = Q = Lo NOT ALLOWEDClocked SR FlipFlopControl times whenR and S inputs matterOtherwise, the slightest glitch on R or S while enable is low could cause change in value storedEnsure R & S stable before utilized (to avoid transient R=1, S=1)

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisClocked SR FlipFlopsNOR-NOR Implementation

TruthTable

For NOR: any-HiLO; ALL-LOHi

RSEnRSQn00011NotAllowed01010Reset to 010001Set to 111x00Qn1xx100Qn1x Dont [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisClocked SR FlipFlopsNAND-NOR Implementation

TruthTable

RSCQn00xQn1011Set to 1101Reset to 0111NotAllowedxx0Qn1x Dont Care

Circuit [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisSR FlipFlop Clock-OverideSometimes Need to Set or Reset the FlipFlop withOUT Regard to the Clock

Note the position of Pr & Cl on the 3rd-Stage ORs (any HiHi)Ensures Pr & Cl OverRide R, S, & C

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisPr = PreSet * Cl = ClearEdge Triggered D FlipFlopsensitive to inputs only near edge of clock signal (not while steady )

QDClk=1RS0D0DDQholds D' whenclock goes lowholds D whenclock goes low

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Edge-Triggered FlipFlop FlavorsPOSITIVE edge-triggeredInputs sampled on RISING edge; outputs change after RISING edgeNEGATIVE edge-triggered flip-flopsInputs sampled on falling edge; outputs change after falling edge

positive edge-triggered FFnegative edge-triggered FFDCLKQposQpos'QnegQneg'[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisEdge Triggered D FlipFlop4-NAND, 1-NOTimplementation

Truth Table for All Postive-GoingEdge D-FFsNAND:any LO HiAll HI LO

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisEdge Triggered JK FlipFlopA Toggling Flip FlopUnder A certain Control-Set: Q QNotice that Q does NOT go HI-for-sure or LO-for-sure, and it does NOT remain STEADYA NAND Nest:Circuit Symbol

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisJK FlipFlop Toggle TruthTableThe Simplified Ckt

Note that the outputs feed back to the enabling NAND gates. This is what gives the toggling action when J=K=1ReCall NANDAny LO HiALL Hi LO

CJKQnNotes0xxQn1No Chg1xxQn1No Chg00Qn1No Chg010Reset to 0101Set to [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisCascading FF Shift RegisterSerial-in/Parallel-out Shift register New value goes into first stageWhile previous value of 1st stg goes into 2nd stgThe QN can be SAMPLED any timeCLKINQ0Q1DQDQOUT

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisExample: Eliminate InconsistencyDQDQQ0ClockClockQ1Async InputClocked Synchronous Systemis asynchronous and fans out to D0 and D1

one FF catches the signal, one does notinconsistent state may be reached!In

Q0

Q1

CLKDQDQQ0ClockClockQ1Async InputDQSynchronizerWant to Send SAMEInput Value to TWO [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisFlipFlops SummarizedDevelopment of D-FFLevel-sensitive used in custom integrated circuitscan be made with 4 pairs of gatesUsually follows multiphase non-overlapping clock disciplineEdge-triggered used in programmable logic devicesGood choice for data storage register

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisFlipFlops SummarizedHistorically J-K FF was popular but now never usedSimilar to R-S but with 1-1 being used to toggle output (complement state)Same Operation Can always be implemented using D FlipFlopsPreset and Clear inputs are highly desirable on flip-flopsUsed at start-up or to reset system to a known [email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisFlipFlops SummarizedReset (set state to 0) RSynchronous: Dnew = R' Dold Transition only when next clock edge arrivesAsynchronous: doesn't wait for clock, quick but dangerousPreset or Set (set state to 1) SSynchronous: Dnew = Dold + S Transition only when next clock edge arrives)Asynchronous: doesn't wait for clock quick but dangerous

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisWhiteBoard WorkUse Gates and a D-FF to Implement the JK-FF operation

CJKQnNotes0xxQn1No Chg1xxQn1No Chg00Qn1No Chg010Reset to 0101Set to 111Qn1TOGGLE

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisAll Done for Today

IEEE91-1984Gates

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit Analysishttp://www.enzim.hu/~szia/cddemo/edemo4.htmBruce Mayer, PELicensed Electrical & Mechanical [email protected] 43AppendixLogic Syn

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit Analysishttp://en.wikipedia.org/wiki/CMOS

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

[email protected] ENGR-43_Lec-05c_Thevenin_AC_Power.pptx#Bruce Mayer, PE Engineering-43: Engineering Circuit AnalysisNAND Gate SynthesisWith the expression in SOP formAfter any need inversions; In the first logic level there are as many logic gates as terms in the SOP expressionEach gate corresponds to a SINGLE Term, and has, as inputs, the variables in that termThe outputs of the First Logic-Level are ALL inputs to a SINGLE (multi-input if needed) NAND gate











engr-43 lec-07c sp12 sequenial-logic flipflops

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