lacthes and flipflops
TRANSCRIPT
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Sequential Circuits:
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Z. Jerry ShiComputer Science and Engineering
Thank John Wakerly for providing his slides and figures.
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Sequential circuits
Output depends on current input andpast history of inputs
The circuits can rememberpast inputs
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Bistable element
The simplest sequential circuit
One state variable, say, Q
HIGH LOW
LOW HIGH
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Bistable element
The simplest sequential circuit
One state variable, say, Q
LOW HIGH
HIGH LOW
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Analog analysis
Assume pure CMOS thresholds, 5 V rail
Theoretical threshold center is 2.5 V
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Analog analysis
Assume pure CMOS thresholds, 5V rail
.
2.5 V 2.5 V
. .
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Analog analysis
Assume pure CMOS thresholds, 5V rail
Theoretical threshold center is 2.5 V
.... ..
2.5 V 2.5 V4.8 V5.0 V2.0 V0.0 V
Metastable state
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Metastability
Metastability is inherent in any bistable circuit
,
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Control bistable
How to control it?
Control in uts S and R
S-R latch
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S-R latch operation
Metastability is possible
simultaneously.
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S-R latch timing parameters
Propagation delay
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S-R latch symbols
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S-R latch using NAND gates
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S-R latch with enable
Let C decide whether S and R can
reach the bistable circuit.
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D latch
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D-latch operation
= =
When C = 0, Q does not change.
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D-latch timing parameters
When C = 1, Q follows D
Pro a ation dela from C or D
When C = 0, Q remembers Ds value at the 10 transition Setup time (D before Cs falling edge)
Hold time (D after Cs falling edge)
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Positive edge-triggered D flip-flop
1 2
CLK_L QLatch 2
Status
QMLatch 1
Status
CLK
Dprev@ Dprev@
0 QM=Dprev@ EnabledDprev@ Disabled1
Dprev@ D
Dprev@ Disabled~ DEnabled
1
0
QM = D @ EnabledD@ Disabled01
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Positive edge-triggered D flip-flop behavior
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D flip-flop timing parameters
Propagation delay (from CLK)
Hold time (D after CLK)
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CMOS positive edge-triggered D flip-flop
Two feedback loops (master and slave latches)
Uses transmission gates in feedback loops
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Positive edge-triggered D flip-flop with preset and clear
Preset and clear inputs
Like S-R latch
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Negative edge-trigged D flip-flop
Invert the input CLK signal
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Positive-edge-triggered D flip-flop with enable
How does EN works?
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Scan flip-flop
How is this circuit
different from the
previous one?
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Scan flip-flops -- for testing
TE = 0 normal operation
TE = 1 test operation
A o t e p- ops are oo e toget er n a a sy c a n romexternal test input TI.
Load up (scan in) a test pattern, do one normal operation, shift
out (scan out) result on TO.
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Edge-Triggered J-K flip-flop
Not used
anymore
Dont
worrya ou em
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T flip-flops
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T flip-flops with enable
Important for counters
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Many types of latches and flip-flops
S-R latch
S_L-R_L latch
S-R latch with enable
D latch
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Edge-triggered D flip-flop with enable
Edge-triggered D flip-flop with preset and clear can p- op
Edge-triggered J-K flip-flop
Master/slave S-R flip-flop
Master/slave J-K flip-flop T flip-flop
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