AB

C AB

C

AB

CA C

AND: C = A B OR: C = A + B

NOT: C = A'

Figure 1-1 Basic Gates

EXCLUSIVE OR: C = A + B

X

YCin

Cout

Sum

FULLADDER

X Y Cin CoutSum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Figure 1-2 Full Adder

(a) Full adder module(b) Truth Table

Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCinSum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin

1

1

1

1

1

1

0100 11 10

01

00

11

10

ABCD

1

X1

X

1

four corner termscombine to give B' D'

C A'BD

F =·m(0,2,3,5,6,7,8,10,11) + ·d(14,15) = C + B' D' + A' BD = (B' + C + D) (B + C + D') (A'+B')

0 0

0 0 0

4

6

7

5 13

15

14 10

12

1

3

8

9

11

2

0100 11 10

01

00

11

10

ABCD

0

Figure 1-3 Four-Variable Karnaugh Maps

X

1

1

1

1

1

0100 11 10

01

00

11

10

ABCD

1

1A'C'

ACD

A'B'D'

0

1

3

2 6 14 10

7 15 11

4 12 8

5 13 9

X

Figure 1-4 Selection of Prime Implicants

F = A'C' + A'B'D' + ACD + A'BDor

F = A'C' + A'B'D' + ACD + BCD

1

X

1

X

X

1 1

1

0100 11 10

01

00

11

10

ABCD

E = F = 0MS0 = A'B' + ACD

X

X

X

X

X

X

1

X

X

0100 11 10

01

00

11

10

ABCD

E = 0, F = 1MS2 = AD

X

1

1 X

X

X

X

X X

X

0100 11 10

01

00

11

10

ABCD

E = 1, F = 0MS1 = A'D

1

E

E X

1

X

X

1

F

1

1

0100 11 10

01

00

11

10

ABCD

G

Figure 1-5 Simplification Using Map-Entered Variables

G = MS + EMS + FMS

= A'B' + ACD + EA'D + FAD

0 21

NAND:

NOR:

C = (AB)' = A' + B'

C = (A+B)' = A'B'

C

C

C

C

AB

AB

AB

AB

Figure 1-6 NAND and NOR Gates

DC

AB' G

EF

Z

A

G'DC'B'

EF

Z

Double inversion cancels

Complemented inputcancels inversion

Figure 1-7 Conversion to NOR Gates

(a) AND-OR network

(b) Equivalent NOR-gate network

AB C

D E F

AB' C

D' E' F

Added inverterAdded inverter

AB C

DE F

Bubbles cancel

Figure 1-8 Conversion of AND-OR Network to NAND Gates

(a) AND_OR network

(b) First step in NAND conversion

(c) Completed conversion

Figure 1-9 Elimination of 1-Hazard

0 1

0

1

10

1

0

10

01

00

11

10

ABC

C

BA

F

A F = AB' + BC + AC

(c) Network with hazard removed

CE

BA D

F0 1

0

1

10

1

0

10

01

00

11

10

ABC

F = AB' + BC1 - Hazard(a) Network with 1-hazard

B

D

E

F

0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns

(b) Timing Chart

B'

DFF

CLK D

QQ'D Q Q+

0 0 00 1 01 0 11 1 1

Figure 1-10Clocked D Flip-flop

with Rising-edge Trigger

Q = D+

CKFF

Q' Q

JK

J K Q Q+

0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

Figure 1-11 Clocked J-K Flip-flop

Q = JQ' + K'Q+

FF

CLK T

QQ'

T Q Q +

0 0 00 1 11 0 11 1 0

Figure 1-12 Clocked T Flip-flop

+Q = QT' + Q'T = Q + T

S

R

P

Q

S R Q Q0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 –1 1 1 –

Figure 1-13 S-R Latch

Q = S + R'Q+

+

LatchQ

DG

G D Q Q+

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Figure 1-14 Transparent D Latch

D

D

G

Q Q+ = DG + G'Q + (DQ)

Figure 1-15 Implementation of D Latch

CombinationalNetwork

StateReg

Next state

Inputs (X) Outputs (Z)

clock

State

Figure 1-16 General Model of Mealy Sequential Machine

S1

S0

S2

S5

S4S3

S6

0/1

1/00/1

1/0

0/1

0/1

0/0,1/1 1/0

0/0,1/10/0,1/1

NC

NC

NC C

C

C

t0

t1

t 2

t3

PS X = 0 X = 1

NS

S0S1S2S3S4S5S6

S1S3S4S5S5S0S0

S2S4S4S5S6S0–

Z

X = 0 X = 1

1100101

001101–

Figure 1-17 State Graph and Tablefor Code Converter

(a) Mealy state graph(b) State Table

From Page 20

I. States which have the same next state (NS) for a given input should be given adjacentassignments (look at the columns of the state table).

II. States which are the next states of the same state should be given adjacent assignments(look at the rows).

III. States which have the same output for a given input should be given adjacent assignments.

I. (1,2) (3,4) (5,6) (in the X=1 column, S1 and S2 both have NS S4;in the X=0 column, S3 & S4 have NS S5, and S5 & S6 have NS S0)

II. (1,2) (3,4) (5,6) (S1 & S2 are NS of S0; S3 & S4 are NS of S1; and S5 & S6 are NS of S4)

III. (0,1,4,6) (2,3,5)

Figure 1-18(a)State Assignment Map

0 1

00

01

11

10

Q1Q2 Q3

S0

S5 S3

S6 S4

S1

S2

Figure 1-17(b) State Table Figure 1-18(b) Transition Table

NS Z Q1:Q2:Q3: ZPS X=0 X=1 X=0 X=1 Q1Q2Q3 X=0 X=1 X=0 X=1S0 S1 S2 1 0 000 100 101 1 0S1 S3 S4 1 0 100 111 110 1 0S2 S4 S4 0 1 101 110 110 0 1S3 S5 S5 0 1 111 011 011 0 1S4 S5 S6 1 0 110 011 010 1 0S5 S0 S0 0 1 011 000 000 0 1S6 S0 – 1 – 010 000 xxx 1 x

001 xxx xxx x x

S0 = 000, S1 = 100, S2 = 101, S3 = 111, S4 = 110, S5 = 011, S6 = 010

1 1

0

0

1 1

0

0 X

1

X

0

1

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

D1 = Q1+ = Q2'

0 1

1

1

1 1

1

1 X

1

X

0

0

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

D2 = Q2+= Q1

0 1

1

1

0 0

1

0 X

0

X

0

1

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

D3 = Q3+ = Q1Q2Q3 + X'Q1Q3' + XQ1'Q2'

1 1

1

0

0 1

1

0 X

0

X

0

0

X

1

1

0100 11 10

01

00

11

10

XQ1Q2Q3

Z = X'Q3' + XQ3

Figure 1-19Karnaugh Maps for Figure 1-17

G5

G6

G7

Q1Q2Q3

Q1Q3'

Q1'Q2'

XG3

G2

G1

D Q

Q'

D Q

Q'

D Q

Q'

ZG4D3

Q2'

Q1

CLK

Q1

Q1'

Q2

Q2'

Q3'

Q3

X

X'

A1

A2

A3

A5

A6

X'

FF1

FF2

FF3

I1

Figure 1-20 Realization of Code Converter

1 1

0

0

1 1

0

0 X

1

X

0

1

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

0 1

1

1

1 1

1

1 X

1

X

0

0

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

0 1

1

1

0 0

1

0 X

0

X

0

1

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

J1 K1' J1

Q1+ Q2+ Q3

+

J3

J3

K3'

K2'

J2

1 1

0

0

1 1

0

0 X

1

X

0

1

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

Q1+

1 X

X

X

X X

X

X X

X

X

0

1

X

0

0

0100 11 10

01

00

11

10

XQ1Q2Q3

J1= Q2'

X 0

1

1

0 0

1

1 X

0

X

X

X

X

X

X

0100 11 10

01

00

11

10

XQ1Q2Q3

K1 = Q2

J1 = Q2' K1 = Q2

J2 = Q1K2 = Q1'

J3 = X'Q1 + XQ1'K3 = Q1' + Q2'

Figure 1-21 Derivation of J-K Input Equations

(a) Derivation using separate J-K map

(b) Derivation using the shortcut method

NRZ

NRZI

RZ

Manchester

0 1 1 1 0 0 1 0bit sequence

1 bittime

Figure 1-22Coding Schemes for Serial Data Transmission

ConversionNetwork

XNRZ data

CLK2Z Manchester data

S 00

S31

S10

S21

0

1 1

1

00S0S1S2S3

S1S2S1 –

S3 –S3S0

X = 0 X = 1Next State

0011

PresentState

PresentOutput (Z)

Figure 1-23 Moore networkfor NRZ-to-Manchester Conversion

(a) Conversion network

(b) State Graph (c) State table

0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0X (NRZ)

CLOCK2

State

Z(Manchester)

S0 S1 S2 S3 S0 S3 S0 S3 S0 S1 S2 S1 S2 S3 S0 S1

0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0

1 bittime

1 bittime

Figure 1-24 Timing for Moore Network

N1 Z1 = 1( s i, X )s i

s j Z 2 = 2 ( s j , X )

X

s i sj

N2

Z1 Z2 X

Figure 1-25 Determination of Equivalent States

for every input sequenceiff =

Figure 1-26(i) State Table Reduction

PresentState

NextState

X = 0 1

PresentOutputX = 0 1

a c f 0 0b d e 0 0c h/ a g 0 0d b g 0 0e e b 0 1f f a 0 1g c g 0 1h c f 0 0

c - de - f

f - g

b - cf - g

a- de- g

e- g a- b

a- b

c - eb-g

e - fa- g

b

c

d

e

f

g

a b c d e f

a ≡ b iff c ≡ d and e ≡ f

Figure 1-26(ii) State Table Reduction

c - de - f

f - g

b - cf - g

a- de- g

e- g a- b

a- b

c - eb-g

e - fa- g

b

c

d

e

f

g

a b c d e f

c - de - f

f - g

b - cf - g

a- de- g

e- g a- b

a- b

c - eb-g

e - fa-g

b

c

d

e

f

g

a b c d e f

a ≡ b iff c ≡ d and e ≡ f

a ≡ b, c ≡ d, e ≡ f

Figure 1-26(iii) State Table Reduction

PresentState

NextState

X = 0 1

PresentOutputX = 0 1

a c f 0 0b d e 0 0c h/ a g 0 0d b g 0 0e e b 0 1f f a 0 1g c g 0 1h c f 0 0

Present State X = 0 1 X = 0 1

a c e 0 0c a g 0 0e e a 0 1g c g 0 1

Final Reduced Table

a ≡ b, c ≡ d, e ≡ f

X

Clock

State S0 S1 S3 S5 S0 S2 S4 S5 S0

Z

S1 S3 S5 S0 S2 S4 S5 S0 S2

1 1 0 0 0 1 1

0 0 1 0 1 0 0 1

1

NextState

t a t b t c

*

* = S 1

Figure 1-27 Timing Diagram for Code Converter

Figure 1-28 Timing Diagram for Figure 1-20

X

Clock

Z

Q2

Q3

Q1

0 0 1 0 1 0 0 1

1 1 1 0 0 0 1 1

Clock

D

Q tplh tphl

tsu th

Figure 1-29 Setup and Hold Times for D Flip-flop

X

CLK

D

txty

tcxmaxtsu th

tcxmin

Figure 1-30 Setup and Hold Timing for Changes in X

CONTROLSECTION

DATASECTION

ConditionSignals

DataIn

DataOut

Clock

ControlInputs

ControlSignals

Figure 1-31 Synchronous Digital System

Clock CS CKClock

CS CK

CLK

Clock

SwitchingTransients

ControlSignal

Clock·CS

State Change Initiated Here

Uncertain

Figure 1-32 Timing Chart for System with Falling-Edge Devicves

Figure 1-33 Gated Control Signal

(a) Faling-edge device (b) Rising-edge device

"Rising Edge" Device

Clock CS CK

CLK1

Clock

SwitchingTransients

ControlSignal (CS)CLK1 =Clock · CS

CS

(a) (b)

State Change Initiated Here

CLK2 =Clock + CS

Figure 1-34 Timing Chart with Rising-Edge Devices

CKClock CS

CKClock

CS Enable

CLK2

(a) with gated clock (b) With enble

Figure 1-36 Correct Design Figure 1-35 Incorrect Design

Synchronous Design Principals (from page 34)

Method: All clock inputs to flip-flops, registers, counters, etc. are drivendirectly from the system clock or from the clock ANDed with acontrol signal.

Result: All state changes occur immediately following the active edge ofthe clock signal.

Advantage: All switching transients, switching noise, etc. occur between clockpulses and have no effect on system performance.

B A C0 0 Hi-Z0 1 Hi-Z1 0 01 1 1

A

B

C

(a)

B A C0 0 Hi-Z0 1 Hi-Z1 0 11 1 0

A

B

C

(b)

B A C0 0 00 1 11 0 Hi-Z1 1 Hi-Z

A

B

C

(c)

B A C0 0 10 1 01 0 Hi-Z1 1 Hi-Z

A

B

C

(d)

Figure 1-37 Four Kinds of Tristate Buffers

Reg. ALda

Ena

InputData

Clock

TRI-STATE BUSEni

Reg. BLdb

Enb

Reg. CLdc

Enc

8

8

Figure 1-38 Data Transfer Using Tristate Bus