eng2410 digital design lab #6 lab #6 sequential logic design (flip flops)
TRANSCRIPT
ENG2410 Digital Design
LAB #6 Sequential Logic Design
(Flip Flops)
ENG241/Lab #6 2
Lab Objectives
Understand the concept of sequential circuit.
Understand sequential circuit design flow. Design a simple D Flip Flop using VHDL.
ENG241/Lab #6 3
Part 1D Flip Flop
Design D-FF with asynchronous reset logic using VHDL.
Use an LED to display the output of the FF.
ENG241/Lab #6 4
Sample Sequential CircuitPositive Edge-Triggered D Flip-Flop
Note that this FF does not have a “reset” input
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
entity dff isport ( d , clk : in std_logic;
q , qbar : out std_logic);
end dff;
architecture behaviour of dff isbeginUp : process (clk,d)begin
if clk’even and clk = ‘1’ thenq <= d;qbar <= not d;
end if;end process;end behaviour;
Flip Flop
Clock
D Q
Q
Academic Misconduct
Reports and demos are submitted as a group, but it is a SINGLE group effort
You may talk with other groups but sharing codes or reports is NOT ALLOWED
Copying reports from previous years is also NOT ALLOWED
If we find copying we are REQUIRED to report it