ctemedia.s3.amazonaws.com · web viewlab exercise 4.3 decoders 65 lab exercise 4.4 encoders 68 lab...

`

DIGITALELECTRONICS

For C.A.D.E.T.™

Published by Global Specialties LLC,22820 Savi Ranch Parkway, Yorba Linda, CA 92887Copyright © 1987 by Preston Barber Written by Russell L. Heiserman & Preston Barber

All Rights Reserved. No part of this book shall be reproduced, stored in a retrieval system, or transmitted by any means, electronic, mechanical, photocopying, recording, or otherwise, without written permission from the publisher. No patent liability is assumed with respect to the use of information contained herein. While every precaution has been taken in the preparation of this book, the publisher assumes no responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained herein.

First Printing, 1987Revised, April 2009

345-3200

04/09

TABLE OF CONTENTS

iii

Introductory Concepts.............................................................. 11.0 Introduction..................................................................... 11.1 Objectives......................................................................... 11.2 Discussion ....................................................................... 2

1.2.0 Digital and Analog Circuits ................................ 21.2.1 Use of Binary Digital Ones and 2 leros.................. 51.2.2 Digital Circuits...................................................... 6

1.3 Summary.......................................................................... 81.4 Review Questions .......................................................... 8

Number Systems and Codes..................................................... 112.0 Introduction..................................................................... 112.1 Objectives......................................................................... 122.2 Discussion........................................................................ 12

2.2.0 The Binary Number System ............................. 132.2.1 Binary to Decimal Conversion ........................... 142.2.2 Decimal to Binary Conversion ........................... 142.2.3 The Hexadecimal Number System .................... 152.2.4 The Octal Number System ................................... 162.2.5 Binary Coded Decimal System ............................ 162.2.6 ASCII Code........................................................... 17

2.3 Summary.......................................................................... 192.4 Review Questions ........................................................... 19

Logic Gates and Boolean Algebra.............................................. 213.0 Introduction..................................................................... 213.1 Objectives......................................................................... 223.2 Discussion ....................................................................... 22

3.2.0 Boolean Variables ................................................ 223.2.1 Truth Tables.......................................................... 233.2.2 The OR Operation................................................. 243.2.3 The AND Operation ............................................ 243.2.4 The NOT Operation ............................................. 243.4.0 Logic Equations..................................................... 25

CHAPTER 1

CHAPTER 2

CHAPTER 3

iv

CHAPTER 4

CHAPTER 5

3.2.6 Logic Circuits........................................................ 263.2.7 NOR and NAND Gates ....................................... 28

3.3 Summary.......................................................................... 283.4 Review Questions ........................................................... 29Lab Exercise 3.1 The NOT Circuit (Inverter) ........................ 30Lab Exercise 3.2 The AND Gate............................................. 33Lab Exercise 3.3 The OR Gate................................................. 35Lab Exercise 3.4 The NAND Gate ......................................... 36Lab Exercise 3.5 The NOR Gate............................................... 37Lab Exercise 3.6 Using NAND and NOR Gates .................... 38

Combinational Loj;;ic Circuits ................................................. 414.0 Introduction..................................................................... 414.1 Objectives......................................................................... 414.2 Sum-of-ProductForm ..................................................... 424.3 Designing Combination Circuits .................................... 424.4 Boolean Sim plification ................................................... 444.5 DeMorgan's Theorem ..................................................... 454.6 The Karnaugh Map.......................................................... 464.7 Product-of-S urns Form ................................................... 514.8 The Exclusive OR and Exclusive NOR Circuits ........... 544.9 Summary......................................................................... 554.10Review Questions ........................................................... 55Lab Exercise 4.1 Minterm and Maxterm Truth Tables .......... 58Lab Exercise 4.2 Simplifying Logic Circuits........................... 61Lab Exercise 4.3 Decoders....................................................... 65Lab Exercise 4.4 Encoders........................................................ 68Lab Exercise 4.5 Exclusive OR Circuits.................................. 69Lab Exercise 4.6 The EXNOR Circuit..................................... 72

Flip-flops.................................................................................... 75vi

5.0 Introduction

755.1 Objectives 765.2 Discussion

76

5.2.0 Set-Clear Flip-flops .............................................. 775.2.1 The "D" Type Latch............................................... 795.2.2 Clod; Signals......................................................... 805.2.3 Clocked "S-C" Flip-flops....................................... 815.2.4 Clocked "T" Hip-flops ......................................... 825.2.5 Clocked "D" Flip-flops.......................................... 835.2.6 "J-K" Flip-flops...................................................... 84

vii

5.2.7 Counting and Frequency Division .................... 865.2.8 Monostable Multivibrators................................... 87

5.3 Summary.......................................................................... 875.4 Review Questions............................................................ 88Lab Exercise 5.1 Set-Clear Flip-flops....................................... 90Lab Exercise 5.2 The "D" Latch .............................................. 93Lab Exercise 5.3 The Clocked Set-Clear Filp-flops ................ 95Lab Exercise 5.4 The "T" Flip-flops......................................... 97Lab Exercise 5.5 The Clocked "D" Flip-flops; .......................... 98Lab Exercise 5.6 The "J-K" Flip-flops ...................................... 100Lab Exercise 5.7 The One-Shot................................................ 102

Digital Arithmetic..................................................................... 1056.0 Introduction...................................................................... 1056.1 Objectives.......................................................................... 1056.2 Discussion......................................................................... 106

6.2.0 Binary Addition.................................................... 1066.2.1 Signed Numbers................................................... 1066.2.2 Complement Notation.......................................... 1076.2.3 Binary Multiplication........................................... 1086.2.4 Binary Division..................................................... 1106.2.5 Hexadecimal Arithmetic...................................... 1116.2.6 BCD Addition....................................................... 1116.2.7 The Half-adder..................................................... 1126.2.8 Full-adder............................................................. 1136.2.9 Parallel Binary Adder........................................... 1136.2.10 BCD Adder........................................................... 1146.2.11 Binary Multipliers ................................................ 115

6.3 Summary.......................................................................... 1156.4 Review Questions ............................................................ 115Lab Exercise 6.1 Binary Adders............................................... 117Lab Exercise 6.2 Parallel Binary Adder.................................. 118Lab Exercise 6.3 The BCD Adder............................................. 121Lab Exercise 6.4 The ALU....................................................... 123

Counters and Registers............................................................. 1277.0 Introduction...................................................................... 1277.1 Objectives.......................................................................... 1277.2 Discussion......................................................................... 128

7.2.0 Ripple Counters.................................................... 1287.2.1 MOD Counters..................................................... 129

CHAPTER 6

CHAPTER 7

ix

CHAPTER 8

7.2.2 Down Counters..........................................130

7.2.3 Parallel Counters.......................................131

7.2.4 Parallel UP/DOWN Counter .....................131

7.2.5 Presetable Counters..................................132

7.2.6 IC Binary UP/DOWN Counter ..................133

7.2.7 Counter Decoding.....................................133

7.2.8 Shift Registers...........................................134

7.2.9 Johnson Counter .......................................135

7.2.10Integrated Circuit Registers.....................136

7.3 Summary.............................................................140

7.4 Review Questions................................................140

Lab Exercise 7.1 UP/DOWN Counters.............................................................................................143

Lab Exercise 7.2 Synchronous Counters...................................................................................145

Lab Exercise 7.3 IC Counters..........................................................................................................146

Lab Exercise 7.4 Shift Registers......................................................................................................149

Lab Exercise 7.5 The 74165.............................................................................................................152

Lab Exercise 7.6 The 74164.............................................................................................................154

Integrated Circuit Logic Families ...........................................................................................................157

8.0 Introduction..............................................•........157

8.1 Objectives...........*...............................................157

8.2 Discussion...........................................................158

8.2.0 Terminology..............................................1588.2.1 TTL Logic Family.......................................159

x

8.2.2 Standard TTL Logic Characteristics1618.2.3 TTL Loading Rules

1628.2.4 Using Specification Sheets

1628.2.5 Open Collector Outputs1648.2.6 Three-State Logic1688.2.7 Other TTL Families 1698.2.8 The MOSFET1708.2.9 CMOS1718.2.10Interfacing CMOS

and TTL ..............................................................1728.2.11..................................................................ESD Control................................................................173

8.3 Summary................................;.......•..................173

8.4 Review Questions ..............................................173

Lab Exercise 8.1 TTL Loading Rules ...............................................................................................175

Lab Exercise 8.2 Open-Collector Logic Gates..................................................................................176

Lab Exercise 8.3 Three-State Logic ................................................................................................177

Lab Exercise 8.4 TTL and CMOS Interfacing..................................................................................179

xi

Medium Scale Integration......................................................... 1819.0 Introduction..................................................................... 1819.1 Objectives......................................................................... 1819.2 Discussion........................................................................ 181

9.2.0 Decoders............................................................... 1829.2.1 BCD-to-Decimal Decoder..................................... 1829.2.2 BCD-to-Seven Segment Display Decoders ........ 1839.2.3 Common Displays ............................................... 1849.2.4 Encoders............................................................... 1869.2.5 Multiplexers ........................................................ 1879.2.6 Demultiplexers..................................................... 1919.2.7 3-State Registers .................................................. 193

9.3 Summary......................................................................... 1939.4 Review Questions ........................................................... 193Lab Exercise 9.1 Decoders....................................................... 195Lab Exercise 9.2 Decoder/Drivers.......................................... 197Lab Exercise 9.3 Encoders....................................................... 199Lab Exercise 9.4 Digital Multiplexers .................................... 201Lab Exercise 9.5 Demultiplexers............................................. 203

Data Conversion/Acquisition ............................................... 20510.1 Introduction...................................................................,. 20510.1 Objectives......................................................................... 20510.2Discussion......................................................................., 206

10.2.0 D/A Conversion................................................... 20610.2.1 D/A Specifications............................................... 20910.2.2 D/A Applications................................................. 21010.2.3 A/D Conversion .................................................. 21110.2.4 Successive Approximation A/D.......................... 21210.2.5 Data Acquisition .................................................. 21310.2.6 Sample and Hold Circuits ................................... 21310.2.7 Multiplexing......................................................... 214

10.3Summary.......................................................................... 21510.4Review Questions .......................................................... 216Lab Exercise 10.1 D/A Converters......................................... 217Lab Exercise 10.2 A/D Converters......................................... 219Lab Exercise 10.3 The Analog Multiplexer .......................... 221

Potpourri.................................................................................... 22511.0Introduction .................................................................... 22511.1Objectives......................................................................... 225

CHAPTER 9

CHAPTER 10

CHAPTER 11

CHAPTER 12

APPENDIX

11.2Discussion.............................................................22611.2.0...................................................................The 555 Timer............................................................ 22611.2.1...................................................................Opto-Isolators.............................................................. 22711.2.2...................................................................DIP Relays.................................................................. 22711.2.3...................................................................Programmable Logic Devices .................................... 228

11.3............................................................................Summary........................................................................... 23111.4............................................................................Review Questions ............................................................ 231Lab Exercise 11.1 The 555 Timer.............................. 232Lab Exercise 11.2 DIP Relays.................................... 234Lab Exercise 11.3 The Opto-Isolator......................... 236Lab Exercise 11.4 Implementing Logic Functions

with ROMS.......................................................... 238

Microcomputer Concepts ........................................ 24112.0............................................................................Introduction....................................................................... 24112.1............................................................................Objectives......................................................................... 24112.2............................................................................What is a Microcomputer? ................................................. 242

12.2.0 Organization of the Microcomputer ...... 24312.2.1 Interfacing.............................................. 247

12.2.1.0 Parallel and Serial Data Transmission 249

12.2.2Programming ..................................................... 251

12.2.2.0...................................................Machine Code................................................ 25212.2.2.1...................................................Assembly Language....................................... 25412.2.2.2...................................................High Level Language...................................... 255

12.3........................................................................Summary .........................................................................25712.4............................................................................Review Questions ............................................................ 257

Pinouts of ICs Used in the LK-1 Kit ...................... 259

FIGURE 1-1. Typical Analog Signals ....................... 2FIGURE 1-2. Typical Digital Signals or Words ........ 4FIGURE 1-3. Comparison of Binary and Decimal

Numbers............................................... 6FIGURE 1-4. Schematic Diagram of a Digital Switch .....................................................................................6FIGURE 1-5. BJT (Bipolar Junction Transistor)

Inverter................................................. 7FIGURE 2-1. Structure of a General Positional

Number System.................................... 12FIGURE 2-2. Converting 214 Decimal to Binary ..... 15FIGURE 2-3. Binary to Hexadecimal Number

System Conversion .............................. 16FIGURE 2-4. Binary/Octal Number System

Conversions ......................................... 16FIGURE 2-5. Decimal Number Coded in BCD ......... 17FIGURE 3-1. Truth Tables........................................ 23FIGURE 3-2. Truth Table for the OR Operation ...... 24FIGURE 3-3. Logical AND Truth Table..................... 24FIGURE 3-4. Truth Table for the NOT Operation .... 25FIGURE 3-5. Schematic Symbols for Boolean

Equations.............................................. 27FIGURE 3-6. Designing Circuit from Logic Equations ..................................................................................... 27FIGURE 3-7. Schematic Symbols for NAND and

NOR Gates............................................ 28FIGURE 3-8. IC Orientation and Pin Numbering . . . 31FIGURE 3-9. Basing Diagram for 74LS04 IC........... 32FIGURE 3-10A. HIGH Pulse Circuit............................. 32FIGURE 3-10B. LOW Pulse Circuit............................... 32FIGURE 3-11. Circuit Schematic................................ 38FIGURE 3-12. Circuit Schematic................................ 39FIGURE 4-1. Circuit Implementation of Minterm

Expression............................................ 44FIGURE 4-2. A Simplified Alarm Logic Circuit ........ 45FIGURE 4-3. DeMorgan's Theorem.......................... 45FIGURE 4-4. Logic Expressions, Truth Tables and

K-Maps for Two, Three and Four InputVariables............................................... 46

FIGURE 4-5. Examples of Looping.................t.............. 48FIGURE 4-6. K-Map Simplification Examples ......... 49FIGURE 4-7. K-Map Applied to Ink Factory

Alarm Problem...................................... 50FIGURE 4-8. Don't Care Conditions in K-Map

Simplification ...................................... 50

ILLUSTRATIONS

xiv

FIGURE 4-9. Examples of Product-of-Sums LogicEquation.................................................................................................................51

FIGURE 4-10. Steps in Creating the Product-of-SumsLogic Equation.......................................................................................................52

FIGURE 4-11. Implementation of the Equations inFigure 4-10.............................................................................................................53

FIGURE 4-12. Logic Implementation UsingUniversal Gates .....................................................................................................53

FIGURE 4-13. The Exclusive OR Gate and ExclusiveNOR Gate................................................................................................................55

FIGURE 4-14. K-Maps.................................................. 55FIGURE 4-15. Outputs for XOR and XNOR Gates........ 57FIGURE 4-16. Examples of Minterm Truth Tables ..... 58FIGURE 4-17. Examples of Maxterm Truth Tables ..... 59FIGURE 4-18. Truth Table for Lab Exercise 4.2.......... 62FIGURE 4-19. Step 7 Circuit Schematic ..................... 63FIGURE 4-20. Two Variable Karnaugh Map ............... 63FIGURE 4-21. Schematic of a Simple Decoder ........... 66FIGURE 4-22. Schematic for a One of Four Decoder . 66FIGURE 4-23. Schematic for a Simple Encoder........... 68FIGURE 4-24. EXOR Truth Table................................. 70FIGURE 4-25. EXOR Schematic #1 ............................ 70FIGURE 4-26. EXOR Schematic #2............................. 71FIGURE 4-27. The EXNOR Circuit .............................. 73FIGURE 5-1. OR Gate Latch....................................... 76FIGURE 5-2. NOR Gate Latch.................................... 77FIGURE 5-3. NOR "S-C" Flip-flop .............................. 77FIGURE 5-4. Basic NAND Latch................................ 78FIGURE 5-5. NAND "S-C" Latch ............................... 79FIGURE 5-6. NOR "D" Latch...................................... 79FIGURE 5-7. NAND "D" Latch ................................... 80FIGURE 5-8. Clocked "S-C" Flip-flop.......................... 81FIGURE 5-9 Clocked "T" Flip-flop............................. 82FIGURE 5-10. Timing Diagram for "T" Flip-flop .......... 82FIGURE 5-11. Clocked "D" Flip-flop ............................ 83FIGURE 5-12. "J-K" Flip-flop ..............................................................................................................................84FIGURE 5-13. "J-K" Hip-flop Configurations .....................................................................................................85FIGURE 5-14. "J-K" Master-slave Flip-flop Circuit

Diagram..................................................................................................................85

FIGURE 5-15. Schematic Symbol for Edge TriggeredFlip-flop..................................................................................................................90

xv

FIGURE 5-16. Edge Trigger Circuits............................ 91FIGURE 5-17. Schematic for NOR "S-C" Flip-flop ....... 91FIGURE 5-18. Schematic for NAND "S-C" Flip-flop .... 92FIGURE 5-19. Schematic for "D" Flip-flop ................... 93FIGURE 5-20. Schematic for Clocked "S-C" Flip-flop .. 96FIGURE 5-21. Schematic for "T" Flip-flop ................... 97FIGURE 5-22. Schematic for Clocked "D" Flip-flop ..... 99FIGURE 5-23. "J-K" Flip-flop Schematic ...................... 100FIGURE 5-24. Schematic for Step Seven .................... 101FIGURE 5-25. "One-Shot" Schematic........................... 102FIGURE 6-1. Rules of Binary Addition ....................... 106FIGURE 6-2. Example of Signed Numbers ................ 106FIGURE 6-3. Rules for Binary Subtraction.................. 107FIGURE 6-4. Examples of Complement Notation ...... 107FIGURE 6-5. Subtraction Using Two's Complement

Notation.................................................. 108FIGURE 6-6. Example of Multi-Digit Binary

Multiplication......................................... 109FIGURE 6-7. Alternate Method for Multiplying Binary

Numbers ................................................ 109FIGURE 6-8. Alternate Method for Division .............. 110FIGURE 6-9. Binary Division by the Restoring Method ......................................................................................IllFIGURE 6-10. BCD Addition Examples........................ IllFIGURE 6-11. Half-Adder............................................. 112FIGURE 6-12. Full-Adder.............................................. 113FIGURE 6-13. Parallel Adder IC................................... 114FIGURE 6-14. BCD Adder Circuit................................. 114FIGURE 6-15. Half-Adder Schematic........................... 117FIGURE 6-16. Full-Adder Schematic ........................... 118FIGURE 6-17. Parallel Binary Adder Circuit ............... 119FIGURE 6-18A. BCD Adder Circuit................................ 122FIGURE 6-18B. Display Circuit...................................... 122FIGURE 6-19. 74181 Adder.......................................... 124FIGURE 7-1. Examples of Ripple Counters ............... 128FIGURE 7-2. Count Rate Formula ............................. 129FIGURE 7-3. Clock and Strobe Pulses........................ 129FIGURE 7-4. Examples of Down Counters ................ 130FIGURE 7-5. Parallel Counter Circuit ....................... 131FIGURE 7-6. Parallel Up/Down Counter ................... 132FIGURE 7-7. Presetable Counter................................ 133FIGURE 7-8. "J-K" Flip-flop Shift Register ................ 134FIGURE 7-9. "D" Rip-flop Shift Register ................... 135

xvi

FIGURE 7-10. Johnson Counter ................................... 136FIGURE 7-11. 74174 Logic Diagram............................ 137FIGURE 7-12. 74174 PIPO Shift Register.................... 138FIGURE 7-13. 7494 Logic Diagram.............................. 139FIGURE 7-14. 74165 Logic Diagram............................ 139FIGURE 7-15. 74164 Logic Diagram............................ 140FIGURE 7-16. Up Counter............................................ 143FIGURE 7-17. Synchronous Up Counter ..................... 145FIGURE 7-18A. Decade Counter.................................... 147FIGURE 7-18B. Seven Segment Display........................ 147FIGURE 7-19. 4-Bit Binary Up/Down Counter ............ 148FIGURE 7-20. SISO Shift Register............................... 150FIGURE 7-21. 74174 PIPO Shift Register.................... 151FIGURE 7-22. 74165 PISO Shift Register.................... 153FIGURE 7-23. 74164 SIPO Shift Register ................... 154FIGURE 8-1. Typical Pulse Signal ............................. 158FIGURE 8-2. Diode Logic Gates................................. 160FIGURE 8-3. Basic TTL Circuit................................... 160FIGURE 8-4. Sinking and Sourcing Current ............. 161FIGURE 8-5. Simple Inverting Amplifier Output ....... 164FIGURE 8-6. Totem-Pole Output Amplifier ............... 165FIGURE 8-7. Open Collector TTL Gate....................... 166FIGURE 8-8. Examples of Wired Logic ...................... 166FIGURE 8-9. Three-State Logic ................................. 168FIGURE 8-10. Schottky Barrier Diode Circuits .......... 169FIGURE 8-11. MOSFET Construction ......................... 170FIGURE 8-12. Methods of Interfacing TTL and CMOS ......................................................................................172FIGURE 8-13. CMOS/TTL Interfacing ......................... 180FIGURE 8-14. TTL/CMOS Interfacing ......................... 180FIGURE 9-1. BCD to Decimal Decoder Logic Diagram ......................................................................................182FIGURE 9-2. Seven-Segment Display Labeling ......... 183FIGURE 9-3. Logic Diagram BCD to Seven Segment

Decoder-Driver IC................................... 184FIGURE 9-4. Decimal to BCD Encoder ...................... 186FIGURE 9-5. 8-Line to 3-Line Priority Encoder ......... 187FIGURE 9-6. Simple Multiplexer Logic Diagram ...... 188FIGURE 9-7. Parallel to Serial Conversion Using a

Multiplexer ............................................ 188FIGURE 9-8. 8-Input MUX Logic Diagram ................ 189FIGURE 9-9. Multiplexer Used as a Boolean Function

Generator................................................ 190FIGURE 9-10. Simple Demultiplexer ........................... 191

xvii

FIGURE 9-11. Serial to Parallel Conversion Usinga Demultiplexer ..................................... 192

FIGURE 9-12. BCD/DEC Decoder................................ 196FIGURE 9-13. BCD/7-Segment Decoder ..................... 198FIGURE 9-14. 8-Line to 3-Line Encoder ...................... 200FIGURE 9-15. Simple Multiplexer ............................... 202FIGURE 9-16. Simple Demultiplexer ........................... 203FIGURE 10-1. Basic D/A Converter Block Diagram . . . 206FIGURE 10-2. Simple D/A Converter .......................... 207FIGURE 10-3. Binary Ladder D/A Converter .............. 208FIGURE 10-4. Ladder Analysis for A4.......................... 209FIGURE 10-5. Flash A/D Converter ............................ 211FIGURE 10-6. Successive Approximation A/D

Converter ............................................... 212FIGURE 10-7. Sample and Hold Circuit....................... 213FIGURE 10-8. Rotary Switch ....................................... 214FIGURE 10-9. Typical Data Acquisition Systems ........ 215FIGURE 10-10. Simple D/A Converter ........................ 218FIGURE 10-11. A/D Converter .................................... 220FIGURE 10-12. MUX Circuitry..................................... 222FIGURE 11-1. 555IC Basing and Circuit Diagrams ..... 226FIGURE 11-2. PAL Architecture .................................. 228FIGURE 11-3. ROM Architecture ................................ 229FIGURE 11-4. PCA Architecture................................... 230FIGURE 11-5. One-Shot Circuit ................................... 232FIGURE 11-6. Astable Circuit....................................... 233FIGURE 11-7. DIP Relay............................................... 234FIGURE 11-8. Opto-Isolator TTL/CMOS Converter..... 236FIGURE 11-9. Programming Circuit ............................ 238FIGURE 12-1. Computer Families ............................... 242FIGURE 12-2. Generalized Microcomputer ................. 244FIGURE 12-3. Parallel Port Functional Diagram ......... 249FIGURE 12-4. Serial Port Functional Diagram ........... 250FIGURE 12-5. Industry Standard Data Bus Definitions ......................................................................................251

xviii

TABLES

TABLE 2-1. Structure of the Binary Number System ......................................................................................14TABLE 2-2. Converting 11010110 Binary to Decimal 214 14TABLE 2-3. Additional Digits for the Hexadecimal

System........................................•.......... 15TABLE 2-4. Excess-3 BCD Code............................... 17TABLE 2-5. ASCII Code............................................ 18TABLE 3-1. Basic Laws of Boolean Algebra............. 26TABLE 4-1. Truth Table and Minterm Expression . . 43TABLE 4-2. Boolean Theorems ................................ 44TABLE 8-1. TTL Characteristics.....................................................................................................................161TABLE 8-2. Typical TTL Parameters..............................................................................................................164TABLE 8-3. CMOS Logic Characteristics.......................................................................................................171TABLE 9-1. Boolean Products of an 8-Bit Multiplexer ......................................................................................190TABLE 11-1. Data Table...................................................................................................................................239

WARNINGFEDERAL REGULATION (PART 15 OF FCC

RULES) PROHIBITS THE USE OF COMPUTING EQUIPMENT WHICH CREATES RADIO OR TV

INTERFERENCE

Global Specialties LLC specifically warns the user of this instrument that it is intended for use in a classroom or laboratory environment for the purpose of learning and experimentation. When building experimental circuits, it may emit interference that will effect radio and television reception and the user may be required to stop operation until the interference problem is corrected. Home use of this equipment is discouraged since the likelihood of interference is increased by the close proximity of neighbors.

CORRECTIVE MEASURES:Interference can be reduced by the following practices.

1) Install a commercially built RFI power filter in the power line at the point where the cord enters the unit.

2)Avoid long wires. They act as antennas.

1) If long wires must be used, use shielded cables or twisted pairs which are properly grounded and terminated.

xx

PREFACEThis book is meant to serve as the text/lab book for a first course in digital electronics. The object of the course is to help you become familiar with the use of digital electronic circuits. After completing the course, the student should be able to design, construct, and effectively troubleshoot digital electronic circuits.

Each chapter of the book contains clearly stated objectives that the student will be able to perform when the chapter is completed. The objectives are followed by text which discusses the subject of the chapter. The text is followed by questions to test the student's understanding of the material. After the questions, most chapters will have several experiments which will demonstrate and reinforce the subjects covered in the chapter.

The course is structured so that most of the material is actually learned in the laboratory. Figures are used generously throughout the text to provide clarity. All parts used in the laboratory are available from E & L Instruments or their local representative. The course is designed so that most contemporary topics in digital electronics are addressed.

The authors would like to hear from you regarding the effectiveness of the material included in the text and the organization of the material.

NOTEThe EEPROM 2864,4N35 Opto-Isolator and the Dip Relay used in chapter 11 are not supplied by Global Specialties LLCas part of the Digital Parts Kit (LK-1). It must be purchased separately.

xxii

INTRODUCTION

xxiv

If you have never used the CADET trainer then the following theory and HANDS-ON exercises will help you get started right. This will be a systematic overview of the features and operation of the CADET. Refer back to this information as you perform the experiments if you forget how a certain section of the trainer operates. Both general information and information dealing specifically with using the CADET trainer in digital experiments will be found on the next few pages. Time spent here... will be time well spent.

So here goes!

As you look at the trainer there is a large white area in the center full of holes called "tie points" or "contact points". This is the breadboarding area and it is not connected to any circuitry underneath the surface of the trainer EXCEPT the top two strips. They are internally connected to the power supply. We will talk more about these two strips later.

This breadboarding area is where you will place your components. Describing this area is more difficult than understanding it. There are actually three separate breadboards or sockets in the center of the trainer. Let's look at just one of them. Pick any one of the three and notice there is a sort of valley or divider running vertically up the center of it. To the left and right of this divider are many rows of five holes or tie points. Inside the plastic there is a metal strip electrically connecting all five of the points in each row together. No row of tie points is connected to any other row however. Each row is independent. If you connect several devices such as resistors, capacitors, etc. to several of the tie points in the same row, these devices are electrically connected together. When placing integrated circuits or chips on the breadboard socket the pins of the chip should straddle the valley running up the center or else pins on opposite sides of the chip will be shorted together.

On the far left and right sides of each breadboard or socket you will notice two vertical columns of tie points in groups of five. The far left column of points, from the top down to the center mounting screw, are all connected together by metal embedded in the plastic. From the

Getting Strarted

Breadboard Sockets

xxv

Breadboard Sockets On Hand

Breadboard Sockets Summary

center mounting screw, down to the bottom of the socket, all tie points are likewise connected together. The other column on the left side is arranged the same way. From the top down to the center mounting screw all points are connected, and likewise from the center mounting screw down to the bottom. On the far right side of each breadboard socket there are two columns of tie points arranged the same as the left side. Notice that none of the columns are connected to each other. Often these tie points are connected with wires to the power strips at the top of the trainer and are used as convenient places to provide power to each circuit or chip.

Set your VOM or DMM to the Rxl range. Connect wires to the probes. (It will be very helpful to have meter leads which have alligator clips or some other type of end which will hold on to wires.) Try checking the resistance between any two tie points in a row of five. DO NOT ATTEMPT TO MEASURE TFIE RESISTANCE OF THE TIE POINTS IN THE TWO NARROW BREADBOARD STRIPS LOCATED AT THE TOP OF THE TRAINER THESE ARE CONNECTED TO POWER. YOU MAY DAMAGE YOURMETER BY CONNECTING IT TO A VOLTAGE WHILE IT IS SET TO MEASURE RESISTANCE! You should find zero ohms of resistance between any two tie points in a row. Measure the resistance across the divider running up the center of the breadboard. You should find infinite resistance. Do the same in the vertical columns on the left and right side of each breadboard or socket. You should find continuity between all tie points in any one column as long as both leads are either above the center mounting screw or below it.

IT IS VERY IMPORTANT TO UNDERSTAND EXACTLY HOW THE TIE POINTS ON THE BREADBOARDS ARE ARRANGED! It is not possible to successfully construct circuits unless you know which tie points are electrically connected together and which are not.

Experiment with the tie points on the main breadboards until you have a good understanding of how they are arranged.

Horizontal rows of five are the same point electrically. Vertical columns of fifty, above and below the center mounting screw, are the same point electrically.

xxvi

At the very top of the breadboard area are two horizontal connector strips of breadboarding material. To their right are lines printed on the surface of the trainer indicating that they are connected to the power supply. The top row of 50 tie points go to the +5V part of the supply. The second row is connected to the +1.3-15V part of the supply. Both of these rows are on the top horizontal breadboard strip. Now look at the next strip down. The top row of tie points on this strip is connected to the -1.3-15V supply and the bottom row are connected to ground. Each of the circuits used in these experiments require power to operate and this is where you'll get it from.

At the top of the trainer above the power connector strips are two voltage adjustments. One labeled+V and the other-V. The voltage of the +1.3-15V tie points is adjusted within this range by the +V adjustment. The voltage of the -1.3-15V tie points is adjusted within this range by the -V adjustment. Most of the digital experiments will use +5V and ground so you may not use these adjustments too often. Be careful to use the correct voltage for each experiment.

At the top center of the trainer is a center tapped 12.6VAC voltage source. Note that this is AC, not DC. This source has been included primarily for analog experiments normally done in other courses.

Let's use our VOM or DMM to check these voltages. Turn the CADET's power switch on. Set your meter to be able to read at least 5V DC. Insert a wire in the bottom row of the power connector strips, the one which is connected to ground. Connect the ground lead of your VOM to this wire. Now insert a wire in the top row of the power connector strips, the one which is connected to +5V. Connect the red or positive lead of your VOM to this wire. Your meter should indicate approximately 5V. If the needle of the VOM tries to go backwards you have the leads of your meter reversed. Now using a Phillips screwdriver carefully turn the +V and then the -V adjustment screws at the top of the trainer.

THESE ADJUSTMENTS ARE PLASTIC. BE CAREFUL NOT TO DISTORT THE SCREWDRIVER SLOTS BY APPLYING TOO MUCH FORCE WHEN YOU REACH THE END OF THE ROTATION.

Notice that the voltage indicated on the VOM does NOT change. The +5V power supply is not adjustable.

Now adjust your VOM to be able to read up to 15VDC. Remove the wire from the +5V row and insert it into the +1.3-15V row which is next

Power Supply

Power Supply Hands On

xxvii

Power Supply

Summary

Logic Indicators

down from the top. Again, using a Phillips screwdriver turn the +V adjustment screw. The lowest voltage indicated should be a little over IV. The highest voltage may be as high as 20V.

Turn off the trainer. If your meter has a polarity reversing switch use that now. It not, reverse the positive and ground leads of your meter. Move the wire which is in the + 1.3- 15V tie point to the -1.3-15V tie point. Turn the trainer on again. Turn the-V adjustment screw. Your meter should again indicate between a little over IV and 20V. If your meter needle tried to go backwards reverse the meter leads.

Power can be gotten directly from the red, blue, yellow, and black binding posts on the top of the trainer in addition to the power connector blocks if desired. The colored part can be tightened down onto a wire placed in the hole in the post or a banana plug may be inserted into the top of the post.

Finally, check the voltage of the 12.6 VAC connection at the very top of the trainer. Remember, this is AC, not DC, set your meter accordingly. Between the center lead and either of the outside leads you'll find 6.3 VAC and between the two outside leads there will be 12.6 VAC.

Two continuously variable DC power supplies are available which provide voltages in the range of +1.3-15V and -1.3-15V giving a full 30 V range. In addition a fixed +5 V supply is always available. AC voltages of 6.3 and 12.6 are provided.

Let's look now at the logic indicators on the right side of the trainer. A small connector block allows these LED's to be connected to the rest of the circuit being constructed. There are eight red LED's at the top of this section and eight green LED's at the bottom. The red LED's indicate a high or "1" logic level. The green LED's indicate a low or "0" logic level. The indicators work in pairs shown by the numbering from one to eight. Each pair has two tie points on the small connector block to the left. It doesn't matter which of the two tie points you use.

The +5/+V switch in the upper left corner of this section determines the voltage to be connected to the logic indicators and should be the same as the circuitry to which the indicators are connected. The switch in the bottom left corner of this section determines the threshold voltages for the indicators. When the +5/+V switch is in the +5 position the TTL/CMOS switch should be in the TTL position. This is the TTL/+5V mode. When the +5/+V switch is in the +V position the TTL/CMOS switch should be in the CMOS position. This is the CMOS/+V mode.

xxviii

When in the TTL/+5V mode, if the voltage connected to a pair of LED's is 2.2 volts or higher the red indicator will light. If the voltage is .8 volts or less the green indicator will light. If the voltage is between 2.2 and .8 volts or there is no voltage then neither will light. When in the CMOS/+V mode, if the voltage connected to a pair of LED's is 70% of the selected voltage or higher then the red indicator will light. If the voltage is 30% or less than the selected voltage then the green indicator will light. If the voltage is between 30% and 70%, or if there is no voltage, then neither LED will light.

Place the top switch in this section in the +5V volt position and the bottom switch in the TTL position. Connect a wire from the +5V supply to the #1 LED pair. The red LED will light. Now connect the wire to the ground point in the supply and the green LED will light.

To demonstrate the voltages necessary for a logic 1 and a logic 0 try this. Select the+5V/TTL mode in the Logic Indicators section, that is, both switches in that section are up. Locate the two pots at the bottom of the trainer. Connect a wire from the #8 LED pair to the center (#2) tie point of the IK pot. Connect the left (#1) terminal of the pot to ground. Connect the right (#3) terminal of the pot to+5V. If you rotate the pot fully counterclockwise the green LED will light. If you rotate the pot fully clockwise the red LED will light. There is an area between these two extremes in which neither LED will light.

Adjust your VOM to be able to read 5V DC or more. Connect the ground lead of your VOM to the ground of the power supply. Connect the positive lead of your VOM to the center (#2) tie point of the IK pot (where you already have your LED connected). Now, turn the pot fully counterclockwise. The green LED is lit. Turn the pot slowly clockwise, until the green LED goes out. Move slightly back and forth with the pot until you find the exact spot where the green LED lights. Look at the reading on your VOM. It should be close to .8V. Continue to rotate the pot clockwise until the red LED lights. Again go back and forth until you find the exact spot where the red LED lights. Check your VOM. It should indicate approximately 2.2.

If desired, this same type of experiment could be done in the +V/ CMOS mode also. Check the voltage adjustment when you begin the experiment and remember that the green LED will light at approximately 30% of that value and the red LED will light at approximately 70% of that value.

Logic Indicators Hands On

xxix

Logic Indicators Summary

Speaker

Speaker Hands On

BNC Connec

tor

Switches

Switches Hands On

Each LED pair indicates the presence of a logic 1 with the red LED. A logic 0 is shown with the green LED. And undefined values between logic 1 and 0, as well as no voltage at all, are indicated by neither LED lighting.

Next we find an 8 ohm speaker. Each of the two speaker leads has four tie points on the connector block.

When you reach the section about the Function Generator you will have an opportunity to test the speaker.

At the bottom right corner of the trainer is a BNC connector. This connector will allow you to use the CADET with oscilloscopes or other test equipment without using clip leads. Attach a wire from one of the eight tie points for the BNC connector to whatever place on the breadboard you wish to connect your test instrument to. You will be able to have your test equipment attached without a tangle of leads in your breadboard area.

Two single-pole double-throw slide switches have been provided on the lower side of the CADET toward the right. The lines printed on the trainer indicate these switches have three leads. When the switch is in the "up" position the middle and top leads are connected. When in the "down" position the middle and bottom leads are connected. The top and bottom leads of each switch have two tie points on the connector block and the middle lead has four tie points.

Insert a wire into the right (#3) tie point of the right (#10) SPDT switch on the bottom of the trainer. Insert another wire into the center (#2) tie point of the same switch. Note that according to the lines printed on the surface of the trainer the center pin of the switch is connected to the center tie point. The top pin of the switch is connected to the right tie point. Set your VOM or DMM on its lowest resistance range (Rxl). Connect the leads of your meter to the two wires. (Remember to zero the ohms adjust.)

xxx

Move the switch into the up position and the meter will show zero ohms indicating you have continuity between the center and top pins of the switch. Move the switch to the down position and the meter will show infinite resistance indicating no connection between the center and bottom pins of the switch.

Now, leaving the meter leads connected to their wires move the wire in the right (#3) tie point over to the left (#1) tie point of switch #10. Move the switch into the down position and the meter will show zero ohms indicating continuity between the center and bottom pins of the switch. Move the switch to the up position and the meter will show infinite resistance indicating no connection between the center and top pins of the switch.

Switch #9 is the same as switch #10 except that the tie point numbers for the bottom and top pin connections are reversed.

The operation of the SPDT switches can be summarized by the following statements. When the switch is in the "up" position it connects the center and top pins of that switch. When in the "down" position it connects the center and bottom pins of that switch.

Two pots can be found at the bottom center of the CADET. The one on the left is a 10 k ohm pot and the one on the right is 1 k ohm. The center adjustable lead on each has four tie points and the two fixed leads have two tie points each.

Connect a wire into the left (#1) tie point of the IK pot at the bottom of the trainer. Connect another wire into the middle (#2) tie point of the same pot. Notice that according to the lines printed on the surface of the trainer the #1 tie point is connected to the left side of the resistance which makes up the pot. The #3 tie point is connected to the right side of the resistance which makes up the pot. The center (#2) lead is adjustable.

Set your VOM so that 1,000 ohms will register toward the left side of the ohms scale. (The RxlO range will probably be appropriate.) Zero it with the ohms-adjust control. Connect the leads of the meter to the two wires.

If you rotate the pot fully counterclockwise (toward the left) the meter will show approximately 0 ohms. This indicates the center adjustable contact of the pot is very close to the left lead and the current is flowing through very little resistance.

Switches Summary

Potentiometers

Potentiometers Hands On

xxxi

Potentiometers Summary

Logic Switches

Logic Switches Hands On

Turn the pot fully clockwise (towards the right) and the meter will indicate approximately 1,000 ohms. This indicates that the center adjustable lead is near the far right side of the resistance element inside the pot and the current must flow through the entire IK resistance path.

Rotate the pot to the 12 o'clock position (the halfway position). The meter will indicate half of the full 1,000 ohms. That is 500 ohms. (Remember, the needle does not actually move half way up the scale because a resistance scale is non-linear.)

The 10K pot is set up the same except that it has 10,000 ohms of resistance.

As you rotate a pot in either direction, resistance between the center lead and the one which you are moving towards will decrease. Resistance between the center lead the the one which your are moving away from will increase.

On the lower part of the trainer toward the left side are eight sliding type logic switches. Each has two tie points on the connector block above the switches. When a logic switch is in its down position it is placing its tie point on the connector block at logic 0 or ground. When in the up position it places its tie point at logic 1. Just exactly what voltage logic 1 is depends on several factors. In the upper left corner of this area is a switch labeled +V and +5. If this is in the +5 position then a high or 1 for the logic switches at this time is +5 volts. If the voltage selection switch is in the +V position then a high or 1 will be determined by the setting of the +V adjustment on the top of the trainer. Be careful to use the correct voltage for each experiment.

Turn on the CADET. Place the voltage selection switch in the Logic Switches section in the up or +5 V position. Set your meter to read at least 5 VDC. Connect the ground lead of the meter to the ground of the power supply. Connect the positive lead of the meter to the tie point for logic switch #8. Put the logic switch in the down position. Your meter should indicate 0 VDC. Move the switch to the up position. The meter should now indicate approximately 5 VDC. Move the switch back to the down position.

Look at the Logic Indicators section and move the top switch to the +5 V position and the bottom switch to the TTL position if they are not already in those positions. You are now in the +5V/TTL mode.

xxxii

While leaving the meter attached to one of the tie points for logic switch #8, attach a wire from the other tie point for that same switch to logic indicator #8. The green or low logic indicator should light. Move the logic switch to the up position and the red or high LED should light. Take note of the fact that logic 1 at this time is +5 VDC. Move the logic switch back to the down position.

Adjust your meter to be able to read at least 20 VDC. Temporarily connect the positive lead of your meter to the +V power supply and adjust the supply to 15 volts. Now move the positive lead of your meter back to the tie point for logic switch #8. Turn off the trainer. Move the voltage selection switch in the Logic Switches area to the +V position. Move the voltage selector switch in the Logic Indicators section to the +V position also. Move the bottom switch in the Logic Indicators section to the CMOS position. You are now in +V/CMOS mode.

Turn the CADET back on. Notice the numbers 1 and 0 printed on the surface of the CADET on the left side of the logic switches. A1 is shown as being the up position on the switch and the 0 is the down position. If logic switch #8 is in the down or 0 position then the green or low indicator will light as expected. Place logic switch #8 in the up or 1 position and the red indicator lights. Look at your meter now. Notice that it is reading the same 15 VDC that you set the +V power supply to. While in the + V/CMOS mode the value for a logic 1 has changed from +5 VDC to the value of the +V power supply. Actually, any voltage from 70% of the +V supply up to 100% of that voltage will be accepted as a logic 1 by the logic indicators.

The logic switches will put out a logic 0 or 0 volts when in the down position. They will put out a logic 1 when in the up position. When in the +5/TTL mode a logic 1 is 5V. When in the +V/CMOS mode a logic 1 is the value set by the +V adjustment.

At the lower left corner of the trainer is another BNC connector identical to the one at the lower right corner of the CADET. See the description of the first BNC connector for more information.

You will find two pushbuttons on the left side of the trainer. These are called "debounced" pushbuttons because they consist of the physical mechanical switch with additional circuitry to eliminate the multiple switch closures normally found when operating mechanical

Logic Switches Summary

BNC Connector

Debounced Pushbuttons

xxxiii

Debounced Pushbuttons Hands On

Debounced Pushbuttons Summary

Function Generator

switches. That is, most switch contacts actually bounce very briefly when closed. Even though this period of time is brief, digital circuitry is fast enough to falsely interpret this as several closures rather than just one. Thus the need to electronically "debounce" these switches.

Each switch has eight tie points of two different types. Four of the points are marked by the letters "NC" meaning "normally closed". These points are connected to ground when that pushbutton is in its normal position and become open when you press the button. Four of these points are marked by the letters "NO" meaning "normally open". These points are open when the switch is in its normal position and are connected to ground when you press the button. The small switch diagram printed on the trainer helps illustrate this.

Connect a wire from the "normally closed" (NC) tie points for the top debounced pushbutton (PB1) to logic indicator #1. Connect another wire from the "normally open" (NO) tie points for the same debounced pushbutton (PB1) to logic indicator #2. Green LED #1 should be lit at this time. This is because it is connected to ground as is shown by the diagram of PB1 on the trainer. Press PB1, green LED #1 should go out and green LED #2 should light. When you press the pushbutton it disconnects the NC contacts from ground and connects the NO contacts to ground. Release the pushbutton. #1 is again lit and #2 is off.PB2 works in exactly the same manner as PB1. Notice that you never get a high or logic 1 from these pushbuttons. These debounced pushbuttons perform this same function whether in +5/TTL or +V/CMOS mode.

These two pushbuttons provide a way for a point to be normally connected to ground then momentarily disconnected from ground, or, to be normally open then momentarily connected to ground.

Also on the left side of the trainer is the function generator where you will get the clock pulses needed for some of the experiments. You will normally only need the TTL output for digital experiments. However, for the sake of completeness let's look at what this generator can do.

There is a switch with sine, triangular, and square wave symbols above its three positions. This selects one of those three waveforms. The speed or frequency of the selected waveform is adjusted by

xxxiv

three other controls. One is the frequency slide adjustment on the left which varies between 0.1 at the bottom and 1.0 at the top. Another is the decade range selection switch at the top right side of this section. It has positions labeled 1,10, and 100. The last is at the top left part of this section. It is a two position switch labeled "kHz" and "Hz". The frequency of your waveform is the number of Hertz or Kilohertz (as indicated by the switch at the top left) found by multiplying the frequency slide adjustment by the decade range selection switch. For example, if the top left switch is in the "kHz" position, the sliding frequency adjustment is at the bottom (0.1), and the decade range selector is in the middle (xlO) position, you have 0.1 x 10 or 1 kHz. The lowest frequency available is 0.1 Hz and the highest is 100 Khz.

The "amplitude" of the waveform is adjusted by the sliding control labled "AMP". It can range from 0V to +10V or -10V (20V peak-to-peak). All of these adjustments apply to all of the waveforms.

You will be using square waves for your digital work and it is possible to create them without the TTL output. However there are advantages to using the TTL output. The square waves coming from this output have much faster rise and fall times than the square waves normally created. In fact, the TTL square waves have rise and fall times that are 20 times faster than the regular square waves (25 nanoseconds vs. 0.5 microseconds). If the rise and fall times of square waves are not fast enough then the sides of the waveforms have a sloping tendency. The faster the rise and fall times the more vertical the sides of the waveforms are and thus the square waves are more "square".

The square wave from the TTL output is continuously available regardless of the position of the waveform selection switch and is in phase with the regular square waves. We will normally use the TTL output in our experiments.

Connect a wire from ground to one of the speaker terminals. Connect the other speaker terminal to the connector block for the Function Generator on the left side of the trainer. Use any one of the six right tie points which are for the three waveforms but do not use the left two tie points for the TTL output at this time. Slide the waveform selection switch to the square wave position. Slide the frequency adjustment to its lowest position (0.1). Place the kHz/Hz switch in the Hz position. Slide the decade range switch (1/10/100) to the 1 position. Move the amplitude adjustment (AMP) to its highest position.

Ready?

Function GeneratorHands On

xxxv

Turn on your trainer. Now listen quietly for at least 10 seconds. You should hear a "click" approximately every 5 seconds. Multiply 0.1 (your frequency adjustment) by 1 (your decade selection) and you will get .1 (your frequency). In other words you have a frequency of 1/10 Hz. Using the formula T=l /f (time period equals the reciprocal of the frequency) you'll find you are hearing a complete square wave every 10 seconds. One click is when the wave rises and the other when it falls. One click every 5 seconds. (If you have an oscilloscope you may want to watch the waveform as well.)

Now slowly slide the frequency adjustment up. The clicks are increasing in speed. The frequency is getting faster. When the frequency adjustment is at the top you have two clicks per second, which is one complete square wave per second or 1 Hz.

Move the waveform selection switch to the triangular wave position, then to the sine wave position. You can't hear anything but the waves are there. If you have an oscilloscope you can see them. Move the waveform selection switch back to the square wave position.

Slide the frequency adjustment to its lowest position. Now move the decade range switch (1 /10/100) to 10. You are now at 1 Hz again. Slide the frequency adjustment upwards slowly, all the way to the top. (If it is too loud slide the amplitude (AMP) adjustment down a little.) If you again multiply the frequency adjustment by the range selection you will find you are now at approximately 10 Hz or 20 alternations (clicks) per second.

Check the triangular and sine waves. Again you cannot hear them but the waves are indeed there. Go back to the square wave position.

Now move the frequency adjustment back down to its lowest position and move the decade range switch to the 100 position. You are again at 10 Hz (0.1 x 100). Slide the frequency adjustment forward, all the way to the top. This is 100 Hz.

Try the triangular and sine waves. If the amplitude (AMP) is all the way up you can hear the triangular wave more faintly than the square wave. The sine wave is audible if you put your ear near it (or are in a quiet place). Return to the square wave.

Slide the frequency adjustment back to its lowest position. Move the decade switch to 1. Move the kHz/Hz switch to the kHz position. You are now again at approximately 100 Hz (0.1 x 1,000). Move the frequency adjustment to its highest position. You are now hearing a 1 kHz tone.

Check the triangular and sine wave. They are now easy to hear. Notice that the sine wave is very "soft" or "mellow", the triangular wave is a little "sharper", and the square wave has the most "cut" to it. Go back to the square wave.

xxxvi

Using the frequency adjustment and the decade range switch continue in this same manner to check increasingly higher frequencies. You will have some frequencies too high for you to hear. You can still see them on an oscilloscope though.

There is one other experiment to try. Set the generator to a sine wave which is easily heard (e.g. 1 kHz). Now remove the wire going to the generator connector block (from one of the six right tie points) and place the wire in the TTL tie point (one of the two left points) on the same connector block. Its not that same "mellow" sine wave is it? You are hearing a square wave. The TTL tie point puts out square waves regardless of the position of the waveform switch. Try adjusting the amplitude of the wave (its probably quite loud and may be wearing on your nerves by now). You can't turn it down can you? This is another important difference. The amplitude of the TTL waveform is NOT adjustable. Try changing its frequency. That IS adjustable. Turn off your trainer.

The function generator can produce sine, triangular, and square waves from 0.1 Hz to 100 kHz. The amplitude is adjustable (except when using the TTL function). Use the TTL tie point for our digital experiments.

At the upper left corner of the trainer is the lighted power switch and fuse holder.

The following article is taken from the CADET instruction manual included with the trainer.

This section contains information which may prove useful when constructing circuits using the CADET. While there are no hard and fast rules for breadboarding, the following tips may save time and trouble.

Unless a circuit is being prepared for a demonstration or display, avoid cutting component leads very short. While short wires and leads may look neat, the clipped components will only fit into a limited "span" of connector sockets, limiting the use of the component. It is perfectly permissible to use untrimmed components while exploring different circuit possibilities. The only time short leads may be necessary is when operating at higher frequencies and experiencing mysterious malfunctions. Sometimes the only way to correct high

Function Generator Summary

Power Switch

Breadboarding Techniques

xxxvii

frequency circuit problems is to shorten all circuit connections.Be cautious when using components which have been

removed from a tape reel used in automatic insertion equipment. Suppliers of surplus components often sell components which are taped together in small batches. Removing the components from the tape does not always remove the adhesive from the leads of the components. Placing a formerly taped component into a socket connector may result in a poor electrical connection and, worse still, leave tape adhesive in the socket. Avoid this problem by either carefully cleaning taped component leads, clipping the taped portion of the lead off, or avoiding the use of taped components altogether.

Be especially careful when inserting integrated circuits into the breadboard socket. Unless the IC pins are straight, it is very easy to crush the pin into a zig-zag shape or fold the pins underneath the body of the IC. Either way the result is a bad connection or no connection at all.

Always use solid wire for breadboard connections. When stripping the wire ends, be careful not to strip more than about three-eighths of an inch of insulation from the wire. Too much bare wire may result in unintentional connections near the wire end.

After you have built up a few circuits, you will have a good collection of prestripped jumper wires. Save them. By re-using these wires, you can save even more time and effort in assembling future circuits.

xxxviii

Some general rules of circuit construction are provided here to help the student efficiently complete laboratory assignments. The rules are:

Construct circuits neatly. Neat construction makes troubleshooting possible should the circuit not perform as expected.

Insert only one wire, 20 gauge or 22 gauge, into each pinhole to avoid damaging the breadboard.

Devote special attention to the routing and connection of the power and ground connections to the ICs used for circuit construction. Reversing these connections is normally sufficient to destroy the misconnected IC. Shorting power and ground may damage the breadboard power supply by overheating it.

If a circuit fails to function, make sure that power is properly applied to the circuit. This prevents embarrassment.

Pay special attention to safety. Don't wear rings, watches and other jewelry while constructing or working on electronic circuits. These metallic items can short across power leads resulting in high currents, hot conductors and the potential for burns and fires. Don't work on electronic circuits when tired or impaired by medications. Do not engage in horseplay in the laboratory.

The final advise to students wanting to improve laboratory success is keep an accurate laboratory notebook. Such notebooks are often required by companies involved in circuit design, evaluation, and quality assurance particularly when involved in research that may end up as part of a patented product. We recommend that in addition to filling in the blanks of your text/lab book, that you develop the habits involved in keeping a laboratory notebook.

This notebook should be a bound book which requires a tool to remove the pages. Ideally, the pages should be

xxxix

consecutively numbered. Describe all experiments performed and record all data in this book. Have the data witnessed by a person (fellow student) competent of understanding the data's validity. If graphs or figures are inserted into the notebook, write your name and the date across the edge of the inserted material onto the notebook page. These precautions prevent tampering with the notebook data. A notebook like the one described can be used as a legal document. More importantly, the notebook will be an invaluable aid to the experimenter as digital circuitry is mastered.

xl

INTRODUCTORY CON

1

CHAPTER

CEPTS

xlii

In this opening chapter, you will review some basic concepts required to understand the characteristics of digital circuits. These concepts are important since they will form the basis of all further study of digital circuits.

Digital circuit and system characteristics will be compared to analog systems and circuit characteristics. This comparison will emphasize the difference between the continuous nature of analog circuits and systems and the discontinuous nature of digital presentation of information.

Some knowledge of how transistors work is helpful in understanding the material presented in this chapter.

1.0 INTRODUCTION

1

After completing this chapter you should be able to:

• Distinguish between digital and analog signals.

• Discuss how 1s and 0s are used either to represent quantityor to represent condition .

• Represent binary quantities.

• Explain the operation of a basic digital circuit.

1.1 OBJECTIVES

xliv

1.2 DISCUSSION

1.2.0 Digital and Analog Circuits

The recent boom in integrated circuit (IC) electronics has largely come about because integrated circuits are inexpensive, compact, consume very little power, and are highly reliable. Integrated circuit technology is applied to both analog and digital circuits. The most popular analog circuits are amplifiers, especially operational amplifiers.

The great utility of digital integrated circuits has added to the popularity of ICs. Digital integrated circuits are the building blocks in computers, calculators, most modern timers, clocks and small electronic displays. They are also used in automobiles, robots, navigational systems, and a variety of consumer electronic products.

We live in two very different electronic worlds. The analog world or the real world where all changes are continuous and the digital world or man-made world that is discontinuous.

In the analog world you have smoothly changing electrical voltages or currents that represent changes in physical things such as temperature, water level, or pressure. (See Figure 1-1)

Other, more familiar, continuous signals that are considered analog are television signals, radio waves, and police radar signals. The trait common to all

3

analog signals is that they are continuously variable.Circuits used to reproduce these continuously changing signals are termed

analog circuits. They feature active devices, such as transistors, operating in their linear region. Transistors operating as amplifiers in their linear region amplify small input signals with a minimum of distortion. As long as an input signal is applied an amplified reproduction of that signal is present as an output. This amplified output signal may be used to drive chart recorders or x-y-plotters.

In using analog circuits, it is important to keep input signals small enough to keep the amplifier out of the cut-off and saturation regions of operation. Analog output signals become distorted or clipped when the amplifier is forced to its cut-off and/or saturation limit(s).

Digital signals are not continuous. They are quantized, that is at any given time they are at one of two allowed voltage levels only. A collection of these states or digital words may be used to represent quantity. Digital words that might represent temperature at particular times are illustrated in Figure 1-2. These signals are not smoothly continuous.

4

A common example of a digital signal is a light which can be either on or off. Another example is the traffic light which may be green, yellow or red. Digital signals could have any number of steps and one way of classifying digital signals is by the number of discrete steps possible with a particular sort of signal. Using this convention, the simple light represents binary digital signals (having only two allowed conditions) and the traffic light tertiary digital signals (having three allowed conditions). Practical digital circuits are binary. Since binary circuits require only two states for operation they are simple to construct.

In the 1800s a researcher, George Boole, studied the mathematics of how humans think. He discovered that humans use either/or logic. That is, we think of things as being either one thing or another. For example: statements can be true or false; it is either light or dark; etc. Thus a system of binary (two state logic) is quite natural to us. George Boole's work led us to use binary digital devices.

Unlike the analog circuit, the binary digital circuit operates in only the cut-off or saturation condition of the active element, usually a transistor. The digital circuit is in its linear operating region only during transition from one of its extreme states to the other, ie. while changing from the cut-off state to the saturation state for example. When the active element is operated in this way, the circuit is said to be operating in a switching mode. The output can only be very close to Vcc or ground.

While this mode of operation would be abnormal and unde-sireable for an analog circuit, it is the normal operating mode for digital circuits.

To summarize, a basic binary digital circuit is one capable of outputting one of two allowed voltages at any given time. One allowed output voltage is near Vcc, the other near ground (0 Volts).

For now let us choose the voltages +5 volts and 0 volts. These choices are arbitrary and not universally adopted. In any case let the +5 volt output represent a logic 1, true, or HI level and the 0 volt output a logic 0, false, or LO level.

The signals generated by the digital circuits discussed in a preceding section have no inherent meaning. The signals are symbols used to represent abstract concepts. One use of such signals is to indicate the state of a device. For example, the door on a microwave oven must be closed before the oven is operated. A switch on the door can be used to provide a digital signal which is symbolic of the state of the door (open or closed). The decision to enable the oven's cooking circuits is based on the door being in the closed state. The choice of whether a logic 0 represents the open or closed state of the door is arbitrary.

In this case the binary output of a digital circuit is being used to sense and report the condition of the door (open or shut). Sensing and reporting conditions is one of main uses of binary digital circuits.

Binary digital signals are also used to represent quantity or amount. A single binary digit (bit) can have the numerical value of one or zero. Again, the choice of whether +5 volts represents a one or a zero is arbitrary though convention frequently results in the selection of +5 volts as the signal level representing a value of one. A single bit can be combined with other bits to represent any desired binary number or quantity.

Pay special attention to the fact the output of a digital circuit can represent a condition (HI or LO, logic 1 or 0, true or false) or a number (1 or 0). This is an extremely important concept to grasp as it allows the representation of state, and quantity by the same type of circuits. The interpretation of the data is by convention of the user.

As stated in the previous paragraph, bits can be combined to represent numbers of any size. The method of representing these numbers is similar to that used for decimal

1.2.1 Use of Binary Digital Ones and Zeros

(base 10) numbers. In the decimal system each digit left of the decimal point represents an integer power of ten. For binary quantities (base 2) each digit left of the "binary point" represents an integer power of two. Each of these systems starts numbering the power of the base with zero (base^). Thus the number 10 in the decimal system represents one TEN and zero ONES. The number 10 in the binary system represent one TWO and zero ONES. Likewise, the number 0.1 in the decimal system is one TENTH. The number 0.1 in the binary system is one HALF. For further clarification of these points see Figure 1-

1.2.2 Digital Circuits Circuits used for analog and digital applications differ greatly. Since analog circuits must represent a large number of values between extremes, they are designed to have a region of operation with linear gain (Vout= A Vin). Digital circuits are designed to switch between the two digital states as quickly as possible. The simplest digital circuits are switches. (See Figure 1-4)

This circuit produces a +5 volt output when the switch is open and a zero volt output when the switch is closed. Switches such as this have limited application since the switch contacts tend to bounce resulting in slow switching from one state to the other. Digital circuits have been constructed using discrete diodes and transistors. An example of a basic digital circuit implemented with a bipolar junction transistor (BJT) is shown in Figure 1-5.

This digital circuit operates only in the saturated mode or the cut-off mode of transistor operation. This means that the emitter-base and collector-base junctions are both forward biased or the junctions are both reverse biased. This mode of operation is chosen so that when the transistor conducts, the resistance from the collector to the base will be minimal. So, when the transistor conducts in response to a +5 volt input (logic 1) to the digital circuit the output of the switch will be very near to ground (logic 0). Actually this voltage, Vce (sat), is about 0.2 to 0.6 volts for silicon bipolar junction transistors. When the transistor is cut-off in response to a 0 volt level at the circuit input, the output will be +5 volts.

Such a circuit is termed a digital inverter since the output logic level is the inverse of the input. It is the simplest digital circuit. When used as a logic circuit it is called a "NOT" gate.

This technique of circuit construction while workable, was rightly perceived as being cumbersome and wasteful of space and designer's time. Out of the need for compact easily usable circuits, the monolithic integrated circuit was developed by Texas Instruments in 1959. The digital integrated circuit combines several circuits similar to those just described onto a single piece or "chip" of silicon. Such ICs are available to perform a wide variety of logic functions. These digital circuits will be studied throughout the remainder of this book.

1.3 SUMMARY The difference between analog and digital signals was brought out in this chapter. Analog signals are continuous and digital signals are discontinuous. Digital signals can be used to symbolize either quantity or state. Binary quantities are represented by strings of bits similar to the digits used to represent decimal numbers. The circuits used to represent digital signals are the same whether the signal will symbolize a quantity or state. Digital circuits are easily constructed from discrete components such as transistors and diodes, but are most often encountered in the form of ICs.

1.4 REVIEW QUESTIONS

1. Explain the difference between digital and analog signals.

2. What states can a bit be in?

3. What numbers can a bit represent?

4. Draw the schematic of a simple digital switch. Why dothese switches seldom appear as shown?

5. Who constructed the first integrated circuit?

6. Name some qualities of an analog circuit.

7. Name some qualities of a digital circuit.

8. Draw the schematic for a simple BJT digital inverter.Explain it's operation.

9. Explain what an integrated circuit is.

CHAPTERNUMBER SYSTEMS AND

CODES

This chapter is about number systems and codes. Digital machines most frequently operate on binary, binary coded or binary related numbers. People most frequently work with decimal numbers or alphabetic characters. This alphanumeric data can be represented as binary or binary coded quantities. You will learn how to translate from one number system or code to another. This translation can be performed electronically by encoders and decoders. Of course the translation can also be done manually and several methods of accomplishing this will be outlined and demonstrated.

The material in this chapter may seem pretty abstract at first. Keep after it. It is important to learn how binary used by machines can be coded to represent a wide variety of characters. One important idea that you will see is that all true number systems presented in this chapter are constructed the same way, only the base or radix, and the character set changes.

2.0 INTRODUCTION

2.1 OBJECTIVESUpon completion of this chapter you should be able to:

• Use and explain the binary number system.

• Convert from binary numbers to decimal numbers.

• Convert from decimal numbers to binary numbers.

• Use and explain the hexadecimal number system.

• Use and explain the octal number system.

• Use and explain the BCD code.

• Use and explain the ASCII code.

2.2 DISCUSSION Though you may not realize it, you are already familiar with positional number systems. The decimal system with which you have worked since grade school is a positional number system of radix or base 10. A positional number system can be constructed using any radix. Digits left of the radix point represent increasing positive powers of the radix and digits right of the radix point represent increasing negative powers of the radix. The general form of a positional number system with n digits left and right of the radix point is shown in Figure 2-1.

Notice that the constants (As) preceding the integral powers of the radix have values (weights) falling between 0 and R-l inclusive. These values or weights form the character set

for the number system. Also note that when R, the radix, is set equal to ten that the familiar decimal number system results and the radix point is called a decimal point. A positional number system like the one described here can represent Rn different integers and has a maximum integer count of R(n-1)

While any radix could be used in construction of a positional number system, digital or computer systems commonly operate on number systems of radix 2, 8, or 16. The number systems based on these three radices plus our own base 10, decimal system will be the only ones studied here. Principles learned about these number systems would apply equally well to other true positional number systems.

In addition to these true number systems, we will review special coding formats that allow us to represent decimal numbers using groups of binary bits. These are not number systems, they are codes.

Numbers will not be the only quantities represented in digital machines. Any practical system will require some method of representing alphabetic data in addition to numeric data. Several codes for representing alphanumeric data in a binary form have evolved. Examples are: the Baudot code, a five bit code named for Emile Baudot, the American Standard Code for Information Interchange (abbreviated ASCII and pronounced "as-key"), a seven bit code, and the Extended Binary-Coded-Decimal Interchange Code (abbreviated EBCDIC and pronounced "eb-see-dik"), an eight bit code. Baudot code was used in older data communication equipment such as teletypewriters. EBCDIC, developed by IBM, will normally be used in systems connected to mainframe computers. The ASCII code is the most common code used in the United States and is the only alphanumeric code covered in this text.

The binary number system is a positional number system with a radix of two. The binary system is the simplest useful positional number system. Each binary digit or bit can have a value of either 0 or 1. No other possibilities exist, this is the complete character set.

These two values can be represented by any device capable of distinct off and on states. The binary number system can be related to the general positional number system outlined above. Table 2-1 shows the structure of the binary number system. Notice that n bits can have 2n states and a maximum count of 2(n-1).

2.2.0 The Binary Number System

2.2.1 Binary to Decimal Conversion

The binary number system is not our natural counting system, so it will seem strange at first. The first step in becoming more familiar with this number system will be to learn how to translate binary quantities to the more familiar base ten system.

The following procedure is suitable for translating numbers from a number system of any radix to the equivalent number in radix 10. The procedure will be illustrated only with radix 2. The procedure to convert a number from any radix to decimal is shown in Table 2-2.

2.2.2 Decimal to Binary Conversion

The procedure outline here will convert any decimal integer into it's numeric equivalent in any other radix. The procedure is:

1. Divide the given decimal integer by the radix of thenumber system to which you wish to convert.

1. Record the remainder.

2. Divide the quotient from the preceding step by the radixnumber and record any remainder.

2. Continue the process until the quotient becomes 0.

5. The remainders will form the digits of the number in the converted base. The first remainder recorded is the LSD and the last remainder recorded is the MSD. If the process of converting has been performed from left to right the number will read out in reverse order.

Use of binary numbers, while convenient for machines, is cumbersome to people. Any sizeable quantity expressed as a binary number has a large number of digits all of which are either 1 or 0. People are far more comfortable with shorter strings of digits with more values since that is what most of us learned in school. Also conversion from binary to decimal is cumbersome. For this reason, the hexadecimal number system (radix 16) has become widely used. The hexadecimal number system uses the same characters as the decimal system for the numbers 0-9. Table 2-3 shows the values from decimal 10 through decimal 15.

2.2.3 The Hexadecimal Number System

The letters were included as part of the character set because they were characters available on standard keyboards.

Hexadecimal digits are formed by grouping binary bits into groups of four from the binary point. This makes conversion between binary and hexadecimal number systems straight forward. See Figure 2-3 for examples of these conversions.

2.2.4 The Octal Number System

The Octal (radix 8) number system is another binary related number system. The octal number system uses the same digits for the numbers 0-7 as the decimal number system. There are no other digits in the octal character set. Octal digits are formed by evaluating binary bits in groups of three bits. The octal system is easier for humans to use than binary since the octal system uses digit characters familiar to most people. Conversion between octal and binary numbers is straight forward. See Figure 2-4 for examples of octal/binary conversions.

2.2.5 Binary Coded Decimal System

The Binary Coded Decimal (BCD) system is the first coded system studied here. A BCD number is formed by leaving a decimal number in it's normal positional notation and expressing each decimal digit using a group of four binary bits. This gives humans a means of working with a system that easily converts between decimal and binary. This also means that 6 states of the four bits are not used for coding the decimal number. Some BCD codes will use these states for error detection. Natural BCD numbers will simply code each digit of the decimal number with the four bits. Figure 2-5 illustrates this concept.

The excess-3 code is a second form of BCD code. This code avoids the all zeros and all ones states by taking the 10 values for the decimal system from the decimal equivalents of 3 to 12. A table showing binary values of the excess-3 code is shown in Table 2-4.

The ASCII code is the most widely used code for transfer of information in the USA. ASCII is a seven bit code which can have up to 128 values. These values are divided into three word sets. Sixty-four words are for the upper case alphabet, numbers, often used punctuation and a blank. Thirty-two words are used as machine commands. Examples of machine commands are the carriage return, line feed, and bell. The remaining thirty-two words are used for the lower case alphabet and infrequently used punctuation marks. A table of the ASCII code is shown in Table 2-5.

Some interesting consistency occurs in the ASCII code. Any upper case letter of the alphabet can be changed to lower case by changing bit 6 from 0 to 1. Also the characters which print as 0 through 9 are coded so that the lower four bits of their ASCII code is the number to be printed expressed in BCD (30 HEX to 39 HEX).

2.2.6 ASCII Code

This chapter reviewed the characteristics of number systems and codes. The number systems included were: binary, decimal, octal and hexadecimal. The codes studied were: BCD and ASCII. You were also given instructions for converting from one radix to another. When appropriate, the uses of the codes were included.

Chapters 1 and 2 have been the foundational chapters that support your future work in digital circuits. The idea that digital circuits respond to input conditions will be further developed in Chapters 3 and 4. The material covered in this chapter will gain increased importance as the study of counters, digital arithmetic circuits, are developed in Chapters 6 and 7. Take a few minutes to look over these chapters.

2.3 SUMMARY

1. What is the radix of the binary number system?

2. What is the common name for the radix ten numbersystem?

3. Which number system includes a character B ?

4. How many bits are required to represent an Octal digit?

5. What is the common name for the radix 16 numbersystem.


6. Convert decimal 122 to binary. (Show all the steps)

7. Convert hexadecimal EF to binary.

8. Convert hexadecimal EF to decimal.

9. Air Force Work unit codes are a radix 34 system. Howmany parts can be in a system which has a three digitwork unit code?

10. Convert decimal 125 to octal.

11. Convert octal 33 to hexadecimal.

12. Convert A0 hexadecimal to decimal.

13. What binary code will be required to force an ASCIIdevice to ring the bell?

14. What is the hexadecimal value of ASCII A?

15. Convert 9 decimal to ASCII.

CHAPTERLOGIC GATES AND

BOOLEAN ALGEBRA

This chapter explores Boolean Algebra and the logic gates used to implement Boolean equations. Boolean Algebra is an area of mathematics involving operations on two-state (true-false) variables. This type of algebra was first formulated by the English Mathematician George Boole in 1854.

Boolean Algebra is based on the assumption that any proposition can be proven with correct answers to a specific number of true-false questions. Further, Boolean algebra provides a means whereby true-false logic can be handled in the form of Algebraic equations with the questions as independent variables and the conclusion expressed as a dependent variable (recall that in the equation y = A+B that A and B are independent variables and y is a dependent variable). This chapter will introduce you to the use of Boolean algebra and the use of electronic logic gates (circuits) to implement Boolean equations.

3.0 INTRODUCTION


• Explain the basic operations of Boolean Algebra.

• Write Boolean equations.

• Use logic circuits to implement Boolean equations.

3.2 DISCUSSION

3.2.0 Boolean Variables

Boolean algebra is the branch of mathematics which studies operations on two-state variables. For the purposes of this book, an algebra is a system of mathematics where the operations of addition and multiplication can be performed with the results of the operation remaining within the system.

In Boolean algebra, addition and multiplication are the only binary (two-variable) operations which are defined. These two operations also may be performed on more than two independent variables. The only other operation in Boolean algebra is the unary (one-variable) complement function. These three operations are the only operations allowed in Boolean algebra. Mastery of these operations will be critical for understanding modern digital electronic circuitry.

Boolean variables are also known as logic state variables. Variables of this type can be in one of two possible states. The states are known as true and false. These true-false variables can be implemented with electronic devices as was illustrated in Chapter one.

Such logic devices are often described as having a 1 or 0, HI or LO, On or Off, True or False input or output. These expressions are convenient ways of noting the state of a particular Boolean variable. Keep in mind that the numbers, 1 and 0, refer to logic states and not binary integers.

Throughout the rest of this text, the terms HI, 1, and On will be used to indicate that a logical variable is True. Likewise the terms LO, 0, and Off, will indicate that the state of a logical variable is False. All exceptions to this convention will be noted.

Again, note that Boolean variables are two-state variables. Having two states allows these variables to be easily represented by electronic two-state switching circuits. Boolean variables are the basis of all modern digital electronic systems.

Truth tables are useful in describing relationships of Boolean variables. A truth table lists all dependent and independent variables and all possible combinations of their states. The states are listed in mnemonic form.

The independent variables are listed at the top of the truth table to the left. At the top right of the truth table is the dependent variable. Columns of the truth table show all possible states of the associated Boolean variable. Figure 3-1 shows several examples of implementing the truth table for the logical OR function.

3.2.1 Truth Tables

In Figure 3-1, notice that the state of the independent variables reads right to left for the corresponding state of the dependent variable. Also note that all truth tables will have only one dependent variable.

The truth table will have the number of lines necessary to represent all possible combinations of the independent logic variables.

For Boolean algebra, the number of lines in a truth table will be equal to 2n where n is the number of independent variables. For example, a truth table for two independent variables require four lines, 2^, to completely define all the possible combinations of the two variables.

With your knowledge of binary states you should be able to construct the independent part of any truth table at this point.

The following sections of this text will provide the information necessary to complete the dependent portion of the truth table.

3.2.2 The OR Operation

The first Boolean operation to be discussed is the logical OR operation. The OR operator operates on two or more Boolean variables. The result or dependent variable of the OR operation will be true if either one or both of the independent variables is true . The result will be false only if both of the independent variables are false. The truth table for the OR operation is shown in Figure 3-2.

3.2.3 The AND Operation

The OR operation is called the Boolean addition operation. The notation for the OR operation performed on the Boolean variables A and B is f = A+B where f is the dependent variable or result. This logic operation is not the same as adding the binary integers A and B.

The logical AND operation operates on two or more Boolean variables. The AND operation will only have a true result if both independent variables are true. In all other cases the result will be false. Figure 3-3 is the truth table for the logical AND operation.

3.2.4 The NOT Operation

The logical AND operation is called the Boolean multiplication operation. The AND operation performed on the independent variables A and B is written as f = A«B. This is not the same as multiplying binary integers.

The NOT operation is the simplest Boolean operation. It is the only unary operation allowed in Boolean algebra. This means that the operation is performed on only one Boolean independent variable or on one Boolean logic expression. The NOT function returns the complement of the state of the

Boolean variable. A truth table for the NOT operation is shown in Figure 3-4.

The NOT operation will result in the opposite logic state of the Boolean variable on which it operates. This means that TRUE Boolean variables will return a value of FALSE when operated on by the NOT operator. The NOT operator is written into Boolean equations by placing a line over the complemented variable. A is read as "NOT A."

The AND, OR, and NOT operators are all of the basic operations in Boolean algebra. All other operations are made from these three basic operations.

Boolean equations involve combinations of these three basic functions according to the rules of Boolean algebra. Boolean algebra has its own set of rules and laws. Boolean equations are written in the same form as other mathematical equations and may involve variables and constants (1 or 0).

Many of the rules of algebra that you already are familiar with will not change in Boolean algebra. Operations in Boolean equations are performed from left to right with logic multiplication first then logic addition after products are completed. Logic equations are frequently written in the form f= A op B op C... where op signifies a logical operation (AND or OR).

Some books will use the symbol Y instead of f for the result. This is not really new to most of you as you have seen the expressions Y and f(x) used interchangeably in other algebra courses. Some common laws of Boolean algebra are listed in Table 3-1.

The Laws of Absorption can be derived from the distributive laws and the laws of tautology. As mentioned previously, the Boolean operations can be combined to solve complex problems. Logic equations are a way of describing and analyzing logical functions.

3.2.5 Logic Equations

3.2.6 Logic Circuits

When George Boole formulated Boolean algebra, electronic switching had not been invented. For lack of a suitable method of implementing logic equations, Boolean algebra was unused in technology for nearly 100 years. The invention of reliable electronic switches stimulated the use of Boolean algebra for solving logic equations.

Early switches implemented with electron tube technology could solve Boolean equations more quickly than humans but large arrays of such switches were bulky and consumed enormous amounts of electrical power. The invention of semiconductor switches was eventually responsible for the widespread use of logic circuits evident today.

Semiconductor switches have been widely used because they provide a compact, efficient, economical, and reliable method of solving logic equations. A large number of logic equations have been implemented as digital integrated circuits. These devices use several transistor switches to solve logic equations. The electrical output of these circuits represents the state of the dependent variable in the logic equation. The electrical inputs to these circuits are the states of the independent variables.

Digital logic circuits are often referred to as logic gates. The schematic symbols for the gates used to implement the basic Boolean logic equations are shown in Figure 3-5.

A logic equation can be solved by arranging logic circuits to perform the logical operations indicated by the logic equation. The electrical inputs to the circuit can be varied between the allowed states while the circuit output can be observed. This technique is used to create a truth table for the entire logic equation.

An example of converting logic equations to logic circuits is shown in Figure 3-6.

LOGIC EQUATION: Y = A • B+C

LOGIC CIRCUIT: The variables A and B must be ANDed then the result ORed with the variable C.

The electrical output of logic circuits will be one of two voltages. When the more positive of these voltages is used to

3.2.7 NOR and NAND Gates

represent a logic 1, HI or TRUE state, the device is termed to use positive logic. Devices using the opposite convention are said to use negative logic. Negative logic circuits are sometimes called "LO true." You will become familiar with constructing circuits from logic equations. This process is crucial to understanding digital systems.

NOR and NAND gates are two of the simpler combinational logic circuits that are commonly available. These combinational logic circuits are used to combine logic functions for de cision making. The logic equation for a NAND gate is f = A • B. The logic equation for a NOR gate is f = A+B. The schematic symbols for the NAND and NOR gates are shown in Figure 3-7.

The NAND and NOR gates are the same as the AND and OR gates previously studied except that an inverter is built into the output of each circuit. Any digital circuit no matter how complex can be constructed entirely from only NAND or NOR gates. This can be readily demonstrated by implementing all the logic functions using only these gates. This fact is largely responsible for the popularity of these gates.

3.3 SUMMARY In this chapter the concepts for the use and understanding of Boolean algebra were introduced. The three basic operations used in Boolean algebra were defined and explained. The use of logic equations and some basic rules of Boolean algebra were presented.

Implementing logical equations with electronic digital circuits was explained and the schematic symbols for some common logic circuits were identified. The NOR and NAND combinational logic circuits were introduced and the flexibility of these circuits explained. The concepts learned in this chapter will be used throughout the remainder of this book and your association with digital electronics.

1. Who first formulated Boolean algebra ?

2. What is the practical use of Boolean algebra ?

3. What are the three basic operations allowed in Booleanalgebra ?

1__________________________________________________

2__________________________________________________

3_________________________________________________4. How many variables does the AND function operate on?

5. How many variables does the NOT function operate on?

6. What is a truth table ?

7. Draw the truth table for the NAND function.

8. Draw the schematic symbols for the three basic logic operations.


9. Draw the schematic of a circuit that will perform theoperations in the following logical equation: f = C+DF.

10. Draw and complete a truth table for the equation fromquestion nine.

11. Name two of the simpler combinational logic circuits.

12. What are combinational logic circuits used for ?

13. Why have digital integrated circuits become so popular ?

LAB EXERCISE 3.1The NOT Circuit

(Inverter)

Objectives

Materials

Procedure

After completion of this experiment you will understand the operation of logic inverters (NOT gates). You will be able to use the 74LS04IC and explain its operation.

C.A.D.E.T.

74LS04 Hex Inverter

Jumper Wires

TTL Data Book

This section will begin your experiments with logic gates. You will learn some general characteristics of logic circuits then study the 74LS04 TTL hex inverter.

All logic circuits will have connections for power and ground. Logic circuits are usually seen as Dual Inline Package

Integrated Circuits known as DIP ICs. The term dual inline package describes the pin arrangement for the integrated circuit inputs and outputs.

All DIP ICs have one end or corner marked in a special way. This marking is used to show integrated circuit pin orientation. With the marked end of the IC facing away from you the pins are numbered counterclockwise from the upper left corner. Figure 3-8 shows how ICs are marked and how the pins are numbered.

The ICs used in this experiment are TTL ICs. This means the voltage of the two logic states are 0 and 5 volts. A large number of compatible integrated circuits have been manufactured as the 7400 series of TTL ICs. Correct connection of power and ground pins is crucial to circuit operation. Many 14 pin DIP ICs use pin 7 for ground and pin 14 for Vcc. Some 14 pin DIPs use pin 11 for ground and pin 4 for Vcc. Most 16 pin DIP ICs use pin 8 for ground and pin 16 for Vcc. If you connect the power and ground connections incorrectly the IC will be destroyed. For this reason, a basing diagram of all ICs used in experiments is provided. The basing diagram explains all connections to an IC and uses schematic symbols to indicate logic functions performed by the circuit. A basing diagram for the 74LS04 hex inverter is shown in Figure 3-9.

If you have trouble during the experiment, remove power from the IC and check circuit wiring. Consult with your instructor if after repeated attempts to correct the problem fail.

1. Place 1 74LS04IC on the CADET breadboard. Make suretrainer is turned off.

2. Use the basing diagram of the 74LS04 to locate the power andground pins.

3. Connect pin 7 to ground and pin 14 to +5V DC at the top of theCADET. You will do this for all TTL circuits.

4. Connect pin 1 to PB1 to obtain a LOW POWER circuit as shownin figure 3.10B. (This figure is from page 22 of the CADETDigital Supplement Manual (80-01-0418). The top figure on thepage should be designated 3.10A and the bottom one 3.10B.The total page would be Figure 3.10. These figures must beadded to this manual and will add a full page followingprocedure 4.)

5. To monitor logic levels use the Logic Indicators (LEDs) on theright side of the CADET. Use Indicator 1. Set the +5 /+V switchto +5 and the TTL/CMOS switch to TTL so the LEDs willindicate true logic LOW or HIGH levels. You will use thesesettings for all TTL circuits you monitor.

6. Connect pin 2 to logic indicator #2 beside your pin 1 connection. This allows monitoring the invertor output.

7. Check circuit wiring. When you are certain that the circuit iscorrectly wired, turn on the CADET power switch. Note theLEDs and record the states of Logic Indicator 1 and 2.

8. Push PB1 and record the states of Indicators 1 and 2. Note: Ahigh indicates a logic 1; low indicates logic 0.

9. Turn off power. Leave the 74LS04 IC connected until after youhave finished the following questions:

1. Construct a truth table for the 74LS04 hex invertor.2. Why is the 7404 called a hex invertor? (hint: lock at the basing

diagram).

3. Are Logic Indicators 1 and 2 ever on high simultaneously?

In this laboratory you will learn the use of the 74LS08 quad two-input AND gate. You will observe and record the AND gate's logic characteristics.

Procedure

Questions

LAB EXERCISE 3.2 The AND Gate

Objectives

M C.A.D

.E.T.

74LS

08

Quad

Two-

input

AND

Gate

Jump

er

Wires

TTL

Data

Book

Procedure

1. Insert the 74LS08IC into the breadboard. Make sure the traineris off.

2. Wire pin 7 to ground and pin 14 to the +5V line at the top of theCADET.

3. Wire Logic Switch 1 on the lower left of the CADET to pin 1 ofthe 74LS08 and Logic Indicator 1. This allows setting the stateof pin 1 with Logic Switch 1 and observing it's state on Indicator1.

4. Wire Logic Switch 2 to pin 2 on the 74LS08 and to Indicator 2.This allows setting and observing the state of pin 2.

5. Wire pin 3 on the 74LS08 to Logic Indicator 3. This allows observation of the AND Gate output.

6. Place Logic Switches 1 and 2 in their off state (towards thebottom of the CADET). Set the +5/+V switch above the logicswitches to +5. Set the +5/ +V switch above the logic indicatorsto +5. Turn on the CADET power switch.

7. Move Logic Switch 1 to on (up). Indicator 1 should show high.If it doesn't, check wiring to pins 1 and 2.

8. Turn switch 1 off and switch 2 on. Indicator 2 should showhigh.

9. Now use SI and S2 to determine the truth table for the 74LS08.Record your results. Observe the circuit output on indicator 3.Power down.

In this laboratory you will learn about the 74LS32 two-input OR gate.

C.A.D.E.T.

74LS32 Quad Two-input OR Gate

Jumper Wires

TTL Data Book

LAB EXERCISE 3.3 The OR GateObjectives

Materials

1. Insert the 74LS32IC into the breadboard. Make sure yourCADET is turned off and the TTL/CMOS switch is in TTLposition and the +5+V switch is in the +5 position.

2. Wire pin 7 to ground and pin 14 to +5V.3. Wire Logic Switch 1 to pin 1 on the 74LS32 and logic indicator

1. This allows setting the state of pin 1 with switch 1 andobserving its state on indicator 1.

4. Wire Logic Switch 2 to pin 2 on the 74LS32 and to indicator 2;this allows observation of the state of pin 2

5. Wire pin 3 on the 74LS32 to Indicator 3. This allows observationof the OR gate output.

6. Place Switches 1 and 2 in their off state (down)7. Make sure your +5V switch is at +5 and the TTL / CMOS switch

is set to TTL. Turn on power.8. Place Logic Switch 1 to ON. Indicators 1 and 3 should go high.9. Place Switch 1 OFF and 2 ON. Indicators 2 and 3 should show

high.10. Place Switch 2 OFF. Use the switches and indicators to deter

mine the truth table for the 74LS32. Record your observationsand then power down and remove your circuits.

Procedure

LAB EXERCISE 3.4 The NAND Gate

Objectives

Materials

In this laboratory you will learn the operation of the 74LS00 two-input NAND gate.

C.A.D.E.T.

74LSO0 Quad Two-input NAND Gate

Jumper Wires

TTL Data Book

Procedure

1. Make sure the CADET is turned off. Insert the 74LS00IC intothe breadboard.

2. Wire pin 7 to ground and pin 14 to +5V DC.3. Wire Logic Switch 1 to pin 1 on the 74LS00 and Logic Indicator

1. This allows setting the state of pin 1 and observing its stateon the indicator.

4. Wire S2 to pin 2 of the 74LS00 and to indicator 2.5. Wire pin 3 of the 74LS00 to indicator 3. This allows observation

of the NAND gate output.6. Place SI and S2 in the LOW state...down.7. Turn on CADET. Logic Indicator 3 should be HIGH and

Indicators 1 and 2 should be LOW.8. Move SI to HIGH. Indicator 1 should show HIGH.9. Move SI to LOW and S2 to HIGH. Indicator 1 should show

LOW and Indicator 2 HIGH.10. Move SI to LOW. Use SI, S2, and Indicator 3 to determine the

truth table of the 74LS00 IC. Record your observations here.When finished power down the CADET and disassemble thecircuit.

In this experiment you will learn the use of the 74LS02 two-input NOR gate.

C.A.D.E.T.

74LS02 Quad Two-input NOR Gate

Jumper Wires

TTL Data Book

1. Insert the 74LS02IC into the breadboard with CADET turnedoff.

1. Wire pin 7 to ground and pin 14 to +5V DC.2. Wire Indicator 1 to pin 1 of the 74LS02 to observe the state of pin

1 (NOR gate output) with Indicator 1.3. Wire S2 to pin 2 of the 74LS02 and to Indicator 2 to set and

observe the state of pin 2.4. Wire pin 3 of the 74LS02 to Indicator 3 and S3 to set and observe

the state of pin 3.2. Switch S3 and S2 in their LOW state...down.5. Turn on your CADET. Indicator 1 should be HIGH and

Indicators 2 and 3 should show LOW.6. Switch S2 to HIGH. Logic Indicator 2 should show HIGH and

Indicator 1 should go LOW.7. Switch S2 to LOW and S3 to HIGH. Indicators 1 and 2 should

show LOW, and Indicator 3 HIGH.8. Switch S3 to LOW. Use S2, S3, and Indicator 1 to determine the

truth table of the 74LS02 IC. Record your findings and thenpower down your CADET and disassemble your circuit.

LAB EXERCISE 3.5 The NOR GateObjectives Materials

Procedure

In this experiment you will confirm that NOR and NAND gates can be used to perform any logic function.

LAB EXERCISE 3.6 Using NAND and NOR GatesObjectives

Materials

Procedure

C.A.D.E.T.

74LS02 Quad Two-input NOR IC

74LS00 Quad Two-input NAND IC

Jumper Wires

TTL Data Book

1. Turn off CADET and install the 74LS02 IC on the breadboard.Then wire pin 7 to ground and pin 14 to +5V.

2. Wire S2 to pin 2 and S3 to pin 3.3. Wire pin 2 to Indicator 2 and pin 3 to Indicator 3.4. Wire pin 1 to pins 5 and 6. (Shorting pins 5 and 6

causes gate2 of the quad IC to act as an invertor). Try it to convince yourselfof this.

5. Wire pin 6 to Logic Indicator 6. This is the invertor output.6. Wire pin 4 to Indicator 4. The is the invertor and

overall circuitoutput.

7. Switch S2 and S3 to LOW.8. The schematic for the circuit you have just

constructed isshown below in Figure 3-11.SEE PAGE 39 FOR FIGURE 3.11 (IT IS 3.10 IN REGULAR VERSION).

9. Turn on power to CADET. Indicator 6 should be HIGH.10. Indicators 1 and 2 monitor the state of S2 and S3.

Indicator 6monitors the NOR gate output. Indicator 4 monitors the circuitoutput. Use S2, S3, and Indicator 4 to create a truth table for thiscircuit. Record this truth table. What logic operation is this?

11. Turn your CADET off. You will now wire invertors into theinputs of the existing circuit.

12. Remove the wire at S2 and connect it to pin 10.13. Remove the wire at S3 and connect it to pin 13.14. Connect S3 to pins 11 and 12, and S2 to pins 8 and 9. The

schematic for this circuit is shown in FIGURE 3.12. FIGURE3.12 IS SHOWN ON PAGE 40 AS FIGURE 3.11.

15. Switch SI and S2 to LO. Turn on power. Use S2, S3, and LogicIndicator 4 to make a truth table for the circuit. Record your ob-servations. What logic function is performed by this circuit?

16. Use S2, S3, and Indicator 6 to make a truth table for the circuitconsisting of gates 4,3, and 1. Record your observations.Which logic function is implemented by this circuit?

17. Flip S2 and S3 HI and LO together while watching Logic Indicators 6 and 4 (output). Record your observations in the form of a truth table.

Questions 1. Which logic function is performed by the circuit observedin step 19?_________________________________________

2. All of the basic Boolean functions have beendemonstrated using the 74LS02 quad two-input NOR gate. Design a circuit to implement the basic Booleanfunctions. Use the 74LS00 quad two-input NAND asyour IC. Describe which gate combinations performwhich Boolean functions. Breadboard your circuit andcheck it's operation.

COMBINATIONAL LOGIC CIRCUITS

In Chapter Three individual gates were investigated. This chapter will use those gates in combination to produce more complex logic functions. Techniques for simplifying these complex functions will also be covered.

Simplification of logic circuits is a responsibility of the designer. Simpler circuits are generally more economic and more reliable. The economy is achieved by using fewer integrated circuits while reliability is achieved by having fewer

solder connections in the finished product

4.0 INTRODUCTION

Upon completion of this chapter you should be able to:

• Simplify logic expressions.

• Simplify logic circuits.

• Use the Karnaugh map to simplify logic circuits andexpressions.

4.1 OBJECTIVES

4.2 SUM-OF-PRODUCT FORM

The sum-of-product form of a logic circuit output looks like the following examples:

These examples show that the output of a logic circuit represented by x, z, or f are a logic one, or are true, when any of the logic products separated by the OR (+) designation are satisfied. The logic expressions completely define a logic circuit's operation in terms of the state of the logic inputs.

Logic equations may be formed directly from a truth table. These equations may also be simplified using Boolean algebra or more mechanical methods. Both types of simplification will be covered. The logic equations shown in the above examples are called "minterm" expressions.

Minterm expressions are logical equations where the logical product terms are separated by the logical sum operator. Minterm expressions are formed directly from truth tables. Minterm expressions are also called sum-of-product expressions.

4.3 DESIGNINGCOMBINATION

CIRCUITS

Logic design begins with a problem statement. The problem statement is analyzed and translated into logic variable inputs. A truth table is then constructed to show when a logic one output is to be produced. Next a sum-of-product (minterm) logic equation is then produced. Then a circuit is drawn from the sum-of-product logic equation. These steps are illustrated by the following example.

Problem statement: An alarm is to be used in an automated ink bottling plant. A conveyer belt carries the empty ink bottles past the filling spout. The alarm is to sound if any of the following conditions occur:

A. The ink tank runs empty.

B. There are no bottles on the conveyor belt even if ink is inthe tank.

C. There is ink in the tank, bottles on the conveyor belt, andelectric power is lost.

The first step is to assign variables to the inputs.

I = ink in the tank

B = bottles on the conveyor belt

P = electric power is on

Next a truth table is constructed using these variables for inputs and indicating when the alarm is to ring by placing a one in the output, X, column. A minterm expression is then written. (See Table 4-1)

Table 4-1 has a one in the output, X, for all cases where ink is not present (I). In fact, the truth table shows that the alarm will not sound, X=0, when ink is present and bottles are present and power is on. Any other condition will sound the alarm.

Analyzing the minterm or sum-of products expression shows that the alarm system may be directly implemented by using a seven input OR gate with each input being fed by a three input AND gate. This circuit implementation is shown in Figure 4-1.

Figure 4-1 could be further complicated by including inverter circuits to form the "NOT" inputs. This circuit will fulfill the design objective of the problem, but may not be the simplest circuit.

4.4 BOOLEAN SIMPLIFICATION

One method of circuit or minterm simplification is to use Boolean algebra l:o remove logic redundancy. This method is based on the Boolean single and multivariable theorems. The Boolean theorems are summarized in Table 4-2.

The first term of the original expression can be used again with the last term of the expression:

This final expression is logically equivalent to the original minterm expression. Figure 4-2 shows the final simplified circuit to implement the alarm system of the original problem. This solution is simpler, less expensive, and more reliable.This solution is simpler, less expensive, and more reliable.

Boolean algebra can be used for logic circuit simplification, but most students find the Karnaugh map technique to be easier. The Karnaugh map technique will be discussed shortly.

DeMorgan's theorem is important enough to command its own major heading in any digital text. DeMorgan's Theorem will allow the expression of logic equations in maxterm or product-of-sum form. (See Figure 4-3)

4.5 DEMORGAN'S THEOREM

Since there are only two logic operators besides the NOT function, DeMorgan's Theorem simply states that if an operator is NOTed it becomes the other. The OR operator NOTed becomes the AND operator and if the AND operator is NOTed it becomes the OR logic operator. The importance of this Theorem will become increasingly apparent in following discussions.

4.6 THE KARNAUGH MAP

The Karnaugh map or K-map technique is a graphical device to simplify logic equations or the output of truth tables following a simple orderly process. The K-map technique can be used for any number of variables, but becomes a little hard to handle when more than lour input variables are considered. For this reason, the discussion of this technique will be limited to cases having no more than four input variables.

A K-map like a truth table displays the relationship between input variables and the desired or true output of a logic expression or truth table. The K-map presents this information as entries in boxes of a K-map rectangle. Figure 4-4 gives three examples. The examples become more complex as more input variables are involved. Note that each box in a K-map identifies a specific and unique combination of the input variables.

In viewing Figure 4-4, the following points should become apparent:

1. The logic equations, truth tables, and K-maps contain thesame information.

2. The addition of an input variable doubles the number ofentries in the truth tables and K-maps.

3. The K-maps are organized in a precise way. The entriesacross the top and down the side of the K-map arearranged so that only one variable changes. Thesepatterns should be carefully and faithfully observed.

Once a K-map has been constructed for a problem. The entries may be looped. The loops are formed around adjacent l's. The l's may be looped in groups of one, two, four, or eight. Examples of looping are shown in Figure 4-5. Each loop of a K-map represents a single term in the simplified logic equation-larger and fewer loops result in the most simplification.

1. Construct the K-map from the original equation or truthtable.

2. Carefully examine the K-map for adjacent l's and loopthe largest number of adjacent Is (two, lour, or eight).

3. Loop any pairs necessary to include any adjacent l's thathave not yet been included in a loop.

4. Loop any remaining single or isolated l's.

5. Any variable appearing in a loop in both its true andcomplemented form is eliminated.

6. Form the simplified sum of products equation from allthe terms generated by the loops.

Figure 4-6 shows some examples of the power of using the K-map technique. Both the original and simplified logic equation is given for each example.

In the examples, each loop that is drawn results in a single term of the simplified equation. Ones may be used in more than a single loop as shown in the second example. Isolated ones become the most complex terms, as shown in the second example.

This technique can be applied to the ink factory alarm logic of the original example shown in Table 4-1. Figure 4-7 shows the original equation, the K-map with loops drawn, and the final simplified equation. Note that the simplified equation is the same as the one obtained by applying Boolean algebra.

Figure 4-8 shows how careful consideration in recognizing "don't care" conditions and later changing "don't cares" to ones or zeros can greatly simplify a logic design. The trick is to recognize early in the design any "don't, care" conditions and identify them by using X instead of 1 or 0 in the truth table.

The opening section of this chapter discussed the sum-of-product form of equations. The implication was that there are other ways to express a logic equation. This other way is called the product-of-sums form. Figure 4-9 gives examples of this form for logic equations.

4.7 PRODUCT-OF-SUMS FORM

To create the product-of-sums form involves the use of DeMorgans Theorem. An example will be helpful in illustrating the concepts involved.

In Figure 4-10, the final product of-sums equation is logically equivalent to the original sum- of-products equation. Figure 4-11 shows how these two equations would be implemented.

The two logic circuits are equivalent.

The reason for interest in having two forms for logical equations is ease of implementation when using universal logic gates; NAND and NOR. The sum-of-product form is most easily implemented using all NAND gates, while the product-of-sums form is most easily implemented using all NOR gates. The examples given in Figures 4-10 and 4-11 are shown implemented using all NAND or all NOR gates.

The circuit using only NAND gates is logically equivalent to the circuit using only NOR gates. This can be verified by setting all possible input states to the two circuits and observe coincidence in the outputs.

4.8 THE EXCLUSIVE OR AND

EXCLUSIVE NOR CIRCUITS

The final topic of this

chapter deals with two gate structures that are not basic £;ate structures, but whose functions occur so frequently that they have earned their own symbols. These gate structures are often used in comparator circuits. Figure 4-13 indicates the symbols and truth tables for these logic gates.

The output of the Exclusive OR gate is true only when the two inputs are different. The output of the Exclusive NOR gate is true only when the two inputs are equal. Each of these gates may be produced using AND, OR, and NOT gates.

This chapter has introduced Boolean algebra and Karnaugh map techniques for simplifying logic circuits. Both single variable and multivariable theorems were covered as well as DeMorgan's theorem.

Product-of-sums and sum-of-products as two forms of logic gates were introduced. Each of these forms are more easily implemented by either NAND or NOR universal gates.

Two important gate functions; the Exclusive OR and the Exclusive NOR were introduced.

4.9 SUMMARY

1. Determine the simplified logic equation for each of the K-maps in Figure 4-14.


2. Write the original equations used to form the K-maps of

Figure 4-14.

(a)______________________________________________________

(b)_____________________________________________________

(c)______________________________________________________

3. Sketch the outputs for the inputs shown in Figure 4-15.

4. In the space below, show how Exclusive OR and Exclusive NOR circuits are constructed from AND, OR, and NOT gates.

LAB EXERCISE 4.1Minterm and

Maxterm TruthTables

Objectives

Materials

Procedure

In this lab exercise you will learn the use of minterm and maxterm truth tables. You will also demonstrate the equivalence of tie minterm and maxterm forms of a logic expression.

CA.D.E.T.

74LS08 Quad 2-Input AND

74LS04 Hex Inverters

74LS11 Triple 3-Input AND

74LS32 Quad 2-Input OR

Jumper Wires(Refer to Appendix for IC pinouts)

1. The truth tables used in this book until now have been minterm truth tables. Logic equations can be directly written from these tables in the sum of products form. (See Figure 4-16).

2. Insert a 74LS08 and 74LS04 in the breadboard of the C. A.D.E.T. Wire the power (+5 VDC) and ground pins for the ICs.

3- Wire LSI (Logic Switch 1) to pin 1 of the 2 74LS04 and to LI1 (Logic Indicator). Wire pin 2 of the 74LS04 to pin 1 of the 74LS08. This is for the A input.

4. Wire LS2 to LI2 and pin 2 of the 74LS08. LS2 will serve as the B

input.

5- Wire LI3 to pin 3 of the 74LS08. This is the circuit output.

Switch LSI & LS2 to LOW. Turn power ON.

7.LSI and LS2 are the A and B inputs which can be observed on LI1and LI2. Use LSI, LS2 and LS3 to determine a truth table for this logic circuit. Record this truth table.

8. Form the maxterm truth table for the truth table in step 7.Write equations for this function in product of sumsform.

9. Remove the circuit used in step 7. Insert a 74LS04, 74LS32 and74LS11 into the C. A.D.E.T. breadboard. Wire power and groundto these circuits.

10. Wire LSI to pin 1 of the 74LS04, pin 1 of the 74LS32 and LI1. Thisis the A input.

11. Wire pin 2 o f the 74LS04 to pins 5 and 9 of the 74LS32.

12. Wire LS2 to pin 3 of the 74LS04, LI2 and pins 2 and 4 of the 74LS32.This is the B input.

13. Wire pin 4 of the 74LS04 to pin 10 of the 74LS32.

14. Wire pins 3, 6 and 8 of the 74LS32 to pins 3,4 and 5 respectivelyon the 74LS11.

15. Wire pin 6 of the 74LS11 to LI3. This allows monitoring the circuitoutput.

16. Switch all logic switches to LOW. Turn ON power.

17. LSI is A, LS2 is B, and LI3 is the logic circuit output. Use LSI, LS2,and LI3 to construct a truth table for this circuit. Record the truthtable here. Leave the circuit connected and answer the followingquestions.

1. Compare the truth tables from steps 7 and 17. What doyou notice about them?

2. Draw schematic diagrams of the circuits that producedthe truth tables in steps 7 and 17.

3. Which circuit better performs this logic function ? (step 7or step 17?). Why?

Questions

In this lab exercise you will study and apply techniques to reduce redundant logic elements in combinational logic circuits.

LAB EXERCISE 4.2 Simplifying Logic Circuits

Objectives

Materials

C.A.D.E.T.

74LS04 Hex Inverter

74LS08 Quad

2-Input AND

74LS27 Triple 3-Input NOR

74LS32 Quad 2-Input OR

Jumper Wires(Refer to Appendix for IC pinouts.)

1. A truth table for a logic function is shown in Figure 4-18.From this truth table write the sum of products form of the logic equation represented by the truth table.

2. Insert a 74LS04, 74LS08 and 74LS27 into the C.A.D.E.T. breadboard. Wire power and ground to these ICs.

3. Wire LSI to 74LS04 pin 1, 74LS08 pin 9 and LI1. This is the Ainput.

4. Wire 74LS04 pin 2 to 74LS08 pins 1 and 4.

5. Wire LS2 to pin 3 of the 74LS04, pin 5 of the 74LS08, and LI2. Wire74LS04 pin 4 to 74LS08 pins 2 and 10. This is the B input.

6. Wire pins 3,, 6, and 8 of the 74LS08 to pins 3, 4, and 5, respectively,of the 74LS27.

7. Wire pin 6 of the 74LS27 to pin 5 of the 74LS04. Wire pin 6 of the74LS04 to LI3. This is the circuit output.

8.schematic for the circuit constructed is shown inFigure 4-19.

9. Switch all logic switches to LOW. Turn ON power. LI3 shouldshow a HIGH.

10. Use LSI, LS2, and LI3 to construct a truth table for this circuit.Record the truth table here.

11. This circuit has redundant elements. It could beconverted to function the same with fewer components.We shall use Karnaugh maps to reduce the logiccircuitry.

12. A generalized Karnaugh map for two variables is shownin Figure 4-20.

13. Use the truth table to fill the Karnaugh map with ones where appropriate. Form loops on the map. Record your results.

14. Write the simplified logic equation for this map here.

Questions

15. Remove the previous circuit from the breadboard. Put a74LS04 and a 74LS32 onto the breadboard and wire powerand ground to them.

16. Wire LS2 to pin 1 of the 74LS04 and Ul. Wire pin 2 of the 74LS04to pin 1 of the 74LS32.

17. Wire LS2 to pin 3 of the 74LS04 and LI2. Wire pin 4 of the 74LS04to pin 2 of the 74LS32.

18. Wire pin 3 of the 74LS32 to LI3.

19. Switch all logic switches to LOW and turn ON power. LI3 shouldshow a HIGH.

20. LSI is A, LS2 is B and LI3 the circuit output. Use LSI, LS2, and LI3to construct a truth table for this circuit. Record your observations.

21. Leave this circuit connected while you answer thefollowing questions.

1. What is the common name for the logic function displayed in the truth table in step 1?

2. What do you notice about the truth tables resulting fromsteps 10 and 20 ?

3. What do you call the simplified logic equation from theresults of step 14 ?

4. Which of the circuits is better to use? Why?

You will learn about decoders in this lab exercise. You will study the simple decoder and the one of four decoder.

C.A.D.E.T. 74LS04 Hex

Inverter 74LS08 Quad 2-

Input AND 74LS11 Triple 3-

Input AND


1. The simple decoder will be studied first. A decoder detects the presence of a specific binary number or word. The decoder is usually formed from AND and NOT gates. Decoders are used extensively in computers for enabling memory and I/O devices.

LAB EXERCISE 4.3DecodersObjectives

Materials

Procedure

2. Place a 74LS11 on the C.A.D.E.T. breadboard. Wire the circuit shown. (See Figure 4-21)

3. Switch all logic switches to LOW and apply power.

4. Use LSI, LS2, LS3, and LI1 to determine the truth table for thiscircuit. Record your observations here.

5. Turn off power and remove the circuit from step 4.

6. Place a 74LS04 and a 74LS08 on the C.A.D.E.T. breadboard. Wirepower and ground for these circuits.

7. Wire the circuit shown in Figure 4-22. This circuit is aone of four decoder.

8. Turn the logic switches to LOW. Turn ON power. LI1 should showa HIGH.

9. Use LSI, LS2, and LI1-LI4 to form a table of the circuit operation.

10. Leave the circuit wired while you answer the followingquestions.

1. What binary number does the circuit from Step 4 decode?

2. Name one use of a circuit like the one in Figure 4-6.

3. Explain the operation of the one of four decoder.

4. Design a circuit to decode 101 binary.

5. Circuits similar to the one of four decoder are used toconvert from BCD to decimal. How many AND gateswill be required to implement such a circuit ? Hint:Examine Figure 4-22 schematic.

Questions

6. Why can't the logic equation from the truth table of step 9 be written as y = AB + AB + AB + AB ?

LAB EXERCISE 4.4 Encoders

Objectives

Materials

In this lab exercise encoders will be studied. Encoders accept one or more inputs and generate a multi-bit binary output. You will study a simple encoder. The basic encoder circuit is the positive NAND gate.

C.A.D.E.T.

74LS00 Quad 2-Input NAND


Procedure1. Wire the circuit shown in Figure 4-23. Note that PB1 and PB2, the C. A.D.E.T. pushbuttons, have normally high and normally low connections. (See Figure 3.10)

2. Switch LS3 to LOW. Turn ON power.

3. Press PB1, PB2, and LS3 one at a time. Note: LS3 will have to bemanually returned to HIGH. PB1 and PB2 return on their own.

4. Describe what happens when PB1 is pressed.

2. Record your observation when PB2 is pressed.

3. Place LS3 to LOW. Record your observations.

4. Return LS3 to HIGH.

5. Remove power from the circuit.

1. What does the circuit of step one do ? Questions

In this lab exercise the exclusive OR (EXOR) circuit and some applications of EXOR circuits will be studied.

C.A.D.E.T. 74LS04 Hex Inverter

74LS08 Quad 2-Input NAND

74LS32 Quad 2-Input OR 74LS86

Quad EXOR

Jumpers(Ref. to Appendix for IC pinouts.)

LAB EXERCISE 4.5 Exclusive OR CircuitsObjectives

Materials

Procedure 1 The truth table for the exclusive OR function is shown in Figure 4-24.

2. The logic expression for this truth table is .

3. Wire a circuit from the schematic in Figure 4-25.

4. Switch the logic switches to LOW and turn ON power.

5. Use LSI, LS2, and LI3 to form the truth table for this circuit. Record your observations here.

6. Notice that the circuit detects when the inputs are odd (not matched). For this reason, the EXOR is often called an odd/even detector.

7. Turn OFF power to the circuit. Remove the ICs from thebreadboard.

8. Place a 74LS86 into the C. A.D.E.T. breadboard.

9. Wire the circuit shown in Figure 4-26.

10. Switch logic switches to LOW and power ON.

11. Use LSI, LS2, and LI3 to form a truth table for this circuit. Record the truth table here.

12. You have focused on the logic circuit uses of the EXOR. The EXOR also performs a binary math function.

1. Examine the truth tables from steps 1, 5, and 11. What do you notice about them?

Questions

2. What math function does the EXOR gate perform ?

3. Which circuit is better to use, the one from step 3 or theone from step 9? Why?

4. Draw the Karnaugh map for the EXOR. Can this bereduced?

LAB EXERCISE 4.6 The EXNOR Circuit

Objectives

Materials

In this lab exercise the EXNOR circuit will be studied.

CA.D.E.T.

74LS04 Hex Inverter

74LS86 Quad EXOR

1. Wire the circuit shown in the schematic of Figure 4-27. Procedure

2. The EXNOR logic function is the complement of theEXOR.

3. Use LSI, LS2, and LI3 to determine the truth table for thiscircuit. Record the truth table here.

4. Note that the EXNOR compares the value of A and B andoutputs a 1 when the inputs are equal.

5. Remove the wire from LS2 and wire it to PB1 normally low.(See Figure 1 OB).

6. Operate LSI while observing LI3. Record your observations.

5. Write the EXNOR logic equation directly from thetruthtable.

6. What function does the circuit of step five perform ?

Questions

3. Make a Karnaugh map for the EXNOR function. Can this function be reduced?

FLIP FLOPS

This chapter will cover "flip-flops." A flip-flop is a digital logic element used for storing binary data. An element capable of storing data is often called a memory or latch. The two kinds of memory encountered in digital electronics are static and dynamic memories. The flip-flop is the basic form of static memory and is also the building block for sequential logic circuits. A primary characteristic of sequential logic circuits is the ability to "remember" the state of the inputs, i.e., memory.

Flip-flops are formed from pairs of logic gates where the gate outputs are fed into one of the inputs of the other gate in the pair. This results in a regenerative circuit having two stable output states (binary one and zero). Frequently additional gates are added for control of the circuit. While some flip-flops are operated asynchronously (without timing pulses), most are operated under clock control in a synchronous system.

Individual flip-flops can be combined to form memory registers , counters and shif t registers . A thorough understanding of the basic flip-flop is required for the study of these more complex circuits in later chapters.

5.0 INTRODUCTION


• Define and describe the action of a flip-flop.

• Describe and implement a "S-C" (set-clear) flip-flop.

• Describe and implement a "J-K" flip-flop.

• Describe and implement a "D" flip-flop.

• Explain and use a "T" flip-flop.

• Explain the difference between synchronous andasynchronous circuits.

• Describe some common applications of flip-flops.

• Explain what a One-shot is.

5.2 DISCUSSION In the introduction to this chapter, it was stated that a latch can be made from paired logic gates. While this is true, a simple latch can be formed from a single OR gate. The circuit is constructed by feeding the gate output back into one of the gate inputs as shown in Figure 5-1.

When the circuit output is in the LO state and the latch command input is LO the latch will have it's output remain low. When the latch command input is forced HI, the gate output will go HI. The feedback loop from the circuit output to the other gate input will cause the latch to remain in the HI state even when the HI logic level is removed from the latch

command input. The latch is now latched and the command input has no further effect. This circuit is not very practical as the only way to unlatch the output is to remove the power to the gate or to break the feedback connection from the gate's output to the input. Such a latch could be useful under some conditions and is used here to show the basic working of a latch. A similar circuit can be constructed from a pair of NOR gates. The gates are connected as shown in Figure 5-2.

The right most gate in this circuit complements the output (Q) and the feedback signal to the gate input. The circuit functions the same as the circuit described in Figure 5-1 since complementing the NOR gate output results in the OR function being performed. The advantage of this circuit is that it gives the user access to the complement of the Q output. The circuit shown in Figure 5-2 will take a little more time to latch than the circuit of 5-1 since two gates will have to switch for the circuit to latch. This circuit is still not extremely useful since it is difficult to unlatch the circuit.

The circuit of Figure 5-2 can be greatly improved by disconnecting one of the inverter stage inputs and using it as the clear input for the latch. This is illustrated in Figure 5-3.

5.2.0 Set-Clear Flip-flops

The operation of this circuit is straightforward. Assume that initially the Set and Clear inputs and the Q output are all LO. If the Set input is forced HI while the Clear input is forced

LO, the Q output will be forced to the HI state. The HI Q output causes the complement output to be LO. If the Set line now returns to LO, the Q output will remain HI as long as the Clear input is LO.

The flip-flop can be cleared by bringing the Clear input HI while holding the Set input LO. This results in a LO on the Q output. The LO Q output results in a HI on the complement output. At this point the Clear input can return to the LO state and the flip-flop is cleared until the next Set command is received.

This is all well and good but what if the Clear and Set inputs are brought to the HI state at the same time? This would result in the true and complement outputs both having to be LO. This state is not allowed since two complement outputs cannot have the same state. The circuit will respond with a race condition with the circuit outputs being LO. For this reason much effort is expended to make certain that the Set and Clear inputs are never both logic one. Additionally, while both inputs can be LO at the same time they cannot reach the LO condition simultaneously without resulting in a race condition with unpredictable circuit outputs. Many refinements to this basic S-C flip-flop were designed to avoid this indeterminate state.

Latches can also be constructed from NAND gates. Figure 5-4 shows a simple NAND latch.

Notice that the latch command input is normally HI and that a LO input is used to Set the latch. A Set-Clear latch can be constructed from NAND gates as shown in Figure 5-5.

The latch performs similarly to the NOR S-C latch except that a LO input is required to activate the Set and Clear inputs. The forbidden state is when S and C are both LO.

The simple NOR S-C latch can give unreliable and unpredictable outputs if both of the inputs to the latch go to the HI or arrive at the LO state simultaneously. The first case is not allowed and the second case results in a race condition with unpredictable outputs. One way of avoiding both of these circumstances is to provide hardware so that the Set and Clear inputs can never have the same state. This can be accomplished with an inverter as shown in Figure 5-6.

5.2.1 The "DM Type Latch

This circuit is known as a D latch and the circuit input is called the D input. The D latch can also be constructed from NAND gates and inverters as shown in Figure 5-7.

5.2.2 Clock Signals

The circuits shown in Figures 5-6 and 5-7 are active HI in that Q goes HI when D goes HI. These latches can be made to perform as active LO circuits by changing which of the inputs to the S-C latch is inverted. The inverter bubble is used to denote the active low D input in schematic diagrams.

The circuits studied up to this point have been entirely based on combinational logic circuits. This sort of circuit has the state of its output change when the input states change. Circuits of this type are said to operate asynchronously. Asynchronous circuits cannot usefully transfer data to or receive data from other flip-flops.

The ability to be chained (receive and transfer data to other flip-flops) is important for making counter circuits which count the number of pulses received by the circuit. This ability to be chained is also important for constructing registers (small arrays of latches) where inputs can be transferred or shifted from one element of the register to the next. The simple latches studied up to this point cannot be chained because of the inherent

system gate delays and settling time. If we are to transfer states from one flip-flop to another all flip-flops concerned must have completed any previous change and be settled into their present state before a change is attempted. The variable gate delays and settling times between flip-flops prevents this from happening in any extensive circuit particularly when the circuit is operated at high speeds.

Different circuit characteristics result in one of the flip-flops in the chain receiving an input before it is ready and hence one of the states or bits is lost. Another problem that can occur if simple latches are used for counting and shift register circuits is that an input into one end of the directly coupled chain will race through the chain of circuits without stepping. This results in a totally useless circuit.

The solution to these problems is to provide a timing or clock signal that allows all of the flip-flops of the chained circuits to switch simultaneously or synchronously tinder control of the clock. This means that in clocked circuits the outputs do not change as soon as the inputs change but must wait for a clock signal before the output state can change.

A clocked S-C flip-flop can be formed by adding two more NAND gates to the simple S-C flip-flop as shown in Figure 5-8.

5.2.3 Clocked "S-C" Flip-flops

Notice that this circuit only provides clock control of the S-C flip-flop which will still have two sets of conditions which cannot be used in any worthwhile circuit. The Set and Clear inputs are only passed to the main section of the flip-flop when the clock input is HI.

5.2.4 Clocked "T" Flip-flops

The clocked T flip-flop is a modification of the clocked S-C flip-flop. The true and complement outputs are fed back as shown in Figure 5-9 to act as the Set and Clear inputs .

When the flip-flop is set the HI Q output is feedback to the reset input. When the next clock pulse occurs, the latch is cleared. The HI Q output is fedback to the set input. When the next clock pulse occurs the latch is set. Note that two clock pulses were needed to change the output state from Set to Clear and back to Set. This type of circuit is called a T flip-flop because of the way the output of the flip-flop toggles or changes to the opposite state with each clock pulse. A timing diagram for the T flip-flop is shown in Figure 5-10.

Notice that the frequency of the output signal is one half of the input clock signal frequency. For this reason a circuit of this type is often called a two to one frequency divider. The type T flip-flop is not available as a TTL integrated circuit; however, a circuit of this type is easily constructed from available devices.

We have already studied the D latch. The truth table for the latch shown in Figure 5-7 reveals some interesting qualities of the D latch. Notice that the true output could be replaced with a wire between the D input and the Q output. Similarly, the complement output could be replaced with an inverter between the input and output. The Q output is said to be "transparent" to the D input since the circuit acts as though a wire were connected between D and Q. This circuit is useless as was shown earlier but can be turned into z useful circuit with only a small amount of additional circuitry.

Initially one might be tempted to add in AND gate to the input as was done to the S-C flip-flop to form the clocked S-C flip-flop. This would not work since the input to the D latch would go LO whenever the clock signal went LO regardless of the state of the D input. The circuitry needed to gate the data input into the D latch is shown in Figure 5-11.

5.2.5 Clocked "D" Flip-flops

Notice that when the clock signal is HI, the data on the D input is transparent to the Q output. Where the clock signal is LO the data on the D input is blocked and the latch stores the output state at the time the clock went LO. The D flip-flop whether clocked or asynchronous is named for its ability to store data.

5.2.6 "J-K" Flip-flops D flip-flops are available as edge triggered TTL circuits with Preset and Clear asynchronous inputs that allow setting the initial state of the latch (edge triggered circuits will be explained in the laboratory for this chapter).

The last type of flip-flop you will study is the J-K flip-flop. This type of flip-flop can function as a clocked S-C flip-flop, a clocked D flip-flop a T flip-flop or can be used to perform other specialized functions. The J-K flip-flop has no ambiguous output states for any input states of the J,K or clock inputs. The J-K flip-flop circuit is shown in Figure 5-12.

The operating characteristics of the J-K flip-flop can be summarized as:

1. J and K inputs LO: when clock goes LO nothing happens.

2. J input HI, K input LO: when the clock goes LO, Q goes orstays HI. Q is LO. The HI on the J input is passed directlyto the Q output.

3. J input LO, K input HI: when the clock goes LO, Q goes LOand Q goes HI. The LO on the J input is passed directly tothe Q output.

4. J and K inputs HI: the circuit toggles on each clock pulse.The circuit now behaves like a T flip-flop.

The J-K flip-flop is very flexible and can be used to perform many of the flip-flop functions already studied. The configuration to perform these functions with a J-K flip-flop is shown in Figure 5-13.

While the J-K flip-flop can perform all of these functions, use of other types of flip-flops may be more economical. The J-K flip-flop is often used in the Master-Slave configuration. In this configuration the state of the flip-flop is determined by the state of the Q output of the Slave flip-flop. The input states to the Slave flip-flop are controlled by the master flip-flop. A circuit diagram for the Master-Slave J-K flip-flop is shown in Figure 5-14.

5.2.7 Counting and Frequency Division

Notice that the J and K inputs determine the state of the Master flip-flop. The clock signal is fed to both sections of the Master-Slave, but is inverted for input to the Slave section.

The operation of this circuit is most readily understood in terms of the clock signal. Assume that the circuit shown is pulse triggered (this only means that we have added no special circuits to cause the circuit to trigger on the edge of the clock pulse). When this is the case, the Master flip-flop will change state to correspond to the state of the J and K inputs when the clock pulse is HI. During this time, the Slave flip-flop will not respond to the outputs from the Master flip-flop because of the inverted clock. When the clock has been HI for a while, the state of the Master flip-flop will be stable and the Slave flip-flop will still be locked out from responding to the outputs of the Master flip-flop. When the clock makes the HI to LO transition, the Master flip-flop will not respond to the J and K inputs since the clock is LO. The inverted clock to the Slave flip-flop will cause the Slave flip-flop to respond to the Q and Q outputs of the Master flip-flop. The output of the Slave flip-flop will settle shortly after the falling edge of the input clock pulse.

The Master flip-flop will not respond to the J and K inputs until the next positive going clock transition. The J and K inputs must be stable while the clock is HI for this type of circuit to function correctly.

J-K flip-flops ire available as both edge triggered and pulse triggered circuits in the TTL product series. This type of flip-flop is also available with Preset and Clear inputs for setting the in i t ia l s t a te of the outputs . These inputs opera te asynchronously and cannot be LO simultaneously.

Two common applications of J-K flip flops are counting and frequency division. As discussed previously, a J-K flip-flop can be configured to perform as a T flip-flop. This circuit will have an output pulse whose frequency is one-half of the input clock frequency. My number of these type of flip-flops may be connected with the Q output of the previous stage serving as the clock input to the next stage to provide frequency division by any integer power of two. For instance two flip-flops connected in this manner will have an output frequency equal to one-fourth of the input clock frequency.

A simple counter can be constructed from similar circuits. The J and K outputs are tied HI to form T flip-flops. The Q output of the previous stage is fed to the clock input of the next stage. The Q output also indicates the binary value of the counter. The first Q output has a value of I, the second a value of 2 , the third a value of 4 and so forth. A circuit such as this is known as a "binary ripple up-counter." The outputs of all flip-flops must be set to zero before counting is started if an accurate count is to be obtained. Other types of counters will be covered in later chapters.

Until now all circuits in this chapter have been flip-flops. Flip-flops are also known as bistable multivibrators. A circuit closely related to the flip-flop is the mono stable multivibrator. This is a circuit which has only one stable slate. When a trigger pulse is received on the input to the circuit, the output of the monostable multivibrator produces a single output pulse. For this reason, circuits of this type are often called "one- shots."

The duration of the output pulse can be set using external components connected to the pulse length controlling inputs of the one-shot IC. Several types of one-shots are available in the TTL series of ICs. Some have special conditioning circuits on the input to the one-shot to allow slowly changing input pulses to trigger the circuit. Some one-shots are like the one described above which will not respond to additional trigger pulses while the output is in the unstable state.

Retriggerable circuits which will respond to additional trigger inputs while in the unstable state are also available. One-shots are widely used for contact debouncing so that multiple input pulses from a switch are converted to a single output pulse. One-shots are also used to provide pulses of a fixed length from pulse trains composed of varying length pulses.

5.2.8 Monostable Multivibrators

This chapter covered several kinds of latches and flip-flops. You have become familiar with the circuit diagrams for and the operation of six types of common flip-flops. You have seen the difference between asynchronous and synchronous logic circuits and were introduced to clock signals. You have been introduced to the use of flip-flopsin frequency division and counting

5.3 SUMMARY

circuits. The one-shot and some of it's applications were covered.

This chapter forms the foundation for further study of sequential logic circuits in later chapters.


1. What is a flip-flop?

2. Draw the circuit diagram and schematic symbol for a S-Cflip-flop. Explain the operation of this circuit.

1. Why are clock signals used in sequential logic circuits?

1. What is the primary characteristic of sequential logiccircuits?

1. Name six types of flip-flops.

2. What is a name for a flip-flop other than latch?

3. What is a One-shot ?

4. Name an application of One-shots.

5. Name two applications of J-K flip-flops

6. What is the maximum count that can be contained in aripple counter made of three J-K flip-flops?

7. Would your answer to question 10 change for "T" flip-flops? Why?

LAB EXERCISE 5.1 Set-Clear Flip-flops

Objectives

Materials

Procedure

This lab exercise will focus on the Set-Clear flip-flops. You will study several methods of implementing the S-C flip-flops.

C.A.D.E.T.

74LS02 Quad 2-Input NOR IC

74LS00 Quad 2-Input NAND IC

Jumper Wires

TTL Data Book

Until now we have concentrated on learning the basics of flip-flop operation, To better understand these experiments some nuances of flip-flops must be understood. Most of the flip-flops discussed in the text were level or pulse triggered devices. These devices use the standard flip-flop notations. As was noted in the text active LO inputs to the flip-flops are designated by a bubble on the input pin. Another type of flip-flop which operates similarly is the edge triggered flip-flop. These devices will have the same basic truth table as the devices we have studied; however, the output will change states only on the positive (LO to Hit) or negative (HI to LO) edge of the clock pulses. Edge triggered inputs are shown by a triangle on the affected input as shown in Figure 5-15.

Circuits to accomplish the edge triggering functions are shown in Figure 5-16.

The operation of the circuits is possible because of the gate delay of the inverters. This gate delay results in a short duration pulse corresponding to the edge of the clock pulse. With these fundamentals you are ready to perform experiments with flip-flops.

1. Wire the circuit shown in Figure 5-17 using the 74LS02 NOR gate.

2. Wire the power and ground pins to the 74LS02 if you have not already done so. Switch LS1 and LS2 to LOW.

3. LSI is the Set input, LS2 the Clear input, LI2 the Q output andLI1 the Q output. Determine the truth table for this circuit andrecord your result here.

4. Wire the circuit for the NAND S-C flip-flop shown inFigure 5-18.

Questions

5. Wire power and ground to the 74LS00. Switch LSI and LS2 toLOW.

6. Turn power ON. LI2 should show a HIGH.

7. Use LSI, LS2, LI1, and LI2 to determine the truth table for thiscircuit. Record your observations here.

8. Remove power from this circuit and leave the circuit onthe circuit board for use in the next experiment.

1. Which states cause trouble for the NOR S-C flip-flop?

2. Which states cause trouble for the NAND S-C flip-flop?

3. What state should the inputs to a NOR S-C flip-flop bein?

4. What state should the inputs to a NAND S-C flip-flop bein?

In this lab exercise you will study the "D" latch. You will implement two types of "D" latches, one with active HI input and the other with active LO input.

C.A.D.E.T

74LS00 Quad NANDIC

74LS04 Hex Inverters IC

Jumper Wires

TTL Data Book

1. Wire the active HI "D" latch circuit shown in Figure 5-19 using the 74LS00 and 74LS04 ICs. If you have retained the circuit from laboratory 5-1, this will only require rewiring the two input lines to the S-C FF.

LAB EXERCISE 5.2 The "D" LatchObjectives

Materials

Procedure

Questions 2. Wire power and ground to all circuits.

3. Use LSI as the D input, LI2 as the Q output, and LI1 as thecomplement output. Construct a truth table for thiscircuit.

4. Now, turn off power and swap the wires connected topins 1 and 5 of the 74LS00. This will result in a lowactive "D" latch.

5. Use LSI, LI2, and LI3 to determine the truth table for thiscircuit. Record your observations here.

6. Leave this circuit connected while you answer the

following questions.

1. What do you notice about the circuit of Figure 5-19? Howcould this circuit be simplified?

2. How could the circuit of step 5 be constructed using onlyone IC? Build a circuit to test your solution.

In this lab exercise we will study the clocked S-C flip-flops and clock signals.

C.A.D.E.T.

74LS00IC Jumper

Wires TTL Data

Book

In order to perform this experiment you will need to know some-thing about clock signals. Clock signals are periodically spaced binary pulses. These pulses are used for circuit timing in sequential logic circuits. The duty cycle of a clock signal is the pulse length divided by the period and is expressed as a percentage by multiplying the quotient by 100. Clock impulses are provided on the CADET using the TTL output on the Function Generator Connector. (It may be wise to review the Function Generator description in Appendix B of your manual. Set the kHz/Hz switch to Hz; the range switch (1 /10/100) to 1. Set the Sine, Tri, Square Wave switch to square wave; and the FREQ potentiometer all the way up. The AMPlitude pot has no effect on the output amplitude if you use the TTL output so its setting will make no difference.

1. Connect the Function Generator TTL to LI.2. Set the Generator Range to 1Hz. Turn on the power andobserve L7. Record your observation. If a scope is available,observe the clock pulse and sketch what you see.(Remainder of Chapter 5 through page 103 corrected in themanual).

LAB EXERCISE 5.3 The Clocked Set-Clear Flip-flopsObjectives

Materials

Procedure

4. Turn-off power and wire the circuit shown in Figure 5-20.

Questions

5. Use LSI as the Set input, LS2 as the Clear or Reset input, FG/TTL and PB2 for the clock input, LI1 as the Q output, and LI2 asthe Q output to construct a truth table for this circuit. Recordyour observations here.

6. Record your observations of the outputs if the clock inputis not actuated.

1. Does adding the clock circuitry cure the inherent flaws ofthe S-C flip-flop circuit? Explain.

2. When do the input signals have an effect on the outputstates?

In this lab exercise we will study the implementation and application of "T" flip-flops.

C.A.D.E.T.

74LS74 Dual "D" Type Positive Edge Triggered Flip-flop With Preset and Clear

Jumper Wires

TTL Data Book

1. Use the 74LS74 IC to construct the circuit shown in Figure5-21.

LAB EXERCISE 5.4 The "T" Flip-flopsObjectives

Materials

Procedure

2. The feedback of the complement output to the D inputresults in the toggle operation. Wire power and groundto the IC.

3. Turn on power and record the initial state of the latch.

4. Record your observation of LI1 and LI7, clock, while pressingPB2 several times.

5. Turn power OFF. Remove the wire to PB2 and place it on theFG/TTL. Set clock frequency to 1 Hz.

Questions 6. Turn power ON and observe the clock and "T" flip-flop outputson LI7 and LI1 respectively. Record your observation here.

7. Leave this circuit connected while answering thefollowing questions.

1. What effect does the "T" flip-flop have on binary pulsetrains?

2. In Step 4 how many times do you have to push PB2before the flip-flop output toggles through an entire cycle(example: starts LO goes HI, then end LO)?

LAB EXERCISE 5.5The Clocked "D"

Flip-flops

Objectives

Materials

Procedure

In this lab exercise you will study clocked "D" flip-flops.

C.A.D.E.T.

74LS74 Dual "D" Type Positive Edge Triggered Flip-flop With Preset and Clear

Jumper Wires TTL

Data Book

1. Wire the circuit shown in Figure 5-22 using the 74LS74.

2. Wire power to the IC and switch LSI to LOW.

3. Use LSI as the D input, PB2 as the clock input and LI1 as the Qoutput and create a truth table for the clocked "D" flip-flop.Record this truth table here.

4. Use PB2 to determine on which edge of the clock pulsethe "D" latch changes state.

5. Remove power from the circuit and disassemble it.

1. From the results of step 4 describe the switching action ofthe 74LS74.

2. Is this an active HI or active LO circuit?

Questions

LAB EXERCISE 5.6 The "J-K" Flip-flops

Objectives

Materials

Procedure

In this lab exercise you will study the "J-K" flip-flop and its applications.

C.A.D.E.T.

74LS76 Dual J-K Flip-flop With Preset and Clear

74LS04 Quad Hex Inverters

Jumper Wires

TTL Data Book

1. Wire the circuit shown in Figure 5-23 using the 74LS76 IC. Make sure Vcc and GND pin are wired correctly. Leave room on the breadboard for the 74LS04 IC.

2. Wire power and ground to this circuit. Switch LSI and LS2 toLOW. Wire Set and Clear to +5VDC.

3. Turn on power. Observe the initial state of the latch.

4. Use LSI, LS2, PB2 with LI1 and LI2 to make a truth table for the"J-K" flip-flop.

5. Switch LSI and LS2 to the HIGH state. Turn off power. Connectthe wire at PB2 to the TTL signal of the Function Generator andLI7.

6. Turn on power. Observe the clock on LIZ and the FF output onLI1. Describe your observations.

7. Turn off power. Wire the circuit shown in Figure 5-24.

8. Wire power and ground to these circuits. Use LSI, III, and LI7to make a truth table for this circuit.

9. Leave this circuit connected while answering thefollowing questions.

1. If both J and K inputs are held HI as in steps 5 and 6 whatfunction is the J-K flip-flop performing?

2. What latch function does the circuit of step eightperform?

Questions

LAB EXERCISE 5.7 The One-shot

Objectives

Materials

Procedure

In this laboratory you will learn about the monostable multivibrator or one-shot.

C.A.D.E.T.

74121 Monostable Multivibrator With Schmitt-Trigger Inputs. (Refer to Appendix for IC pinouts.)

Assorted Resistors

Assorted Capacitors

Jumper Wires TTL

Data Book

1. Wire the circuit shown in Figure 5-25.

2. Wire power and ground to the circuit.

3. Turn on power. What do you notice about LI7?

2. Press PB2. What happened to LI7.

3. Turn off power. Remove the 100 k ohm resistor and puta 47 k ohm resistor in its place.

4. Turn on power and press PB2. What did you observe?Compare this pulse with the pulse obtained in Step 4.

5. Turn off power to this circuit.

1. Name one use of a One-shot IC.

2. Explain the name One-shot.

Questions

ctemedia.s3.amazonaws.com · web viewlab exercise 4.3 decoders 65 lab exercise 4.4 encoders 68 lab...

Documents