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ISSUE 1597 MONDAY, MARCH 7, 2011 WWW.EETIMES.COMEE Times

March 7, 2011 Electronic Engineering Times 3

CONTENTS MARCH 7, 2011

OPINION 4 Commentary: iPad 2 faces

crowded dual-core tab field

50 Last Word: Patent reform actjeopardizes innovation

NEWS OF THE TIMES 7 Intel details Sandy Bridge

12 Images from ISSCC

14 China chases petaflops;IBM pushes past 5 GHz

GLOBAL WATCH 18 Nikon tips litho road map

COVER STORY 20 Thunderbolt interface

rattles placid PC landscape

INTELLIGENCE 26 Millimeter-scale computer

targets medtech

DESIGN + PRODUCTS Global Features

31 Unlocking multicore’s full potential

38 Model-driven developmentfor multicore software

42 How manycore will reshape EDA

44 Planet Analog: Why measure differential gainand phase?

EE LIFE 48 Practical Jokes

Raising alarms; Lowbrowfun with highfalutin math;Press ‘del’ to stop . . .

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4 Electronic Engineering Times March 7, 2011

COMMENTARY

Apple held a commanding 84.7 per-cent share of the 17-million strongtablet market in 2010, according toInternational Data Corp., as it shippedthe iPad months earlier than its near-est competitor, the Samsung GalaxyTab. Fueled by the addition of manynew vendors, IDC expects the tabletmarket to grow to 44 million units thisyear and more than 70 mil-lion in 2012.

Last year, Apple sold near-ly 50 million total systemswith its single-core A4processor, nearly four

times as many units as the company’sX86-based PCs, according to estimatesfrom market watcher IHS iSuppli.

Apple currently offers five productsbased on the A4: the first-generationiPad, both the GSM (AT&T) and CDMA(Verizon Wireless) versions of theiPhone 4, the iPod Touch and Apple TV.The iPad 2 is Apple’s first product to useits new, dual-core A5 CPU.

In 2011, however, Apple faces a hostof top tier competitors, all with giga-hertz-class chips.

Some powerful competitionHewlett-Packard Co. has announced awebOS tablet based on a dual-core Qual-comm Snapdragon processor, while LG

Corp., Motorola Mobility Inc. and Sam-sung Electronics have all introducedAndroid tablets based on Nvidia’s Tegra2 chip. Research in Motion, meanwhile,is ramping up a beta program for itsPlayBook tablet using a dual-core ARM

Cortex-A9 OMAP 4430 processor fromTexas Instruments.

“This is the year for dual-coretablets—there’s no doubt about that,”said Nathan Brookwood, principal ofmarket watcher Insight64 (Saratoga,Calif.), who attended the original iPadlaunch last year.

The extra horsepower is helping shifttablets from content consumption tocontent creation systems, Brookwoodnoted, citing Apple’s new Garage Bandand iMovie apps for the iPad. “That’swhere the extra core will come inhandy,” he said.

“I was a little disappointed they aresticking with the same resolution [as inthe original iPad]; however, they do

have an HDMI port on the iPad 2 tohook up to large-screen TVs,” he added.

Apple CEO Jobs, who returned frommedical leave to launch the iPad 2 inSan Francisco, said at the event, “Theseare post-PC devices that need to be easi-er and more intuitive than a PC, and thesoftware, hardware and applicationsneed to intertwine in an even moreseamless way than on a PC.”

“In the new design paradigm ofsmartphones and tablets, computingefficiency trumps raw computing pow-er,” agreed Wayne Lam, senior analystfor competitive analysis at informationservices company IHS. “Designs like theiPad demand highly integrated micro-processors that emphasize graphics per-formance, lower power consumptionand small space usage.”

Details about the Apple A5 chip andother iPad 2 electronics will have towait until systems become available forteardown experts.

The A5 runs at the same frequency asthe A4. Adding a second core alonewould not provide the doubling of per-formance or ninefold increase in graph-ics that Apple claims.

Brookwood suggested Apple mayhave shifted from the ARM Cortex-A8core in its A4 chip to a Cortex-A9,upgraded a separate graphics core andthrown in a few other tricks as well. p

By Rick Merritt ([email protected]),computing and medical devices editor atEE Times.

READERS RESPOND

Fundamentally, this is the same device; ifthey go smaller or bigger, people will com-plain. Interestingly, there is no bump in reso-lution. It will be interesting to see if theirsunlight performance is better. — selinz

Two cores = double the speed. It sounds tome like a marketing slogan. I am lookingforward to Apple revealing the completespecification of the iPad 2.— chanj

I like higher speed (even though it is notdouble), but I would like to know moreabout any new special features from thisdevice that hopefully can rock the world.

— GREAT-Terry

The iPad 2, introduced by Steve Jobs and com-pany on March 3, joins a growing chorus ofdual-core tablets in what the Apple chief execu-tive hails as the post-PC era. Although Applelacks a jump on competitors in the currentround of tablets, observers expect it’ll do wellwith the iPad 2 and new A5 system-on-chip.

iPad 2 faces crowdeddual-core tablet field

>> Find out how LabVIEW can make you better at ni.com/labview/better 800 453 6202

©2010 National Instruments. All rights reserved. LabVIEW, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. 2781

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OF THE TIMESNews

Intel details Sandy Bridge platform By Dylan McGrath

SAN FRANCISCO—Intel Corp. dis-closed more technical details of its 32-nanometer Sandy Bridge processor atthe International Solid-State CircuitsConference (ISSCC) on Feb. 22. Thesemiconductor giant further describedthe platform’s modular ring intercon-nect, design techniques used to mini-mize the cache’s operational voltageand the inclusion of a debug bus tomonitor traffic on the interconnect.

The 32-nm Sandy Bridge processordie integrates up to four X86 cores and apower/performance optimized graphicprocessing unit, plus DDR3 memory

and PCI Express controllers, accordingto a paper presented at ISSCC by ErnestKnoll, a designer at Intel’s design centerin Haifa, Israel. Sandy Bridge features1.16 billion transistors and a die size of216 square millimeters, Knoll said.

The Sandy Bridge Intel Architecturecore implements several improve-ments that boost performance withoutincreasing power consumption. Theyinclude an improved branch-predictionalgorithm, a micro-operation cache anda floating-point advanced vector exten-sion, according to the Intel paper. Also,the devices’ CPUs and GPU share the

same 8 Mbytes of Level 3 cache.Although Intel organized the L3

cache units in four slices along withthe X86 cores—at 2 MB per core—they are fully shared with the GPU,Knoll said.

Sandy Bridge’s ring interconnect fab-ric connects all elements of the chip,including the CPUs, the GPU, the L3cache and the system agent. Because thering interconnect is modular, the four-core die can easily be converted into atwo-core die by “chopping” out twocores and two L3 cache modules, accord-ing to Knoll’s presentation. The initialversion of Sandy Bridge is available intwo- or four-core variations.

“By simply ‘chopping’ two slices, weget to another level of die,” Knoll noted.

Intel provided the first details on theSandy Bridge heterogeneous processors

PROCESSORARCHITECTURE

The 32-nm dieintegrates up to four X86 cores and a power/performanceoptimized GPU, plus DDR3 memoryand PCI Expresscontrollers

NEWS OFTHETIMES

at the Intel Developer Forum, also inSan Francisco, last September. It intro-duced the first Sandy Bridge products,the second generation of the company’sCore processor family, at the ConsumerElectronics Show in January.

Intel started shipping some SandyBridge devices in January as well. And itexpects those processors to find theirway into more than 500 laptop anddesktop PC designs by the end of 2011.

Eye on power savingsThe Intel paper revealed that becauseSandy Bridge’s X86 cores and L3 cacheshare the same power plane, the mini-mum voltage required to retain the L3 cache data could have limited theminimum operating voltage of thecores, thereby increasing the systempower consumption.

Intel got around the issue by develop-ing several circuit and logic design tech-niques to minimize the minimumoperational voltage of the L3 cache andthe register files of the chip, bringing itto a lower level than the core logic.

“One of the design targets was tominimize power consumption as much

as possible,” Knoll explained.One way Intel skirted the issue was

to implement a shared p-channel MOS-FET technique that weakens the effec-tive strength of the memory cell pull-updevice. That solved the problem of theRF writability degradation at low volt-ages that can occur as a result of manu-facturing process variations.

“We are able to improve the mini-mum operating voltage for a vast major-ity” of the chip, Knoll said.

Thanks to the use of these design tech-niques, Sandy Bridge’s power dissipationranges from 95 watts for a four-coredevice operating in a high-end desktopto 17 W for a two-core Sandy Bridge run-ning an optimized mobile product .

Sandy Bridge also introduces a debugbus that enables the monitoring of thetraffic between the X86 cores, GPU,caches and system agent on the proces-sor internal ring. The bus—dubbed the Generic Debug External Connection(GDXC)—allows chip, system or soft-ware debuggers to sample ring data traffic as well as ring protocol controlsignals and drive it to an external logicanalyzer, where it can be recovered

and analyzed.“The GDXC is a valuable tool for sys-

tem and software debuggers,” Knollsaid during his presentation.

Sandy Bridge also includes two typesof thermal sensors to monitor the tem-perature of the die. One is a diode-basedthermal sensor on each core that com-pares the diode voltage output to thetemperature, providing information forthrottling, catastrophic function andfan regulation. The second is a muchsmaller, CMOS-based thermal sensorwith a more limited temperature range.This one can be placed at several loca-tions inside the core to deliver an accu-rate picture of core hot spots.

Early this year, Intel discovered adesign flaw in one of the support chipsfor the first quad-core version of SandyBridge, which began shipping in Janu-ary. The company came up with a quickfix for the issue and temporarily haltedshipments of the support chip.

Intel later resumed shipments of the flawed chip to PC suppliers thatwere implementing it in systems forwhich the design flaw would not be an issue.p


Samsung’s chip chief: Phase-change RAM fights OEM headwindBy Mark LaPedus

NEXT-GENMEMORY

SAN FRANCISCO — Samsung Elec-tronics is looking to bolt out of thechute ahead of Micron TechnologyInc.’s Numonyx group in 1-Gbit phase-change RAM. The question is whetherthe race is warranted, since even thepresident of Samsung’s semiconductorbusiness has acknowledged that systemmakers’ response to PRAM and othernext-generation memory alternativeshas been tepid thus far.

Samsung revealed technical detailsfor its 1-Gbit PRAM on a 58-nanometerprocess at the International Solid-State

Circuits Conference here, but it did not say when devices would ship. TheSouth Korean giant reportedly hasshipped limited quantities of a 512-MbitPRAM. UBM TechInsights, part of thesame company that publishes EE Times,recently found a NOR-compatible 512-Mbit PRAM from Samsung in a mobilehandset (www.eetimes.com/4211190).

Numonyx, meanwhile, is late with a45-nm 1-Gbit offering that had beenslated to ship at the end of 2010. Newparent company Micron Tecnology saidlast summer that it was committed to

PRAM and expected Numonyx to pro-duce a 1-Gbit memory on a 45-nmprocess this year, but details have notbeen forthcoming.

“We are shipping a little bit” ofPRAM in the market, Oh-Hyun Kwon,president of Samsung’s semiconductorbusiness, told EE Times after hiskeynote address at ISSCC. “Phase-change has some very nice features,” hesaid, but “the systems guys” have been“very reluctant” to adopt the technolo-gy in mass quantities.

Indeed, during his keynote, Kwon



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acknowledged OEMs’ lukewarmresponse to next-generation memoriesin general, including magnetoresistiveand resistive RAM (MRAM and ReRAM)as well as PRAM. The problem is thatthe next-gen memory types “are notcompatible with today’s technology,” he said.

Kwon urged OEMs to collaboratewith memory houses to increase thealternative memories’ appeal and widentheir adoption.

Phase-change memory is based onchanging the material phase and theelectrical resistance of a chalcogenidelayer in each memory cell throughelectrical heating. It is an attractivetechnology because of its nonvolatility,theoretical high density and bit alter-ability, and it has been touted as a possible replacement for both flashand DRAM.

But while phase-change technologyhas been on the radar for decades, it has proved difficult to commercialize.Devices based on 90- and 65-nm process-es have made it to market, but ques-tions have been raised about the abilityto scale the technology beyond flash,which is already being made at close to22 nm.

While Samsung has not indicatedwhen it might ship its 1-Gbit PRAM, itshared technical details of its technolo-gy in an ISSCC paper.

The Samsung PRAM is implementedin a 58-nm process and equipped with alow-power double-data-rate nonvolatilememory (LPDDR2-N) interface. It com-prises a 1-Gbit diode-switch cell arraywith 16 partitions.

Blocks include an embedded con-troller, command address input, datachannel, row address buffer, decoders,PRAM core, program buffer with 1kbyte of SRAM, row data buffer (256-bit-sized row, or 32 bytes) and data com-parison write with an inversion flag(DCWI) scheme.

“The PRAM has significantly low pro-gramming bandwidth compared withthe DRAM write, [which] has a SRAM-based 1-KB program buffer with 800-Mb/s write throughput,” according tothe paper. “If the proposed DCWIenables, the program and overwritebandwidths are measured by 6.4 MB/sand 2.3 MB/s, respectively.” p


Oh-Hyun Kwon, president of SamsungElectronics’ semiconductor business, out-lined four challenges for next-generationIC design at the International Solid-StateCircuits Conference: wrestling power con-sumption into submission, encouragingOEM uptake of next-gen transistor andmemory structures, taking chip packag-ing 3-D, and making circuits less vulnera-ble to instability at low voltages.

Needless to say, ICs are power hun-gry. When the industry moved from 180-nanometer to 90-nm chip designs, chipmakers were able to cut dynamic powerby about 30 percent per node, Kwonsaid. “However, beyond 90 nm, we experi-enced well-known short-channel effects,which make it hard to lower the operat-ing voltage,” he said. The industry alsocontinues to grapple with gate leakage.

Leading-edge chip makers have

moved or are moving to high-k/metal-gate for the gate stack, a shift that canreduce dynamic power consumption by20 percent, Kwon said. But that’s notenough; the overall goal is to reducepower consumption by a compoundannual rate of 20 percent over the nextdecade, he said.

Other structural changes are requiredfor transistors and memory. Today’s planar transistors could run out of gasbeyond the 20-nm logic node; at 14 nm,the industry will require a new transistorstructure. Candidates include multigate,FinFET, fully depleted silicon-on-insulatorand 3-D devices.

At ISSCC, Kwon called FinFET “astrong candidate” beyond the 20-nmnode. Combined with a high-k/metal-gate scheme, FinFET adoption couldreduce power by up to 10 percent, whileimproving performance by an expected20 percent, he said.

Kwon added that it is still unclearhow far today’s DRAM and flash memorystructures can continue to scale. Sam-sung is developing a range of next-gener-ation replacement technologies, including3-D NAND, magnetoresistive RAM, phase-change RAM and resistive RAM. Thechallenge for memory vendors, Kwonsaid, is to get OEMs to collaborate onnext-gen memory designs in order toencourage wider adoption.

In packaging, 3-D stacking based onthrough-silicon via (TSV) technology alsofaces market hurdles. At ISSCC, Sam-sung did its part for the 3-D cause byannouncing the development of a 1-GbitDRAM with a 512-pin wide I/O interfaceintended for mobile applications such as smartphones and tablet computers.The chip is implemented in a manufac-turing process technology somewherebetween 50 and 59 nm and reportedlywill be offered in a 3-D package basedon TSV technology. Shipments are target-ed for 2013.

“The wide I/O memory interfaceenabled by TSV technology offers consid-erable power reduction [up to a claimed75 percent] by reducing the load capaci-tance of interconnect and I/O circuits,”Kwon said.

Further breakthroughs are needed incircuit design, the Samsung executivesaid. “Commonly used low-power circuit-design techniques include clock gating,clock-tree gating, power gating, multi-threshold/multichannel libraries and volt-age islands; however, circuit structuressensitive to process variation tend to beunstable at lower voltages, limiting theextent of voltage downscaling.”

Embedded SRAM is “particularity sen-sitive to process variation,” Kwon said. Toaddress the problem, “SRAM designershave employed various techniques,[including] the read-assist and write-assist circuit technique, which improvesSRAM cell stability.”

Replacing today’s “six-transistormemory cells with eight-transistor cells is[also] an attractive option,” said Kwon.

— Mark LaPedus

SAMSUNG’S KWON SEES FOUR BIGCHALLENGES FOR NEXT-GEN IC DESIGN

The goal: Cut powerconsumption in thenext decade at a 20%compound annual rate



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NEWS OFTHETIMES


Eye on innovations at ISSCCBy Rick Merritt

SAN FRANCISCO — This year’s International Solid-State CircuitsConference drew nearly 3,000 chip designers, who got to choosefrom among 211 papers in 28 sessions, two days’ worth of tutorialsand a handful of evening sessions exploring hot technology topics.Here are some highlights from the floor, particularly from an Indus-try Demonstration Session that was new to ISSCC this year. Theevent gathered the authors of a baker’s-dozen papers to demo real-life applications of the silicon advances they’d described.

bEye-trackingOLED displayUwe Vogel, a business unitmanager at the FraunhoferInstitute, demonstrated atwo-way OLED display and imagesensor. It presents a 320 x 240-pixel display and tracks a user’seye movements, which act as acursor and mouse, sendingcommands to a host system.

HP adopts AMD’s ZacatemDenis Foley, a senior fellow atAdvanced Micro Devices, describedZacate, the company’s first chip to put X86 and graphics cores on onedie. Hewlett-Packard liked the chipenough to design it into the DM1Zmini-notebook (Foley holds one here).The DM1Z is available now and retails for about $500.

The processor uses two of AMD’snew Bobcat cores, plus a graphics core, and consumes just 18 W max. It fits in a performance space betweenIntel’s Atom and Sandy Bridge processors. Intel described one of itsSandy Bridge CPUs at ISSCC (see P.7).

bProcessor on plasticIMEC researcher Kris Myny showed what’sclaimed to be the first 8-bit processordesigned on a plastic substrate. The chipopens the door to more-sophisticatedorganic logic devices, but it also shows thestill-nascent state of the emerging technology. Myny, tongue in cheek, com-pared his foil device to one of the first silicon processors: the Intel 4004.

His paper was one of four in a session on organic electronics that included discussions of a DRAM and a new process for printing CMOS on foil with both p- and n-type transistors.


bCellular SoC saws off filtersMediaTek described a single-chip receiver for GSM/Edgecellular handsets. The SoC eliminates the need for fourexternal SAW filters, opening the door to simpler cellphone designs. MediaTek is one of many companiesworking to simplify silicon and systems for emergingmarkets in China and around the world.

bWiMax dials homeMediaTek described a 65-nm WiMax Wave 2 home router chip setcapable of providing 70 Mbits/second. The Taiwan-based chip designerdemonstrated the chip set in a router the size of a small smartphonecarrying high-definition signals to an HDTV set. The chips use MIMOantennas and consumes about a watt.

bPower amp in CMOSWoonyun Kim, a staff researcher at SamsungElectro-Mechanics America, designed a quad-band poweramplifier in CMOS for GSM and Edge cellular phones.That’s a first, claimed Kim, who said previous poweramps have used gallium arsenide compounds. His chipsshould be in production in about two months.

bNet chip juggles copper, opticsHalil Cirit, senior mixed-signal design engineer at NetLogicMicrosystems, shows the clean eye his 40-nm, 10-Gbit/secondEthernet chip can deliver over either 10GBase-KR copper or SFP+optical links. The market for 10-Gbit/s Ethernet is taking off amid atransition from optical-only to a mix of optical and copper cables.The low-jitter chip described at ISSCC is already in production.

NEWS OFTHETIMES

SAN FRANCISCO — China gave theworld a look at a microprocessor designthat aims to power a petaflops-poweredsupercomputer in a paper presented atthe International Solid-State CircuitsConference here. At the same session,IBM Corp., which continues to push thelimits of CPU frequency, described a 5.2-GHz mainframe processor.

Separately, Advanced Micro DevicesInc. provided more details on its Bull-dozer core, and Intel Corp. describedtwo server chips.

Weiwu Hu, lead designer of China’sGodson processor family, described theGodson-3B, which is expected to emergethis summer in a high-performance sys-tem from Dawning Information Indus-try Ltd. (Shenzhen). The Dawningsystem will use 3,000 Godson-3Bs todeliver about 300 teraflops, Hu said. A future system aims to crack thepetaflops barrier using the chip.

The eight-core, 65-nanometer proces-sor delivers 128 gigaflops at 1.05 GHzand is in production at STMicroelec-tronics Inc. The next-gen Godson-3Cwill be a 16-core version targeting 512Gflops at 2 GHz in 28-nm technologyand is still two years away, said Hu.

The Godson-3B is based on a 64-bitMIPS core with 200 instructions addedfor X86 compatibility and integratedvector processing units. China previous-ly described the processor in August atthe Hot Chips conference.

The chip and a related operating sys-tem constitute one of 16 projects fund-ed by China’s National Science andTechnology Initiative. Additional proj-ects include next-generation VLSIprocess technology, 4G networking, ahigh-resolution satellite system andChina’s space exploration program.

Separately, IBM said at ISSCC that ithad pushed its z196 CPU to 5.2 GHz,

about 18 percent above its previous, 4.4-GHz z10 chip, while maintaining a ther-mal envelope similar to that of the earlierprocessor. Frequency is key for gettingthe top single-thread performance that amainframe class system requires.

“We think there is still room forfuture improvements, but frequencyincreases won’t go on forever,” said JimWarnock, a senior engineer at IBM.

The multichip modules used in IBM’szSeries servers include six CPUs and twoL4 cache chips and consume a whop-ping 1,800 watts. The processors them-selves have a 260-W power budget butcould get more headroom if new multi-chip module materials can be found.

“We are the last of the high-endprocessors still pushing higher frequen-cy,” asserted Warnock.

To get the speed boost, IBM moved thedesign from a 65-nm to a 45-nm silicon-on-insulator process. It also made exten-sive use of embedded DRAM for memoryand capacitors and added out-of-orderexecution to the chip. All in all, IBMgained a 40 percent total performanceimprovement via the new techniques.

IBM conducted extensive poweranalysis of the design, calculatingdynamic and leakage power with vari-ous workloads. It applied the resultingpower and thermal budgets to workfrom the planning to the physicalimplementation design of the part.

Designers used an extensive set oftools to optimize frequency tuning.They delayed the master clock and localclock pulse-width and timing controls.

Bulldozer rollsAlso at ISSCC, AMD provided addition-al details on its new Bulldozer core, firstdescribed at Hot Chips last summer.

Hugh MacIntyre, an AMD seniorengineer, said the core enables 3.5-GHz


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performance at the same power andthermal envelope as the company’s pri-or core design.

The new core delivers linear per-formance across a range of frequenciesand the 0.8- to 1.3-volt levels requiredfor operation. Bulldozer implements213 million transistors in a 30.9-square-millimeter block with 11 metal gates in a 32-nm SOI process,MacIntyre said.

A separate AMD paper describedBulldozer’s 40-entry instruction out-of-order scheduler and execution unit thatcan issue up to four instructions percycle. Another AMD engineer, MichaelGolden, said the unit helps the coremeet the processor company’s target ofdelivering 90 percent of the perform-ance of past AMD cores with a signifi-cant reduction in area and power.

Intel server CPUs Intel, in another paper, described someof the techniques used to reign in pow-er on its 10-core Westmere-EX server

processor. The 32-nm chip includes twomemory controllers and four IntelQuickPath Interconnect (QPI) CPUinterfaces to handle up to 6.4 gigatrans-fers per second.

Intel shaved half a watt from thechip’s power consumption by using a32-byte-wide ring interconnect to linkthe cores, which it designed using latch-and flop-based sequential circuits, saidShankar Sawant, a senior engineerbased in Intel Bangalore.

Sawant described a handful of powermanagement features, including theuse of multivoltage domains and newlower-power states and substates in thecores. In addition, Intel applied tem-perature compensation and receiveequalization techniques on the QPIinterconnect to enable the 6.4-giga-transfer/s maximum throughout.

Intel also made the first technicaldisclosures of Poulson, the next mem-ber of its Itanium processor family, and the first to use eight cores and a 12-instruction-wide data path.p


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Report: Android platform to hit140 million units in 2011By Peter Clarke

MOBILE DEVICES

MARKET WATCHER IMS Research ispredicting that the installed base ofAndroid portables, including smart-phones and tablets, will hit 140 milliondevices by year’s end.

IMS estimates that the installed base for Android-run devices reached 54 million units by the end of 2010.That means the research firm predicts86 million or more tablets and smart-phones will join the Android foldbefore the close of this year.

The unveiling of Google’s Android3.0 operating system for tablets, knownas Honeycomb, along with enhance-ments to the Android Market Web site,will help with the platform’s continuedgrowth, IMS states in a recent report.

“This provides an exciting opportuni-

ty for pay-TV operators, which have tra-ditionally been tethered to the livingroom, to expand the reach of theirbrands to multiple portable platformswith apps development,” IMS principalanalyst Anna Hunt said in a statement.

“In total, Apple OS and Android OSwere present in nearly 125 million con-nected devices shipped in 2010, and this is only expected to increase,” saidBill Morelli, IMS research director formobile technologies. “Such reach intoconsumers’ hands means more opera-tors will be developing apps that enablesubscribers to purchase and consumecontent on new portable platforms andexplore new convergence applications,such as controlling your on-demand ser-vice on the TV set via the smartphone.” p

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GlobalWATCH

SAN JOSE, CALIF. — At the annualLithoVision event here, Nikon Corp.tipped its lithography road map, disclosing the S621D standalone 193-nm immersion tool as well as a sepa-rate illuminator and a metrologytechnology for extreme-ultravioletlithography.

Nikon sponsors LithoVision, whichruns in conjunction with the SPIEAdvanced Lithography conference here.

The Japanese equipment maker andrival ASML Holding NV are going toe-to-toe in lithography, but with marked-ly different strategies. ASML is pushinghard to bring EUV to the 22-nanometernode. Nikon, for its part, “anticipates adelay in EUV ecosystem readiness” thatcould push its rollout to the 16- or 11-nmnode, said Yuichi Shibasaki, generalmanager of the Next Generation Devel-opment Department at Nikon (Tokyo).

For now, Nikon is pushing for opticalsolutions. The company is shipping itspreviously announced S620D, a 193-nmimmersion tool for the 32-nm node andbeyond that offers a 1.35 numerical aper-ture (NA) and a throughput of 200 wafers

per hour. Customers are said to includeGlobalFoundries, Intel and Samsung.

Intel reportedly is using the S620Dfor development at the 22-nm logicnode. With a different tool, Nikon wasIntel’s sole lithography vendor for criti-cal layers at the 32-nm node, but at 22nm Intel reportedly is using both ASMLand Nikon scanners.

Nikon’s S621D immersion tool,tipped at LithoVision, can be ordered asa standalone system. The S620D is amodular system that can be upgradedto an S621D.

Like the S620D, the S621D boasts anNA of 1.35, but the new scannerimproves the overlay requirements forthe 14-nm logic node.

During a presentation, Nikon’sShibasaki tipped several “tuning andoptimization knobs” within the toolthat are said to boost performance andoverlay. They include an intrashot grid,dynamic lens control, an adaptive reticle chuck and aberration control,he said.

Nikon also expanded its source maskoptimization (SMO) efforts by rolling

out a so-called freeform illuminator.Dubbed iPure, the technology adjuststhe illumination in a scanner on the fly,said Hamid Zarringhalam, executive vicepresident of Nikon Precision Inc.

Extreme UV movesIn EUV, meanwhile, Nikon rival ASMLhas shipped two alpha tools—one toAlbany Nanotech and the other toIMEC—and recently shipped its firststandalone preproduction EUV tool toSamsung Electronics.

Nikon is not shipping standaloneEUV tools but has brought up R&Dtools at its headquarters in Japan and atJapanese R&D organization Selete.

Nikon’s EUV1 tool has been in devel-opment for some time. The companynow predicts the insertion of EUV forthe 11-nm “half pitch” node in 2015.

At LithoVision, Nikon and Canonjointly revealed development of anactinic wavefront metrology technolo-gy for EUV. The Multi-Incoherent-Source Talbot Interferometer (Misti)technology is still in the R&D stage, thecompanies said. p

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ITRS chairman calls quantumtunnel FET a transistor optionBy Peter Clarke

GRENOBLE, FRANCE — Paolo Gargi-ni, an Intel fellow and chairman of theInternational Technology Roadmap forSemiconductors (ITRS), used a talk hereat the Industry Strategy Symposium-Europe to discuss the prospect of com-bining a field-effect transistor withquantum tunneling to reduce powerconsumption while maintaining ade-quate performance.

Increasing mobility through the useof nonsilicon materials in the transistorchannel remains a favored theme forGargini. But in his talk at the SEMI-sponsored symposium, he appeared topush back the prospect of deploymentuntil about 2020.

Gargini discussed compound semi-conductor-on-silicon technology, as hehas done before. He also predicted thearrival of multigate high-k/metal-gateIII-V devices on silicon substrates by2020. And he discussed the need to opti-mize for power consumption ratherthan performance.

Previously, the challenge was per-ceived to be how to design for maxi-mum on-current while tolerating orreducing the leakage current, Garginisaid. Now—perhaps driven by the newawareness of power efficiency atIntel—Gargini believes the goal is tominimize the leakage current and, inparticular, the subthreshold impact ondevice performance.

Indeed, he raised the prospect ofbandgap engineering to produce tun-neling FETs based on germanium in thechannel as an intermediate or alterna-tive step to introducing indiumarsenide (InSb).

But Gargini also appeared to push outproduction to close to 2020. At the same

event a year ago, he had said that com-pound semiconductors in silicon couldbe an option by 2015.

When questioned about the apparentinconsistency he said, “We put thesethings on the shelf; it is up to others todecide when to use them. They may beheld for two, three or four years.”

Gargini recalled, for example, howhigh-/metal-gate technology was readyat Intel in 2005, but volume productionwas delayed a couple of years.

The overriding message was thatwhile the period of 1970-2000 had beenan era of geometric scaling and “easyriding,” the coming decades would befar tougher, requiring complex materi-als engineering.

Gargini pointed out that as silicontransistors have shrunk from 90 nm to 32nm, the germanium doping in the chan-nel has gone from 17 percent to 40 per-cent. It is not difficult to imaginegermanium-channel transistors with thehigh mobility that such structures imply.

Gargini made it clear during his pres-entation that he’s bullish on theprospects for the tunneling FET. Thevisuals included pictures of Garginitalking with Leo Esaki, a winner of theNobel prize for physics in 1973 for workon quantum tunneling. Gargini also ref-erenced a paper by Chenming Hu et al.titled “Prospects of a tunneling greentransistor for 0.1-V CMOS,” presented atlast year’s International ElectronDevices Meeting.

When asked about the prospects forgraphene in the channel, another hotresearch topic, he said, “It’s perfectacross 100 microns but very imperfecton a 12-inch wafer . . . It’s going to take15 years to get it right.” p

MATERIALS


Thunderbolt interface rattlesplacid PC landscapeBy Rick Merritt

IT’S RARE THAT A BRAND-NEW technology strikes thematuring computer industry. But that’s what happened a fewweeks ago when Apple Inc. announced a family of MacBookPro notebooks that contain something from Intel calledThunderbolt.

The Apple press release marked the first public use of thename, which hadn’t even appeared in the blogs that had beenchurning with rumors of an electrical version of the opticalLight Peak technology. Intel had been demonstrating a LightPeak prototype since September 2009, but the conceptremained little more than a curiosity. Then Thunderboltemerged full blown in the Apple systems late last month andsuddenly became a flashpoint.

Intel followed Apple’s Feb. 24 announcement by hosting aconference call later the same day to introduce Thunderbolt.The event was so oversubscribed with callers from aroundthe globe that no one could hear the presenter speaking froma San Francisco conference room.

It took a full day—eons in the Internet era—for the full sto-ry to emerge. It was another day or so before word leaked outabout the misgivings of a silent majority of big PC, displayand hard drive makers not listed among the early adopters ofThunderbolt (see story, page 22).

Now that the blinding flash is over, the details are emerg-ing in the sober light of day.

Inside ThunderboltThe Thunderbolt interconnect supports two 10-Gbit/secondbidirectional channels on a common transport for 40-Gbit/smaximum aggregate throughput.

An Intel Thunderbolt controller enables a common trans-port layer on which both 4x PCI Express Gen 2 and Display-Port traffic can ride. The underlying transport has its ownprotocol encapsulation method as well as unique synch-ronization and traffic prioritization mechanisms for its

10-Gbit serial lanes.Thunderbolt presents to the operative system what looks

like native DisplayPort and PCI Express traffic, so no newsoftware is needed.

Intel defines several applications for the interface. Accord-ing to the company, Thunderbolt can be used to create flexi-ble system designs. For instance, thin notebooks or clientscould use it to link to high-end drives, displays and otherexternal devices instead of building them all into one box.Essentially, it provides a PCI Express link outside the box.

The interface will be used to send big files quickly amongPCs, cameras and drives, Intel says. It will also be used as astraight DisplayPort link to displays.

Intel has produced two Thunderbolt controllers. One sup-ports a single cable with two bidirectional 10-Gbit/s Thunder-bolt links and consumes about 1 W max. The other supportstwo cables, presumably for less power-sensitive systemssuch as desktops.

Intel is the sole supplier of the controllers and is not com-menting on their price, except to say the chips are “competi-tive with” 10-Gbit/s Ethernet controllers in cost per gigabit.

Intel wouldn’t say whether it alone owns the intellectualproperty for Thunderbolt or whether other companies suchas Apple own any piece of the IP. It did say the technology isavailable royalty free and that it will make case-by-case deci-sions whether to license the interface for use in systems-on-chip. So far, no one has such a license.

Thunderbolt requires new kinds of active cables. For now,Apple is providing the active copper cable for Thunder-bolt; the five-wire assembly uses one wire each for the four 10-Gbit/s links (two in and two out) and the fifth for manage-ment traffic.

An active optical cable is in development to supportlengths of tens of meters. It will be available later this year.

The connector itself is a slightly modified version of the

COVER STORY


bIntel showed a nonworking mechanicalprototype of a LaCie portable flashdrive using two Thunderbolt links andtwo solid-state drives.

bIntel is producing a 1-WThunderbolt controller for asingle-cable as well as adual-cable version.

bThe Thunderbolt connector is a modified mini DisplayPorttype that plugs into existingDisplayPort ports and can carryPCI Express.

bIntel demonstratedThunderbolt on a newMacBook Pro notebooklinked to a storagearray from PromiseTechnology.


COVER STORY

mini DisplayPort connector and plugs into existing Display-Port devices. It can automatically detect DisplayPort and PCIExpress traffic. Intel would not identify any third-party con-nector and cable makers it might be working with for Thun-derbolt support.

Thus far, the chip giant is sharing full technical specs ofThunderbolt only under nondisclosure with partners makingThunderbolt products. It plans to release a developer’s kitbefore July that will include the technical specs, but it doesnot plan to publish details of the spec online.

The road map, too, is unclear. Intel could increase the num-ber of 10-Gbit/s lanes or increase the lane speed in the future,but it is not saying what it plans or when.

New ecosystemThe new interconnect could leapfrog work on USB 3.0, whichaims to deliver about 5 Gbits/s max and has no capabilitiesfor flexibly supporting multiple protocols.

USB is assured a long life based on its broad adoptionacross computer and consumer peripherals. If Thunderbolt is successful, however, it could eclipse USB as the new high-end interconnect—as many market watchers once

Intel Corp.’s new high-speed I/O technolo-gy, Thunderbolt, is leaving some peoplefeeling burned. Rather than drive a newinterface into the market, they say, thechip giant should give its full attention toan existing, successful one: USB.

Thunderbolt’s critics say the interfacebrings new costs and complexity to delivertwo bidirectional 10-Gbit/second copperlinks that won’t open up any major newapplications. USB 3.0 is already availableat data rates up to 5 Gbits/s over copperand, like Thunderbolt, can also ride opticallinks in the future.

Simply put, Thunderbolt “is a mistake,”said one big Intel customer.

Their arguments—not generally beingaired in the public—are why some of thebiggest PC, display and hard drive vendorshave yet to throw their support behindThunderbolt.

The technology will clearly carry aprice premium, although Intel won’t sayhow much. The cost of the controller, cur-rently made only by Intel, will be roughlyin line with that of today’s 10-Gbit/s Eth-ernet chips. That represents a premiumover the cost of a USB 3.0 chip.

Further, Thunderbolt requires a unique,

five-wire active cable, thus far supplied onlyby Apple, and modified mini DisplayPortconnectors from an unidentified source.Other costs are hidden in the complexitiesof mastering a new technology, potentiallywith new supply chain partners.

Apple is the only system maker tohave adopted Thunderbolt thus far. Apple,of course, has a business model based on selling generally upscale products, typi-cally with higher-than-average PC profitmargins. Most PC and display makerscompete primarily on cost in higher-vol-ume markets with thinner profits.

Companies not yet publicly backingThunderbolt say there are no compellingapplications that need more than the 5-Gbit/s links USB 3.0 can offer. Intelmanagers say Thunderbolt is unique insupporting display resolutions greaterthan high definition, but that’s a very limited niche.

Thunderbolt will let OEMs have oneport that can support either a display or ahigh-speed data link, potentially simplify-ing designs, said Intel. But opponents saidsystems will still need to support existinginterfaces, such as USB, and making roomfor one more connector on space-con-

strained systems such as ultrathin laptopswill be difficult.

Intel argues Thunderbolt will let OEMsbuild systems that put previously internalresources, such as fast disk drives orgraphics, outside the box. Opponentscounter that such designs are already pos-sible with a cabled PCI Express spec—andthat no one, thus far, has found thosecompelling.

In the end, Thunderbolt’s detractorswant the industry to put the full weight ofits collective effort behind USB—a rela-tively low-cost, well-understood technologythat’s already shipping billions of portsacross computers, peripherals and con-sumer devices.

The USB 3.0 version, much like Thun-derbolt, was architected in a way that sup-ports its extension to optical links andhigher speeds. Intel has not backed USBstrongly enough and has delayed plans tosupport the interface in its PC chip sets,Thunderbolt’s critics say.

Thunderbolt will no doubt get morebacking from top-tier PC, display and diskdrive makers. But it remains to be seenwhether it will provide sustained impact or,like FireWire, flame out. — Rick Merritt

THUNDERBOLT’S CRITICS WANT INTEL UNDER USB’S UMBRELLA

Thunderbolt detractors warn of the difficulty of making roomfor one more connector onspace-constrained systems

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COVER STORY

expected FireWire would do. For that scenario to play out, Thunderbolt would have to

establish a broad ecosystem of chips and supporting systemsand peripherals. Intel said companies planning to supportThunderbolt include Aja, Apogee, Avid, Blackmagic, LaCie,Promise and Western Digital. Intel aims to enable the inter-face for use on other computers, displays, storage devices,audio/video devices, cameras, docking stations and more.

The company demonstrated Thunderbolt sending videofiles at rates up to 800 Mbytes/second between one of the newMacBook Pro notebooks and a prototype storage array fromPromise Technology. Intel also showed a nonworkingmechanical prototype of a LaCie device supporting Thunder-bolt; the portable flash storage array had two Thunderboltports and two solid-state drives.

Apple does not have exclusive rights to Thunderbolt for aset period. But it remains unclear which other OEMs will support the interconnect or when they might sign on.

“There is significant interest with other PC OEMs, but it’snot across the board,” said Jason Ziller, who manages theThunderbolt program for Intel.

“We have talked to CE manufacturers, and there is someinterest in having [Thunderbolt for its support of] high-

def display and data carried on the same cable,” he added.Intel owns the Thunderbolt trademark and will set up

an interoperability verification program for using it. The program will be offered at no charge, Ziller said.

For its part, Apple has a mixed history of embracing newsystem interconnects. It was among the first to championFireWire, which for a time appeared to be a shoo-in as thehigh-end computer and consumer interface of choice. ButUSB quickly eclipsed FireWire, which never gained tractionbeyond a niche of professional A/V systems and high-enddisk drives. On the other hand, Apple was also among the early adopters of Wi-Fi, now standard across all notebooks.

How Thunderbolt might avoid FireWire’s fate is perhapsthe biggest unanswered question. FireWire initially hadbroad backing from chip and systems companies and was farahead of USB in throughput and latency. Apple took the leadin building FireWire into its systems, courting its users inpublishing and media creation.

But FireWire’s proponents rolled out a somewhat long andconfusing road map, leaving some to question whether theywanted to support the interface from its first iteration or waitfor a future generation. A battle over intellectual propertyrights further chilled the market. Meanwhile, USB madesteady progress getting design wins for its royalty-free tech-nology and regularly updating its speeds, closing the gapwith FireWire.

Indeed, USB 3.0 was poised to leapfrog FireWire whenThunderbolt struck.

Thunderbolt had its genesis as Light Peak, first announcedby Intel as a tech demo in September 2009 as an optical inter-connect positioned as a successor to USB 3.0. Last September,Intel said it had accelerated its work and would deliver a con-troller chip by the end of 2010.

Then Intel went quiet about its plans. Reports emerged ithad revised its work to focus on a copper-based implementa-tion. The adoption move by Apple, which apparently soughtan exclusive deal to be the first OEM to use the I/O, likelyrequired Intel to keep its plans quiet.

Despite bloggers’ best attempts to break the silence, thesecret remained fairly well kept, until the Apple announce-ment shook things up. p

Thunderbolt technology carries two protocols—DisplayPort and PCI Express—to connect displays anddata devices, respectively.

Intel demos Thunderbolt for EE Times: http://tiny.cc/6ivdp

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Intelligence

RESEARCHERS FROM the University of Michigan unveiledwhat they called the first all-in-one, millimeter-sized proces-sor at the recent International Solid-State Circuits Conferencein San Francisco.

Designed for implantation in the eyes of glaucomapatients, the chip would also be useful in wireless sensor net-works, remote surveillance and other applications requiringon-chip trackable smarts, according to researchers.

“Ours is the first true millimeter-scale complete computingsystem,” University of Michigan College of Engineering pro-fessor Dennis Sylvester said at ISSCC. Sylvester worked withfellow professors David Blaauw and David Wentzloff to devel-op the processor.

“Millimeter-scale systems have a host of new applica-tions for monitoring our bodies, our environment and our buildings,” said Blaauw. “When you get smaller thanhandheld devices, you turn to these monitoring devices.There could be tens to hundreds of them per person, and it’sthis per capita increase that fuels the semiconductor indus-try’s growth.”

In its first application, the millimeter-scale computer willmeasure the pressure inside the eyes of glaucoma patients tomonitor the progress of that disease. Packaged in a volume ofless than a cubic millimeter, the system contains a micro-processor, pressure sensor, memory, thin-film battery, solarcell for recharging, and wireless radio and antenna for trans-mitting stored measurements.

The current prototype, the third generation of what theresearchers call their Phoenix effort, supposedly consumes 10 times less active power and 30,000 times less standby pow-er than conventional processors. The latest iteration of thePhoenix consumes an average of just 5.3 nanowatts of powerand wakes up every 15 minutes to take a measurement andtransmit the results.

The processor requires 1.5 hours of sunlight or 10 hours ofindoor lighting to recharge its battery.p

Millimeter-scale computertargets environmental,medical monitoring By R. Colin Johnson

WIRELESS PROCESSING

All-in-onecomputerdeveloped atUniversity ofMichigan isclaimed to bethe firstcompletemillimeter-scalecomputingsystem.Photo: Greg Chen

THE EUROPEAN UNION’S Dotfive project has produced asilicon-germanium (SiGe) chip that it says achieves the high-est-frequency operation thus far for the semiconductor tech-nology. The purpose of the 820-GHz (0.82-THz) transmitterand receiver chip pair is to enable X-ray-like visibility intocontainers, but at harmless millimeter wavelengths.

Today’s terahertz imaging, radar and communicationsapplications require expensive exotic devices, but the EU’sDotfive project aims to lower the cost of terahertz devices bycasting them in high-frequency SiGe. The three-year old proj-ect is focused on producing millimeter-wavelength SiGe het-

erojunction bipolar transistors that will be manufacturedcommercially by STMicroelectronics NV and Infineon Tech-nologies AG.

At the International Solid-State Circuits Conference, IHPGmbH and the University of Wuppertal (North Rhine-West-phalia, Germany) presented the latest results of the Dotfiveproject.

The team described its two-chip set (transmitter and receiv-er), which includes all the frequency multipliers, harmonicmixers, power amplifiers, on-chip antennas and other circuitsrequired to create 820-GHz frequencies from an 18-GHz

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Consortium claims SiGe frequency recordBy R. Colin Johnson

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SENSORS


INTELLIGENCE

THE COLLEGE OF NANOSCALE Science and Engineering (CNSE) at the Universi-ty of Albany is spearheading a pair of national nanosensing-technology initiativesto support critical applications in the military and energy sectors.

The U.S. Space and Naval Warfare Systems Command has awarded the college’sSmart System Technology & Commercialization Center of Excellence (STC) a $3 mil-lion contract to develop, fabricate and test a variety of smart sensor technologiesintended to enhance military intelligence gathering by soldiers in the field.

STC is also leveraging earlier work with the Electric Power Research Instituteinto a $3 million initia-tive through the U.S.Department of Energyto develop full systemsof wireless sensors formonitoring potentiallydamaging vibration ofcomponents on high-speed power generat-ing equipment.

The systems devel-oped for the DOE willfeature a combinationof integrated circuitswith active sensingtechnologies.

Prototypes areexpected this summer for the first-of-its-kind sensor system. The system initiallywill monitor blades in steam turbines, but eventually it is expected to be used withblades in wind turbines, helicopters, jet engines and turbines that power ships andsubmarines, among other applications.

“These new partnerships highlight STC’s expanded focus on developing smartsensor technologies and solutions to address areas of critical national need, includ-ing the military and energy sectors,” CNSE senior vice president and chief execu-tive officer Alain Kaloyeros said in a statement.p

reference. The researchers demonstrat-ed the chips in a terahertz imagingapplication that could “see” inside aUSB memory stick.

Leading corporate participants inthe Dotfive project include STMicro-electronics ( Geneva), Infineon Tech-nologies (Munich, Germany), XmodTechnologies (Talence, France) andGWT-TUD GmbH (Dresden, Germany).Research institutes involved in the

project include IMEC (Leuven, Bel-gium) and IHP (Frankfurt, Germany).

Academic partners include JohannesKepler University (Linz, Austria);France’s Bordeaux National School ofElectronics, IT and Radiocommunica-tions; Paris-Sud University; the Techni-cal University of Dresden; BundeswehrUniversity of Munich; Germany’s Uni-versity of Siegen; and the University ofNaples (Italy).p

Nanosensor development projectstarget military, energy appsBy Nicolas Mokhoff

A miniaturized infrared diffraction grating,fabricated by CNSE’s Smart SystemTechnology & Commercialization Center ofExcellence for a private industry partner,provides a low-cost alternative to existingIR imaging systems deployed amongemergency first responders.

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THE NUMBER OF CORES in a systemisn’t the be-all and end-all when itcomes to power; when developersswitch from a single-core to a multicoredevice, they can still run into limits inperformance. These caps aren’t justabout processor speed. They could alsobe due to the constraints of the overallsystem configuration.

So instead of focusing on cores alone,developers should turn their attentionto system architecture and the perform-

ance of key interfaces when gauging thequality of a new platform. That willenable them to measure the function ofkey interfaces and correlate those tosoftware operations to reach whatshould be their end goal: unlocking thefull potential of a multicore device.

In the past, with single-core devices,processor speed was the key determi-nant of performance. Now—with theaddition of four, six or more processingelements—measuring system perform-ance can be trickier.

Links in the chainYou’ll notice we’ve changed our termi-nology from cores to processing ele-ments. That’s because multicore devicestypically do not consist of just cores.They also include hardware acceleratorsand intelligent peripherals. Those pro-cessing elements are all part of the pro-cessing chain, so they must beconsidered in order to assess and tunesystem performance accurately.

Processor performance continues toincrease exponentially, as integratingmultiple cores, accelerators and evensubsystems into a single device hasbecome routine. This is an extension ofthe current trend to integrate card-levelfunctions into a single device.

Because interoperability betweendevices relies on standards, however,the pace of change for card-level I/O hasbeen much slower. At the same time,the number of interfaces on devices hasincreased while physical package sizesremain constrained, forcing interfacesto become both fast and narrow.

As a result, as is illustrated in

Stephen Lau is in emulation technology product management at TexasInstruments. He is responsible for the definition of on-chip debug technologyand associated emulator products deployed through TI’s Third-Party EmulationDeveloper Community.

DESIGN PRODUCTS+

Beyond cores: Unlockingmulticore’s full potentialBy Stephen Lau

GLOBAL FEATURE

Elements likehardware accelerators

and intelligentperipherals are part

of the processingchain and must be

considered whenassessing and tuningsystem performance


Figure 1, real I/O perform-ance is leveling off.

Where to focusFocusing on the systemlevel requires a thoroughunderstanding of the dataflow. Figure 2 shows ablock diagram of a typicalmulticore device, with aconcentration on theshared aspects of thedevice.

The processing ele-ments consist of cores andcoprocessors that shareI/O, external memoryinterface and internalmemory, and are connect-ed by on-chip buses. Typi-cally, the external memory interface isthe most heavily used. One potentialsolution is to increase internal memory,

but this is expensive compared withleveraging commodity external memo-ry. On-chip buses are normally designed

with the appropriate per-formance level.

From a software perspec-tive, maximum efficiency is obtained when all process-ing elements are utilized. Modern processing elementsachieve maximum perform-ance with repetitive opera-tions on blocks ofdata—analogous to singleinstruction, multiple data(SIMD)—in a core. Thoseoperations are data intensive,however.

The more parallel an algo-rithm becomes, the greaterthe data demands on the sys-

tem. Therefore, having theability to monitor perform-

ance on the memory interface thatfeeds the processing element is crucial.It is also valuable to measure perform-

DESIGN PRODUCTS+

Figure 1. CPU performance vs. I/O performance.

Figure 2. Monitoring performance on shared interfaces on a TI KeyStone multicore device.


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ance at all key processing element inter-faces to gain an overall view of systemperformance.

Maximizing performanceUnderstanding data flow enables devel-opers to focus their efforts on the appro-priate interface to boost systemperformance.

In Figure 2, the external memoryinterface is of key interest. In manydevices, counters in the memory inter-face provide throughput information.This may not be sufficiently fine-grained if the memory interface isshared among processing elements.

Users need the ability to narrow per-formance measurements to the process-ing element of interest. Correlatingsystem-level performance to programoperation helps developers make deci-

sions on system performance in theproper context.

Multicore devices deployed in real-time applications must maintain real-time performance while achieving highpower efficiency and improved costs.Real-time systems have deadlines, soperformance information, such as accu-mulated wait time, helps developersunderstand why a processing element isnot performing as expected when work-ing with a specific interface.

For example, if the accumulatedwait time for a processing element toaccess a RapidIO serial interface islonger than expected, it may be theresult of other processing elementsmonopolizing the interface. Informa-tion such as average access width isalso valuable, as it helps developersunderstand whether the performance

level is due to the type of accessesbeing made or is the result of someother issue.

Designing a debug architecture tosolve key challenges of performanceanalysis on important interfaces and toprovide visibility into multicore is oftenoverlooked during device selection, butit can have a major effect on productschedule and performance.

Industry standards, such as the IEEE1149.7 debug standard and the MIPIAlliance’s System Trace Protocol (STP)specification, have helped make systemvisibility and debug capability easilyrecognizable and more straightforwardfor software developers to request.

Users must also consider the cost ofutilizing advanced debug capabilities.For example, you can collect systemtrace information through an on-chip


DESIGN PRODUCTS+

Figure 3. Visualization of system trace information showing measurement of transactions on a key interface in a TI KeyStone multicore device.

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buffer or a low-expenditure debug andtest controller.

System tracing using the STP stan-dard provides software developers with a hardware-accelerated multicore“printf” capability, through which messages from each processing ele-ment are identified and are globallytime-stamped by hardware. Softwaredevelopers receive a global time-corre-lated view of software execution acrossprocessing elements.

The capability also provides multiplechannels that aid in filtering messages.

For instance, developers can leveragedifferent channels for each type of soft-ware function: Low-level device driverswould be on channel 1, operating sys-tem messages on channel 10 and appli-cation threads on channel 100. In thisinstance, a developer working on ahardware problem could view devicedriver messages by filtering for channel1 on cores 1 and 2. That would result inthe system showing just the device driv-er messages from those cores. The devel-oper could also correlate these to theperformance on a system interface.

In Figure 3 (page 34), transactionsmade to an accelerator are measured bythe CTools 4 Bus watchpoint and trafficmonitors. The transactions are shownin context with the software threads.

The software threads, which includemessages from two processing ele-ments, provide developers with theability to quickly find and eliminate

inefficiencies at the device level.When working with multicore infor-

mation, visualization can be a chal-lenge, as trends quickly identifiedgraphically may not be so obvious in a textual display.

Figure 4 highlights performanceanalysis on a memory interface fromthe perspective of a processing elementin the device. It also shows throughput(red) and the average access width(green) on the interface. Developers can use such information to fine-tunetheir systems in order to improve performance.

Although the potential is there formulticore processors to increase pro-cessing performance significantly,developers must change their focusfrom the core to the system.

The ability to obtain a time-correlat-ed view of system performance and soft-ware activity is necessary for developerswishing to unlock the full potential oftheir multicore devices.p


DESIGN PRODUCTS+

Figure 4. Performance analysis on memory interface showing throughput (red) and average access width(green).

When working withmulticore information,visualization can be achallenge, as trendsquickly identifiedgraphically may notbe so obvious in atextual display

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IN A QUEST TO BRING innovativeand differentiated products to marketfaster, the electronics industry willincreasingly adopt multicore processingto reap the benefits of higher perform-ance, longer battery life and increasedflexibility, as well as lower power con-sumption and lower cost. Vendors canonly realize those advantages, however,when they architect software specifical-ly for multicore devices.

Model-driven development methodswill help software design teams per-form multicore design trade-off studies,visualize and refactor code for greaterreuse, and automatically generate codefor hardware configuration and com-munication protocols.

With software a critical factor in deliv-ering on the promise of multicore, let’stake a look at the landscape of multi-core computing and examine severalcutting-edge software developmentmethods.

The promise of multicore The tide has turned in the drive toincrease performance and reduce powerconsumption in the computing plat-forms used for building today’sadvanced electronic products. From PCsand workstations to smartphones andother portable devices, consumerdemand for ever-improving perform-ance, battery life and advanced featureshas led device manufacturers to buildand deliver products that use multicoretechnologies. The next generation ofsmarter products will rely on multi-core processors to deliver even greaterusability and productivity to an increas-

ingly technology-savvy clientele. Traditional processors deliver better

performance by cramming more tran-sistors on a die and increasing the clockrate in a never-ending challenge toMoore’s Law. While that trend willcontinue, true leaps in performanceand power management lie in innova-tion around multicore technologies.

Multicore-based systems typicallyoperate at slower clock speeds, whichcan significantly improve battery lifeand reduce heat production. The cool-er operating temperatures allow forquiet (fanless) cooling systems andproducts with smaller form factors.thanks to a reduction in the numberof distinct processors.

Further, multicore operating environ-ments support true multitasking andbetter application performance thansingle-core environments. And multi-core makes true parallelism possiblewhen handling increasing loads of com-pute-intensive applications.

Environmental challengesFor system designers, decisions aboutthe actual number of necessary proces-sors and cores, operating system charac-teristics (symmetric or asymmetric) and required middleware are difficult.They must take into account new issues regarding application partition-ing and both intercore and intertaskcommunication, as well as the scalabili-ty of a multicore design. Features of theoperating system(s) and potential mid-dleware increase the complexity of theoverall software design as well.

Simply put, organizations moving to


DESIGN PRODUCTS+

Model-driven development methodsfor multicore-based softwareBy Ravi Patil

GLOBAL FEATURE

multicore will require changes in theskill set of their software design teams.

For parallelism to become the norm,application design must map to theadvantages of the parallel architectureavailable in a multicore operating envi-ronment. Considerations regardingincreased use of multiple tasks, inter-task communication mechanisms andtask-to-core allocation all become criti-cal in successful application develop-ment. Also, reuse increases inimportance for tasks and componentsof these software-intensive systems.

Debug and test are critical whendeploying software for a multicore sys-tem. Traditional code-level debug andlate-cycle testing techniques often donot scale to multicore environments. Sonew techniques and test environmentsare needed to ensure that software isoperating correctly and providing therequired level of functionality.

Three methodsExperience has taught us three usefulmethods for effective multicore devel-opment.

• Perform trade-off studies to assessalternatives. Moving an existing sys-tem to a multicore processor can causeit to run at the same speed or evenslower. This is because the actual coresare typically slower on an individualbasis than on the original processor. As a result, the whole application mayrun at the speed of a single corebecause shared data can slow downcommunication. Implementing trade-off studies is therefore critical inassessing alternatives to ensure desiredimprovements in performance, speedand resource utilization.

Modeling your product’s softwarearchitecture and creating options for itto run on multiple cores make trade-offs easier to diagnose. By mappingexisting tasks to cores and adding moretasks as needed, you can learn how tooptimize communications between thetasks involved in your applications.

An important related assessmentmethod is to simulate the model you

Ravi Patil is industry marketing manager for IBM Rational Software. He has anMSME from MIT and an MBA from the University of Michigan.

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• Use existing software to acceleratedevelopment. If your application runswell in the existing single-core operat-ing environment, it may function prop-erly in the new multicore environment.So you’ll want to retain its value byreusing as much code as you can whileworking to ensure that it will performcorrectly and scale to meet the demandsof the new environment.

Development for multicore—anchored by a model-driven approach—should present significant softwarereuse opportunities. From the simplevisualization of the structure and rela-tionships of the software and its compo-nent parts, to refactoring the code fordeployment within a multicore environ-ment and on to integration and exten-sion into completely new designarchitectures, the right model-driventooling can accelerate your ability toreuse your code.

Existing software components can beused in new designs built for multicore-based products. Again, visualization,refactoring and automated generationcapabilities in a strong model-drivendevelopment tool greatly enhance yourability to make these reuse decisions.

New applications can be written anddelivered for products, and the model-driven approach limits the need todesign from scratch. The successfultrack record of the reused componentsmeans their behavioral aspects areunderstood and tested, thereby allow-ing the test-and-debug efforts to focuson performance.

• Automate software generation toimprove quality. Because multicoretechnology inherently provides a high-ly parallel environment, communi-cation between tasks within an applica-tion becomes critical. Tasks must usedifferent mechanisms as they commu-nicate between one core and another,further necessitating good interfaces

between tasks. Implementing a modeling environ-

ment to enable the automatic genera-tion of supporting communicationmechanisms helps you better under-stand, specify and explore alternativesinvolved in task switching. Modelingalso helps you analyze different hard-ware and communication protocols,and model-driven tools further speedthe process with automatic code genera-tion. This allows for the visualization ofthe design and its systematic replica-tion in the generated code.

When moving a task from one coreto another, you can—as needed—regen-erate and reflect the modeled change incode that is specific to the new core,even if it uses a different operating sys-tem or has to use a different protocol tocommunicate to tasks on the originalcore. Typically, this requires hand cod-ing, but a modeled application providessimple assignment of the options, withthe automatic generation taking care ofthe rest of conversion.p


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IT IS DIFFICULT TO IMAGINE a worldwithout the smartphones, tablets, e-readers and game consoles that are per-vasive in our lives today. Behind suchinnovations are embedded systems. Toprovide the automation and the speed tobuild them, EDA companies are takingadvantage of the parallelism offered bymultiple cores. All claim some multi-threading and multicore capabilitiesand are porting more code to multi-threaded applications.

This is certainly no easy task. EDAcode is complicated, and EDA develop-ers must work within Amdahl’s Law,which states that the gains you get fromparallelizing code are sharply limited byany section that cannot be parallelized.Thus, if 90 percent of the code is paral-lelized and 10 percent is not, the maxi-mum gain expected is 10x.

Since all EDA flows include somenonparallelizable code, it is unreason-able to expect a 4x gain on four CPUs.Hence the need for holistic parallel pro-cessing in EDA design flows. Thus far,the work has focused on tackling“embarrassingly” parallel applicationsand using coarse-grained partitioning.But EDA applications and the EDAworkflow as a whole will not achievethe necessary scaling by focusing onlyon problems that are easy to parallelize.

Digital IC implementation aloneinvolves many design flow steps fromnetlist to tapeout. In order for the usersof EDA tools and specifically digital ICimplementation tools to gain the benefitof multicore chips and multiprocessormachines, every step in the flow willneed to support parallel computation.

The need for holistic parallel process-ing extends to each major segment ofthe EDA industry, but digital IC imple-mentation software is a good represen-tative example. A coarse-grainedpartitioning of the problem will notsuffice, as coarse-grained approachesmust include a serial step in which thework is partitioned and another inwhich the partitioned elements arereassembled. For large digital designapplications, such partitioning is a bot-tleneck. Nearly every step of the work-flow needs to be run in parallel—and toachieve that, the fine-grained parallelproblems that are most difficult to par-allelize are the ones that most urgentlyrequire innovation.

For multicore architectures with fourto eight cores, creative techniques canbe applied to get legacy code to run inparallel without the need for excessiverecoding. Cadence Design Systems hasexploited some techniques that usefine-grained distributed processing tospeed compute-intensive pieces of serialprograms. Most of the code for theCadence netlist-to-GDSII flow has beenparallelized within the context ofAmdahl’s Law.

For example, floor planning for com-plex giga-gate/GHz designs can requiremany months of designer time. Byusing a combination of coarse-grainedand fine-grained processing capabilitiesin the Cadence digital flow, designersnot only can abstract giga-gate/GHzdesigns overnight but also can createmultiple floor plans in parallel.

Similarly, in the routing, extractionand physical verification engine, where a

lot of code leverages fine-grained dis-tributed processing and has been writ-ten with parallel processing in mind, aspeedup of 3x over four CPUS and 6xover eight CPUs has been observed.

This is the kind of scalability thatmultithreaded architectures can pro-vide, and it is imperative that EDA com-panies take full advantage of it.

What has yet to be seen, is how EDAwill reshape itself to support manycoredesigns (32 cores or more). A lot of fine-grained problems are not going to scalewith manycore; many legacy applica-tions will have to be retrofitted, andothers will have to be rewritten.

Such rearchitecting will result in anew paradigm for EDA companies. Wewill see a focus not only on modifyingtools and algorithms for manycoreprocessors and GPUs but also for distri-bution across server farms and comput-ing clouds. Clusters and clouds builtout of manycore processors will provideopportunities for unparalleled computeresources.

EDA on the cloud is an excitingprospect. Cadence is using the software-as-a-service (SaaS) model to providehosted design solutions, and it offersEDA software and intellectual propertyevaluation through the Xuropa cloud.At last year’s Design Automation Con-ference, Bernie Meyerson, vice presi-dent of innovation at IBM, suggestedcloud computing would become thedominant standard for EDA companies.

Certainly, cloud computing for EDAcomes with its own challenges, includ-ing security, resource management andlicensing issues.

If EDA manages the coming changeswell, however, users will benefit fromthe inexpensive parallel computingpossible with manycore and the scala-ble compute resources available in theage of cloud computing. p


DESIGN PRODUCTS+

How manycore will reshape EDABy Abha Maheshwari

GLOBAL FEATURECOMMENTARY

Abha Maheshwari is a product manager in the Silicon Realization group atCadence Design Systems, where she is responsible for design explorationand planning technologies. She holds an MS from the University of California, Santa Barbara and a bachelor’s degree in electrical engineering from the Indian Institute of Technology Bombay (Mumbai).

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MANY SAY THAT VIDEO differential gain and differentialphase (DG and DP) are not visible to the human eye. So whywould anyone want to measure something that is invisible?(The reason that DG and DP are said to be “invisible” isbecause the magnitude is usually small and the change inscene brightness often masks the errors.)

The DG and DP tests were designed to detect very smallerrors before they could bother a human. This ensures goodvideo quality when the video passes through hundreds ofamplifiers in succession as it goes from source to destination.For amplifiers, analog-to-digital converters (ADCs) and digi-tal-to-analog converters (DACs), there are some simple waysto evaluate their DG and DP performance and verify the per-formance at both the sweet spot and near the power rails.

Again, this detects very small errors, ensuring signalintegrity with multiple stages. To better understand theimpact of DG and DP errors, let’s examine how DG and DPare applied to amplifiers, ADCs and DACs.

Simply, the impact of a DG or DP video error could trans-late into a person’s flesh tone changing as they move from abrightly lit area to a dimly lit area. First, for subcarrier typetelevision systems like NTSC, (North America and Japan), DGchange directly changes the saturation or how vivid the coloris, much like the chroma control on your TV. The DP errorwill change the hue of the color (toward green or purple) likethe TV’s tint control.

Second, in subcarrier TV systems such as PAL (Europe andChina), DG directly applies where DP results in a second-order saturation change. Third, for high definition (HD) andcomponent systems, DG and channel gain differences resultin colorimetry changes. Though NTSC is not broadcast wide-ly over-air in the USA, industrial and security video systemsare still dominated by the legacy technology.

Why do we need DG and DP specifications?Think of how a TV program is created. Multiple camera sig-nals are switched and sent through special effects equip-ment, recorded, played back and edited, all on their way tobecome a program. The program may be distributed overlong distances by microwave, fiber optics or satellite sys-tems, and eventually be broadcast over-the-air. A cable, DVDor satellite system then brings the program into our homesso we can enjoy it.

In this process, the video may pass through hundreds ofamplifiers. Each amplifier contributes a small amount of DGand DP to the video signal. To be sure that the video signal ispreserved, engineers designed a very sensitive test signal. p


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Differential gain and phase:Why measure it, if we can’t see it?By Bill Laumeister

Bill Laumeister is principal member of the technical staff with theAdvanced Video Strategic Applications Group at Maxim IntegratedProducts and works with companies selling consumer products. Hehas 38 years of experience and holds several patents in the videofield. He is the inventor of a video communications method calledVEIL (Video Encoded Invisible Light). It is being considered by theU.S. Congress in the Digital Transition Content Security Act as apossible patch for the “analog hole.” He can be reached [email protected].

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any other form of external input tuning, thereby simplifying designs and reducing

component count and cost. With the industry’s broadest portfolio of high performance

RF detectors, ADI can meet any RF power measurement challenge. Learn more at

www.analog.com/TruPwr.

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New TruPwr™ RMS detectors:ADL5902Accurate rms-to-dc conversion from 50 MHz to 9 GHz. Single-ended dynamic range of 65 dB. Best-in-class temperature stability of <±0.3 dB. Linear-in-dB output.

ADL5505For use in 450 MHz to 6 GHz Rx and Tx designs; 35 dB input powerdynamic range, inclusive of crestfactor. Excellent temperature stability.

In RF, ADI makes the difference.

Test and measurementPower meter handles 10 MHz to 50 GHz The 8650B power meter from Giga-tronicsInc. can provide up to 26,000 readingsper second in fast buffer mode. The power meter works with a selection ofGiga-tronics diode power sensors coveringthe 10-MHz to 50-GHz frequency rangeand power ranges from –70 dBm to +47 dBm.Full story: http://bit.ly/e6uB88www.gigatronics.com

NI blows the lid off VSA performancein PXI form factorNational Instruments unveiled the NI PXIe-5665, a 3.6-GHz RF vector signal analyzer that offers industry-leading phasenoise, average noise level, amplitude accu-racy and dynamic range. Full story: http://bit.ly/h3BI3pwww.ni.com

Handheld analyzers updated for installation, maintenance of LTE netsThe R&S FSH4 and R&S FSH8 handheldanalyzers from Rohde & Schwarz have beenupdated to provide more detailed measure-ments in LTE networks. Full story: http://bit.ly/gVGJ8mwww2.rohde-schwarz.com

Geotest adds support for Linux,LabView Real-TimeGeotest has released the GtLinux v1.0 software driver package, which allows Geo-test’s PXI instruments to operate under theLinux operating system. Full story: http://bit.ly/enJ7rNwww.geotestinc.com

Scalable platform tests multimode LTE, W-CDMA gearAnritsu’s ME7834 is a scalable platform fortesting wireless technologies, including multi-mode LTE and W-CDMA user equipment. Itenables complete design, certification andcarrier acceptance testing of multimode LTEor W-CDMA UE with incremental investmentsin capital test equipment.Full story: http://bit.ly/hPbu6dwww.anritsu.com

Arbitrary function generatorprovides 50 MHzThe TG5011G from Aim-TTi is a combinedfunction/arbitrary/pulse generator with afrequency range of 1 µHz to 50 MHz. It hasa GPIB interface in addition to the USB andLAN (LXI) interfaces of the standard model.Full story: http://bit.ly/eoZfGVwww.aimtti.com

ElectromechanicalAerco stocks high-reliability connectorswith 360° electrical screeningHarwin Datamate S-Tek 2-mm, high-reliabili-ty connectors, now stocked by Aerco, aredesigned for applications that require highlevels of EMC, such as military, aerospace,industrial and control equipment. Full story: http://bit.ly/eJqYn0www.aerco.co.uk

Connectors deliverhigh current-to-space ratioMolex Inc. introduced a version of itsEXTreme Ten60Power high-current connec-tor that delivers up to 260 A per linear inch, representing what Molex claims is the highest current density available in

a low-profile connector.Full story: http://bit.ly/fyzbU8www.molex.com

Power connector available in straddle-mount versionFCI’s high-power card-edge (HPCE) connec-tor is now available in a straddle-mountconfiguration, providing a lower-profileoption to facilitate system airflow.Full story: http://bit.ly/fjh5i1www.portal.fciconnect.com

Signal connector provides 100 percent signal integrityITT Interconnect Solutions has developed afully sealed (IP69K) RoHS-compliant signalconnector that it says is the first of its kindto withstand temperatures up to 150°C.Full story: http://bit.ly/gGuIINwww.ittcannon.com

Teledyne connectors transmit fiber-optic signalsTeledyne Reynolds Inc.’s Hyperion seriesconnectors integrate broadband fiber-optictransceivers. Full story: http://bit.ly/dGXuX1www.teledyne.com

Advanced technologyMobile MIMO Wi-Fi unveiled Marvell unveiled what it says is the firsthigh-performance MIMO combination radiowith advanced power management. TheAvastar 88W8797 is an 802.11n 2 x 2dual-band Wi-Fi system-on-chip supportingnext-generation mobile devices.Full story: http://bit.ly/gouuj5www.marvell.com


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Software Engineers, Multiple Positions for both Level II, Entry Level& Level II, Advanced: Acme Packet Inc, a worldwide leader in sessionborder controller network infrastructure products, has SoftwareEngineer (Level II, Entry Level & Level II, Advanced) openings attheir Bedford, MA headquarters. Responsibilities include:Socket/Network programming using IP, TCP, & UDP in a Linux-basedenvironment; analyze customer needs to design/develop software inC/C++ within time/cost constraints; modify existing software/correctsoftware defects to customer satisfaction; develop functional/designspecifications on new software development features; support varioussignaling protocols and/or security protocols as required; & interactdirectly with end users. Minimum requirements for both open posi-tions: M.S. (or foreign equivalent) in Computer Science or any related Computer or Engineering fields, including TelecommunicationsSystems Management, Electrical Engineering, etc; proficiency inC/C++ programming languages; prior knowledge designing & developing software in a Linux RTOS based development environment;knowledge of signaling & security protocols. In addition to theserequirements, applicants for the position of Software Engineer (Level II, Entry Level) must have at least 1 year of software develop-ment &/or sustaining experience; applicants for the position ofSoftware Engineer (Level II, Advanced) must have at least 2.5 years ofsoftware development &/or sustaining experience. Send cover letter &resume to: Susan Anderson Acme Packet Inc 100 Crosby DriveBedford, MA 01730. Applicants must include the following trackingcodes to be considered for each position: Software Engineers (Level II,Entry Level): #1300-100; Software Engineers (Level II, Advanced):#1300-101.

SEARN A COOL HUNDREDTell us about a memorable experience you’ve had solving an engineering problem athome or work, and we’ll pay you $100 if we publish it, plus eat up a modest chunkof your Andy Warhol 15 minutes. E-mail [email protected].

Like this content? Check out EE Life, our new community site, or sign up for ourweekly EE Life newsletter and get this content delivered directly to your inbox:http://tiny.cc/goykk. It’s chock full of unique content written by, inspired by and com-mented on by engineers. From things that go bump in the lab to products that didn’tperform quite as expected and the absurd things that happen, EE Life explores what itmeans to be an engineer today.


EE LIFE

Raising alarms in the design groupBy John Rettig

PRACTICAL JOKES

A COLLEAGUE OF MINE pulled offthis prank in the early 1980s. Though Iwasn’t the culprit, I had pulled similarstunts in the past, so I got the blame. Ofcourse, I took that as a compliment.

I worked in a microcircuits designgroup. My coworkers included “Bob,” a PhD who analyzed problems to a faultand thus took a long timeto solve them, and “Fred,”a practical, hands-on typewho would just go in andchug through a problem toget it done, leaving thefine tuning for later. Need-less to say, there was fric-tion between them.

We all worked in a noisy environment.Our second-level manager kept a white-noise generator at his desk to mask theambient noise and reduce stress. Bobasked to borrow the unit one day to eval-uate whether it would be worth gettingone of his own. The manager said he’ddrop off the machine at Bob’s desk at theend of the day; Bob could try it out allthrough the next day and give it a reallygood assessment.

After the manager dropped off theunit as promised and Bob left for theevening, Fred sprang into action. He dis-assembled the unit and happily notedthat the 120-V power in the box wasswitched through a DPDT switch. He

then located a battery and a lift truckbackup alarm in the engineering stock-room and proceeded to wire themacross the unused half of the DPDT on-off switch. When he was done, he tapedeverything down tight inside the box,reassembled the white-noise generatorand placed it back on Bob’s desk.

The next morning, Bobcame in, plugged in thewhite-noise generator and hitthe switch. The backup alarmblasted away, drowning outthe unit’s white noise, whichwas still working.

Bob jumped up, amazed,and immediately began for-

mulating theories to explain what hadhappened. As he went over to the man-ager to share his long-winded ideas, theunit became unplugged. Bob, failing tonotice the power cord dangling on thefloor by his feet, theorized away as thealarm continued to blast.

Then the manager noticed the loosecord and held up the plug for Bob to see. Only then did Bob realize he hadbeen punked.

After the unit was taken apart andthe modification discovered, I wasassumed to be the prankster. My protes-tations of innocence fell on deaf ears.

Fred admitted to me only much, muchlater that he’d been the perpetrator. p

Lowbrow funwith ‘highfalutinmath’ hackBy Don Dodge

WHEN I WAS A STUDENT years ago atLong Beach City College in California,the school had an IBM 1620 that we stu-dents could actually touch. The schemat-ics for the computer were left with thesystem for use by service technicians.

Being enterprising students, we stud-ied them to understand the inner work-ings of the machine. The 1620 had 8 kbytes of read/write core memory and8k of read-only memory that containedthe operating system. The write line forthe ROM terminated on a test pointabout six inches from the write line onthe read/write memory.

We decided to try jumpering the testpoints and found—voilà—that wecould actually write to the read-onlymemory. Next, we discovered thesquare-root routine and made a minorchange to cause the IBM 1620’s consoletypewriter to type out “I ain’t cut outfor this highfalutin math” as itprocessed the square root.

Our fun came in watching the IBMtechs in action. The first group couldonly do routine maintenance and hadno clue what was causing the problem.(Of course, we’d removed our jumperright after writing our instructions.)The second group could not fix it either.

The school walled off the computer,barring students from further access.After about a month, an elderly IBMtech showed up in a white coat (the oth-ers wore suits) and chased away the oth-er IBM techs. He went to the operator’sconsole and poked around.

We watched from the other side ofthe fence as the light bulb went off inhis head. He pulled a jumper from hispocket, opened the computer and—with a few instructions—placed a jumparound our routine, fixing the IBM 1620.

Some years after our stunt, I heardthe word “hack” for the first time. p

Don Dodge is vice president of research atCalmont Wire and Cable.


EE LIFE

7I ENJOYED READING Chuck Hill’sstory about EDGAR, the command-lineinterface replacement (www.eetimes.com/4211972). It brought me back to the early ’80s when I worked my waythrough engineering college at the Uni-versity of Colorado at Boulder as a Digi-tal Equipment VAX/VMS hacker—er,programmer—at the National Oceanicand Atmospheric Administration and,later, Mobil Oil.

Like RSX-11 operating systems, VMSallowed for shenanigans through whichusers could game their friends and ene-mies. The classic was to alter someone’s.login script to redefine certain com-mands or to run init scripts, much like.cshrc and alias today in Linux andUnix. At NOAA, we developed all sorts ofvariations of this script, but the best was“Removing all files—press ‘del’ to stop.”It didn’t actually delete files, of course,but was only a simulated listing of all ofthe files, preceded by the word “deleting.”Naturally, the script redefined dir tosimply print “no files found.” But manyfrantic victims of the prank nearly

broke the del key in their panic.My ultimate hack attack occurred one

summer at Mobil Oil. We had a bone-head on staff who (unfortunately)shared my first name. This other Jeffonce altered the systemwide .startup fileto “fix” the ASCII mapping; his foolishhack permanently disabled all of theVT220 terminals, making it impossibleto go back and edit the changed startupfile to fix it.

As a result of the other Jeff’s mischief,I had to pull out the manual on the oldline editor and use the only workingterminal in the whole system, an agedteletype, to search for and fix his ill-advised modification. Feeling justifiedin my thirst for revenge—and evencompelled to solve our “Jeff problem”—I found ways to slow his “productivity,”devising a series of scripts and hacks aspart of my system setup files job.

Essentially, I created a daemon thatsat in waiting for Jeff to log in. Once he did so, the daemon “niced” every-thing he did, including every process hespawned. It even, on occasion, froze his

processes for minutes at a time. And itwas not only in his .login but in the sys-tem .startup as well—not just once buttwice. One instance was obvious, but Ihid the other by giving it a similarname to an ancillary disk process. Oncestarted, this sweeper process went back,checked to see if the .login or .startuphad been altered, and “fixed” them backto the daemon version. Finally, I addedthe sweeper to a backup routine thatran nightly and to another that ranweekly. I also implemented a full back-up to ensure the reversal of anyattempts to remove my hack.

It took months for the group to ferretout all of my hidden Jeff-containmenthacks. The next summer, Mobil Oilrehired me. On my first day, the newmanager called me into his office. Heacknowledged my cleverness, told methe other Jeff was now gone andwarned, “Never do that again.”p

M. Jeffrey Holley is a software engineer atInfoPrint/Ricoh (Boulder Colo.). He earlierworked as an ASIC designer at LSI Logic.

March contest: Deadline March 31 Flex those little gray cellsand pen an amusing captionfor our cartoon.

Submit your caption andview the contest rules athttp://bit.ly/marchcaption,or e-mail your submission [email protected]. We’llchoose three finalists, andour readers will vote for theirfavorite.

The author of the winningentry will receive a signedcopy of the cartoon, whichwill be published in anupcoming issue of EE Times.

Press ‘del’ to stop . . . Stop! STOP! HELP! By M. Jeffrey Holley


LAST WORD

President Obama, in January’s State of the Union Address, made innovation a priority for empowering the economyand ensuring long-term competitive-ness. He continued his innovationmantra when outlining his budget thenext month. Despite the President’s sup-posed commitment toinnovation and R&D, heis supportive of legisla-tion that severely discour-ages those very things.

Likewise, Senate Judi-ciary Committee chair-man Patrick Leahy(D-Vt.), the chief propo-nent of the AmericaInvents Act, has paid lipservice to the idea ofencouraging innovationeven as he has pushedlegislation that would dojust the opposite.

As the founder andpresident of AmericanInnovators for PatentReform, I am disappoint-ed to see a rehashing of the same badideas that characterized previous, failedpatent reform proposals.

For one, the President’s budget wouldhave the U.S. Patent and TrademarkOffice impose a “temporary surcharge”to “better align application fees withprocessing costs.” Last year, the USPTOcollected approximately $51 million in

fees over and above its authorized budg-et. That’s money it could have used forhiring more patent examiners. But Con-gress only let it keep the amount allo-cated for its fiscal 2010 budget. The restwent to the Treasury. This amounts tonothing short of a tax on innovation. If

you want more innova-tion, taxing it more heavi-ly is not the best approach.

Another bad idea ispost-grant review. Propo-nents tout this provisionas a way to evaluate patentvalidity that is “potential-ly 50 to 100 times lessexpensive than patent liti-gation,” according to aWhite House fact sheet onpatents. Yet it would pilework more on alreadyoverburdened patent offi-cials and likely lengthenthe patent backlog.

Post-grant review will beunaffordable for manysmall businesses, universi-

ties and, especially, independent inven-tors. Driving up the cost of what isalready an expensive process will dimin-ish intellectual property rights by forcingmany inventors to abandon their patents.

The current legislation also proposeschanging America’s traditional first-to-invent system, firmly rooted in the Con-stitution, to the inferior first-to-file

regime. The United States has alwaysawarded patents on the first-to-inventbasis. If two parties file for patents onsubstantially the same invention, thepatent is awarded to the one who canprove to have invented first. In countriesthat use a first-to-file system, inventorsrush to patent offices with half-bakedapplications, many of which ultimatelytranslate into low-quality patents.

To reduce infringement damagesawards, the America Invents Act pro-poses requiring that judges preventjuries from even considering slappingan infringer with a large judgment. Thisdevalues patents by decreasing legiti-mate damage awards.

Another provision seeks to make itharder for patent owners to prove will-ful infringement in order to obtain tre-ble (or triple) damages. If this sectionpasses, infringers will have less of a rea-son to settle, clogging the courts withlonger litigation.

USPTO director David Kappos hasalready improved efficiency throughreforms and experimental programs.Future reforms should encourage quali-ty patent examination while encourag-ing innovation by making it quickerand less expensive to obtain patents.

One way to do just that is to create atwo-tier patent system, with juniorpatent applications examined only fornovelty and senior patent applicationsalso examined for nonobviousness, as allpatent applications are examined fortoday. A junior patent—in the mode ofthe Australian petty patent, GermanGebrauch patent or the utility modeladapted in most other countries—wouldhave shorter terms and lower filing fees.

While a determination of nonobvi-ousness requires a subjective humanjudgment that only a qualified examin-er can make, examination for noveltycan and should be computerized.Advances in artificial intelligence andsemantic search make that possible.

Patents are critical to encouraginginnovation by enabling inventors tokeep the fruits of their labor. They arealso the primary drivers of job cre-ation. The Senate should reject harmfulchanges to the U.S. patent system.p

By Alexander I. Poltorak is the founder andpresident of American Innovators for PatentReform.

The U.S. Senate started deliberations on S. 23,the Patent Reform Act of 2011, on Feb. 28. TheSenate Judiciary Committee unanimouslyapproved the bill—since renamed the AmericaInvents Act of 2011—without, amazingly, testi-mony from a single inventor. If voted into law,this legislation will hurt American innovation.

Patent reform act detersinnovation, jeopardizes jobs

If you wantmoreinnovation,taxing it isnot the bestapproach

eetimes mar 2011

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