eecs 312 discussion
TRANSCRIPT
Overview
• Reminder
– HW 2: Due Oct 10
– Midterm: 8 October 19:00–20:30 in 1670 BBB
– Close book. One sheet note.
NMOS
G
S D
A unified model
1. If VDS is minimum: Linear region
2. If VGT is minimum: Saturation Region 3. If VDSAT is minimum : Velocity saturated region
NMOS
G
S D
CMOS Process
Cross-Sectional View
3 Dimensional View
Layout View
Width
Channel Length
Channel Length
Width
Inverter Layout
Width
Channel Length
NMOS
G
S D
5 Important MOSFET Capacitances
DS
G
B
CGDCGS
CSB CDBCGB
Gate-to-channel Capacitance (CGC)
S D
G
CGC
S D
G
CGC
S D
G
CGC
Cut-off Resistive Saturation
CGCB
CGCS
CGCD
Properties of Static CMOS gates
• Voltage swing=supply voltage (full swing)
• Logic level is not dependent upon the relative device sizes (ratioless)
• A path with finite resistance between the output and VDD or GND
• Input resistance is extremely high
• No direct path exists between supply and ground under steady-stage
CMOS inverter- Intuitive Perspective
Power
• Dynamic Power
• Static Power
• Short-Circuit Power *
Power