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Ruggedized Camera Encoder P14571 Hornyak, Jason, Moreno, O’Connor, StreatMay 15, 2023

CoaXPress Communication Subsystem Detail Design Rev.A

Author: Lennard Streat, Computer Engineering, RIT

Multi-Disciplinary Senior Design I

RIT Ruggedized Camera Encoder (P14571)

1 | P a g e [email protected]

https://edge.rit.edu/edge/P14571/public/Home


Table of Contents

1. Module 1: Conceptual Overview Introduction & Application Transceiver Concepts Data Transmission Rate Table CoaXPress (CXP) Daughter Cards Trade Analysis Design Overview

2. Module 2: CoaXPress Physical Layer High-Speed Serial Interface Description High-Speed Mezzanine Card (HSMC) Design CoaXPress HSMC Schematic Mechanical Implications Bill of Materials

3. Module 3: CoaXPress Firmware Layer CoaXPress Communication Standard

4. Module 4: Conclusion

I. Conceptual Overview




Introduction & Application

A Ruggedized Camera Encoder (RCE) is a compact and robust system that analyzes a stream of image data in real-time. Typically, video analytics are completed using post processing techniques on a unit that is separate from the camera stream. This system will eliminate the need for post processing, which cuts down on turnaround time and the need for a secondary system.

The goal of this project is to deliver a working prototype that will have a small enclosure, with two tethered camera inputs, acquiring HD 1080p 30fps image data. The system will be capable of processing the image data in real-time running different video analytics algorithms. It will be capable of streaming compressed image data over GigE to a standard video client for diagnostics.

The purpose of this document is to provide a detailed treatment of the high-speed communication layer that will manage transmission of data from a sensor to a host processor; namely, from a high-speed, high-resolution camera sensor to an image processing DesignCore board.

Transceiver Concepts

For this engineering design project data will be received from a camera sensor over a coaxial cable, processed inside of an image processing DesignCore card, encoded to standard H.264, and then transmitted out to other devices using a variety of I/O standards (such as USB, HDMI, and GigE). This document addresses the first layer of this process, namely the reception of the camera sensor data over a coaxial cable using the CoaXPress (CXP) high-speed serial communication standard. In later modules of this document further details will be provided concerning the aforementioned concepts. However, this section will deal address transceivers.

What is a transceiver?

A transceiver (XCVR) is a device that has both transmission and receiving functionality paired together into one circuit module. For the purpose of this engineering design project transceivers will explicitly be used to refer to the interface comprised of a Deutsches Institut Für Normung (DIN 1.0/2.3) coaxial cable connector.


Figure—1.1a: Radio Grade 59 (RG59) DIN 1.0/2.3 coaxial cable.



What is a coaxial cable?

A coaxial cable (Fig. 1.1) is a cable that has a central core that is shielded by a dielectric insulator, wrapped in a conducting metal shield and contained in a plastic jacket (usually polyvinyl chloride—PVC). The term “coaxial” comes from the fact that the conducting core runs in parallel to the two sub-layers of the metallic shield. This cable is designed to improve signal integrity via high and low frequency noise protection as well as impedance regulation (for attenuation minimization). The plastic jacket is there for

mechanical protection, the dielectric maintains consistent impedance along the wire. The metallic shield is comprised of a braid of wire and an aluminum wrap; the wire braid shields the data cable from low frequency noise (AC noise) and the aluminum wrap shields the data cable from high frequency noise (RF signals).

FPGA Transceivers

Transceivers typically operate at higher frequencies than the host processor because the host processor provides data to the transmitter in parallel (using multiplexing), and the transmitter sends the data serially. “The task of parallel-to-serial conversion is performed by a multiplexer (MUX) in the transmitter. The MUX should be synchronized with a system clock generated by a clock multiplication unit (CMU) that incorporates a VCO, a PLL and a clock path [4].” For instance, if a processor transmits 8-bit data at 500 Mbit/s, the transceiver must to transmit that data at 4 Gbits/s to keep up. Transceivers are realized in three general layers—the Media Access Controller (MCA), Physical Coding Sub-Layer (PCS) and the Physical Medium Attachment Layer (PMA).

1. Media Access Controller (MAC)—assembles packets to be given to PCS to be transmitted across the link. Disassembles packets received across the link. Handles error and fault messages from link.

2. Physical Medium Attachment Layer (PMA)—handles encoding the data being transmitted to the format expected by the receiver/transmitter. E.g. encoding, decoding, scrambling, descrambling.

3. Physical Coding Sub-Layer (PCS)—converts digital data to serial analog stream. E.g. parallel to serial conversion.


Figure—1.1b: Coaxial Cable.



Figure—1.2: Transceiver general architectural diagram. The MAC layer is not included, because it is assumed that this is implemented in the FPGA fabric [5]. This is the full duplex

data path.

The PCS may be implemented either in hardware, or in software, but the PMA must be handled in hardware. For most real-world applications, a standard specific transceiver interface is defined. However, FPGA transceiver interfaces are designed to be flexible and as such are fully customizable. For instance, the complete PCS layer depicted in Fig. 1.2 may be bypassed, where the functionality would then be implemented in the FPGA fabric directly.

The transceiver interface (Fig. 1.2) is described as being a SerDes, or a Serializer-Deserializer. A SerDes takes a multiple data line input and converts it a representation that features fewer wires. There are significant benefits to using a SerDes, such as EMI reduction, lower power consumption, and cost reduction.

Figure—1.3: SerDes Architecture [3].

For this engineering design project the CoaXPress interface is a SerDes interface (Fig. 1.3), where the transmitter (TX) acts as the serializer and the receiver acts as the deserializer (RX). At gigabit signaling speeds explicit clocks are not typically used.




Consequently, the clock rate information is embedded within the data using encoding techniques, such as 8B/10B encoding standard. The SerDes interface is capable of operating at a clock frequency higher than that of the host FPGA by using Phase-Locked Loops (PLL) to scale up the clock frequency. Synchronization occurs between the transmitter and receiver during transmission using various techniques beyond the scope of this discussion.

Phase-Locked Loop

“Feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Phase-locked loops can be used, for example, to generate stable output high frequency signals from a fixed low-frequency signal [6]”.

Figure—1.4: Phase-Locked Loop functional diagram (left). PLLs use a source frequency (FREF), which is usually compliant to the Rubidium Standard, because the signal integrity at

the output of the PLL is only as good as that of the input signal. For high-frequency-clock serial communication, the clock must have a low-jitter, high-reliability signal. Reliability of

the output signal is also dependent upon the delay of the internal components, especially the low pass filter (loop filter) [6]. The figure to the right is the Voltage Controlled Oscillator (VCO); discussion of this is beyond the scope of this design document [7]. Clocking in the

Transceiver are managed by configurable Clock Management Unit PLLs, ATX PLLs, MPLLs, or/and FPLLs; the availability of each is FPGA dependent [8].




FPGA Transceiver Classes

Some FPGA manufacturers provide a line of boards with transceiver communication capabilities. For the purposes of this project, only the Xilinx and Altera brands were considered (Table 1.1).

Transceiver Grade FPGA Speeds Cost

High-EndStratix V GX/GS/GT

8.5Gbs – 28Gbs> $4,995.00

Stratix IV GX/GT > $4,495.00

Mid-RangeArria 10 GX/SX/GT

6Gbs – 28.1GbsUnavailable

Arria V GX/GT/GZ > $3,995.00Arria II GX/GZ > $3,195.00

Low-CostCyclone V GX/GT

3Gbs – 5Gbs> $1,099.00

Cyclone IV GX > $1,295.00Table—1.1: Altera FPGA transceiver capability classification. For the purpose of this project

FPGAs at the lower end may be used (to minimize costs) because the project only requires that one camera be used for the demo, but that the design is extendable to more. One camera may

easily be processed on a 3Gbs transceiver [8].

Transceiver Serializer and Deserializer Block Diagrams

The SerDes interface is very complex in nature, especially on FPGA systems (due to the flexibility). Altera and Xilinx provide IP Cores to simplify transceiver interface design. On the Altera website a tutorial is provided that dives deeply into the functionality of Transceivers for the Altera brand FPGAs. Therefore, this topic will not be deeply covered. Note: Some online documentation addresses the logical element consumption of the IP Cores.

Figure—1.5a: The Serializer/Transmitter path block diagram. This is an expansion of the transmitter block diagram provided in Fig. 1.2. The PCS path is circled [8].

Serialization of the data occurs in five major steps.

1. (PCS) Phase Compensation—because the serializer typically operates at a different frequency than the host processor (FPGA), phase compensation is made to synchronize the host processor and the serializer.




2. (PCS) Byte Serialization—Reduces the FPGA fabric clock rate requirements while leveraging the higher data rate necessary by the transmitter.

3. (PCS) 8B/10B Encoding—Takes 8-bit data and a 1-bit control to 10-bit code groups. Ensures that the data transitions enough to allow the deserializer to synchronize with the receiver. Maintains a neutral running disparity, which has an impact on EMI effects.

4. (PMA) Bit Serialization—converts parallel to serial data. It has two clocks (one on the parallel side, and another on the serial size. Note: the PMA is not explicitly labeled in the figure.

5. (Post PMA) Transmitter Buffering—hardware that improves signal integrity before transmission of data to optimize data quality and power consumption. An example technique that is applied is pre-emphasis, which magnifies the high frequencies of the data signal and filters out noise. Signals are transmitted in a different format.

Beyond the aforementioned steps there are error checking tests that are made using a Pseudo-Random Binary Sequence (PRBS) and further customizations. For instance, higher end transmitter interfaces have a longer serialization pipeline. Furthermore, the whole PCS phase may be bypassed, as previously mentioned. For more information reference the Altera Transceiver Basics tutorial [8].

Figure—1.5b: The Deserializer/Receiver path block diagram. This is an expansion of the receiver block diagram provided in Fig. 1.2. Figure should be read from right to left.

Deserialization occurs in ten primary steps:

1. (Pre PMA) Receiver Buffer—converts differential input signal into a CMOS value. Most importantly, it supports equalization (to aid in signal integrity), which compensates for signal degradation due to factors such as power loss that may have occurred during transmission. High end transceivers support adaptive equalization.

2. (PMA) Clock & Data Recovery—clock data is recovered from the received data to synchronize the data reception process. A high-speed clock and low-speed clock are generated to handle the deserializer and the PCS module, respectively.

3. (PMA) Deserializer—converts the serial data (LSB first) to parallel data.




4. (PCS) Word Alignment—uses an alignment pattern to identify data word boundaries and realigns data via method such as shifting. This ensures that the data will be properly read by the receiving processor.

5. (PCS) Deskew Step—aligns all input channels to the channel 0 clock. Ensures that multi-channel data arrives at the proper rate and handles error signaling in the event that alignment is lost.

6. (PCS) Rate Matching—compensates for PPM differences between transmitter and receiver. Removes or inserts characters in the data stream to pad the data stream (preventing overflow and underflow); regulates data rate into the subsequent stages. Each serial transmission standard stuffs the data stream with different bit patterns. (Cannot be used with the Byte deserialization phase).

7. (PCS) 8B/10B Decoding—undoes the encoding step made in the transmitter. Not all serial transmission standards have this encoding/decoding step. It may detect disparity errors.

8. (PCS) Byte Deserialization—this step, in like manner to the same step in the transmitter, reduces the clock rate requirements of the host system. This works in reverse by outputting parallel data at a slower rate than the data is received.

9. (PCS) Byte Ordering—restores transmit byte order by re-ordering bytes after the byte deserialization process. (Cannot be used with the rate matcher). This step must handle scramble codes (they should not be stored).

10. (PCS) Phase Compensation—ensures correct timing between transceiver and the FPGA, in like manner to the transceiver compensation step.

Note: There are more complex versions of this signal flow pipeline [8].

Data Transmission Rate Table

Today, there are many serial data transmission standards in use. This section is devoted to providing a brief background on several of the available serial interface standards. Serial communication interfaces exist to provide a robust, cost-area effective solution to intersystem communication. Some older standards are typically used to interface in low-speed requirement environments, such as RS232, RS422, RS423, and RS485. Some applications include low-speed sensor interfacing, short distance device communication, and more. As time has progressed mid-speed communication standards have been developed that are designed for operating in the megabit range such as I2C, SPI, and USB and CAN. Sample applications are inter-processor communication on a single PCB, consumer devices, automotive control and communication, and multiple-device communication networks.




For some modern applications higher speeds are necessary. For instance, modern CPU-to-memory interfaces, video processing, bioinformatics, Neuromorphic computing and simulation. In such data-intense applications communication standards such as GigE, USB 3.0, SATA, HDMI 1.3, and PCIe 3.0 are used. CoaXPress falls in this category of communication standards. It exhibits transmission speeds far superior to other standards in its class, such as Camera Link (which operates in the megabit range). An approximate comparison of the serial transmission standards has been provided in the following table.

Standard Max Data Rates Configuration Distance CostRS232 115200 bit/s 2/9 Pins 15 m $3/meter

CAN 1 Mbit/s 2 Pins 40 m $1/meterRS485 2 Mbit/s 2/3 Pins 50 m $3/meter

I2C 3.4 Mbit/s 2 Pins 4 m $3/meterSPI 50 Mbit/s 4/8 Pins 10 m $3/meter

GigE 1 Gbit/s 8 Pins 30 m $4/meterUSB 3.0 5 Gbit/s 4 Pins 5 m $5/meter

SATA 6 Gbit/s 15 Pins 2 m $12/meterCamera Link III 2 Gbit/s SFP 300 m $19/meter

CoaXPress-6 6.25 Gbit/s Coaxial 68 m $5/meterHDMI 1.3 10.2 Gbit/s 19 Pins 8 m $6/meterPCIe 3.0 128 Gbit/s 82 Pins 15 m $20/meter

Table—1.2: Approximate specifications for each serial data transmission standard. Note: these rates are simply provided for reference, not all of the values are specifically consensually agreed upon. Data was compiled via various internet searches. The purpose of this table is to

depict the relative performance of each cable standard. CoaXPress and Camera Link (competing technologies) have been highlighted [9].

CoaXPress Daughter Cards Trade Analysis

An FPGA Mezzanine Card (FMC) is an ANSI standard that defines the I/O standards for interfacing mezzanine modules to a field-programmable gate array. Modules that are added to a host system are called mezzanine modules or daughter boards/cards; mezzanine modules may be hardware accelerators, I/O cards, etc. Altera has also published the High Speed Mezzanine Card standard (HSMC), for similar applications, with a different form-factor.

This section highlights several CoaXPress mezzanine cards currently available on the public market. FMCs support transmission speeds up to 10 Gbit/s. The connectors (Fig.




5) for these mezzanines are purchased through the Samtec Company. Samtec sells these connectors in two types—high pin count (HPC) and a low pin count version (LPC).

Figure—1.6a: FMC Connector Form Factor [10].

Figure—1.6b: FMC Connector Form Factor [13].

CoaXPress (CXP) is an “asymmetric high speed point to point serial communication standard for the transmission of video and still images, scalable over single or multiple coaxial cables. It has a high speed downlink of up to 6.25Gbs per cable for the video... ” [6]. Further details concerning the CXP standard are provided in later sections. This remainder of this section is dedicated to presenting technology used to interface with CoaXPress devices. The majority of the products in this space are completely integrated systems or frame grabbers; frame grabbers are devices that capture individual still frames from an analog video signal. Therefore, a large majority of products were not presented seeing as the capabilities are very similar.



http://www.samtec.com/standards/vita.aspx


Kaya Instruments HSMC for CXP

The Kaya organization has developed “the industry’s first High Speed Mezzanine Card defined by Altera providing a high performance CoaXPress compliant connection” [7]. This card (HSMC-CXP) is capable of interfacing with up to 4 CXP mode cameras. The card also features control GPIO. A hardware block diagram has been provided. HSMC-CXP features 8 Bayonet Neill-Concelman (BNC) Radio Frequency (RF) connectors, which are quick, connect/disconnect coaxial cable connectors. The four connectors on the left are host links and are provided with 13W power via Power over CoaXPress (PoCXP). The device is capable of operating in an environment with -40C to 85C temperature ranges. The same company also released an FMC compatible CXP mezzanine card. Currently, this is the only company that provides

an HSMC/FMC compliant CXP mezzanine card. It also features Opto-isolated outputs.

Figure—1.7b: HSMC-CXP (left; Fig. 1.7a) and FMC-CXP (right) [12] [14].


Figure—1.7a: Kaya HSMC-CXP [12].



Matrox Radient eV-CXP

The Matrox Radeint eV-CXP is a high performance CoaXPress frame grabber, capable of reading data from 4 devices. It features four BNC connectors that may be connected to an external sensor. There is a memory interface on board that may be connected to up to 4 GB of storage. A GPIO interface is placed on the board in addition to a PCIe 2.0x8 bus. All of the frame reconstruction and color space conversion is done on board. This system is not relevant in terms of its form factor, but is relevant with regards to its CoaXPress interface. BitFlow (as well as several other companies [18]) has designed similar boards, such as the Cyton-CXP [16].

Figure—1.8b: Matrox Radient eV-CXP block diagram [23].


Figure—1.8a: Kaya HSMC-CXP [23].



Unknown CoaXPress Evaluation Boards

There are several CoaXPress evaluation kits on the market, albeit they are poorly documented. This section is dedicated to addressing those boards. Microchip owns two IPs in this space: EVB-DBSUB1584 and EVB-DSUB1586—a transmitter (camera) and receiver (host) module, respectively. These devices are available for purchase for just under $400.00, but are not documented. Also, the sensor-to-image website (s2i.org) has an FPGA core. In the picture demonstrating the physical setup of the evaluation system, there are two unnamed CoaXPress cards—one used on an Altera board and another on a Xilinx board [17].

Figure—1.9: The functional diagram for the core is depicted (left) and the daughter card used to demo it (right). It has two female BNC connectors, a camera, power and some other

circuitry, presumably for control and configuration on board [17].

In light of the aforementioned designs, the basic components and functionality needed to produce a feasible design become clear. For the application that this document is addressing, the CoaXPress HSMC/FMC must meet the following requirements:

1. Host connectivity—this enables the device as a CoaXPress receiver. The design is expected to be extendable to 4 inputs—this requires the HSMC/FMC to utilize 4 CXP DIN 1.0/2.3 connectors. The device must also be capable of communicating the transmitter (camera) to control it.

2. PoCXP—Power of CoaXPress support will supply 13W power to the transmitting device, which will be a camera. The device will not have a power source. Therefore, this is vital.

3. Small Form Factor—the FMC/HSMC presented by the Kaya Instruments Company was bounded by 70.5mm x 88mm (both form factors for the Kaya products were averaged together).




4. CXP-6—to meet the 6.25Gbs requirement, the device must be CXP-6 compliant, or better.

5. Temperature Stability—the HSMC/FMC must be capable of operating within the temperature range of -40C to 85C.

6. Optoisolation—since the output operates at high frequencies, the logic on the board should be isolated from the outputs/inputs [19] [20] [25].

7. SamTec Connectors—SamTec connectors must be used for the HSMC/FMC output. Basic GPIO options are also desirable, as they allow for simpler debugging and control.

8. Power—the board must be relatively low power; but still capable of delivering 13W of power. Surge protection should be available [24] [25].

In the next section, the design of the hardware of the proposed device will be more thoroughly explored.

Design Overview

The system proposed in this detailed design document is discussed within this section. Various block diagrams are presented in this section (Fig. 10a & b). In the previous section, design requirements were identified, via a trade analysis. These requirements were compiled into features and a light review of contemporary technology was made as a part of a feasibility analysis.

Design V.1

The design features four DIN 1.0/2.3 connectors (Fig.1.10a), for connecting with the CXP coaxial cables. Within the original specification, the design is only required to be capable of deserialization. However, serialization capabilities have been indicated on the functional block diagram; having transmission capabilities is useful for reuse purposes. Since this was not a requirement, only two of the connectors on the board were given transmission and reception capability.

Another design concern was EMI effects. To address this, all logic on the board was placed within shielding (red box with dotted lines). Electromagnetic interference would originate from the coaxial cabling. No protection was placed on the GPIO or the HSMC output connector. However, this is also an option, but likely to be unnecessary as this was not explicitly included in any of the other designs (See Trade Analysis). GPIO has been inserted to control each individual DIN 1.0/2.3 interface. The main purpose of this interconnection is to enable/disable power to these components—this is expected to reduce power consumption in applications that do not use all of the DIN 1.0/2.3 interfaces.




Figure—1.10a: 4xCXP-HSMC design configuration (v.1). It has optoisolation on the BNC connectors to protect the equalization circuitry from voltage transients in the sensors. PoCXP

is implied in all the DIN 1.0/2.3 connectors.

Design V.2

A secondary layout variation is presented (Fig. 1.10b). In this design, power control is handled at the DC-DC power supply interface instead of separately from that component. In this design the DC-DC converter output is essentially gated by a buffering system (such as tri-state buffers) or transmission gate logic. Also it should be noted that within both designs LEDs will be placed at various points to provide visual feedback.

One useful utility to this design is that a basic loop-back test may be done by connecting the driver modules to the single function receivers. The FPGA may transmit frames through the drivers and read back the values via the receivers. These designs assume that the best-practices have been applied (such as adding terminations).




Figure—1.10b: 4xCXP-HSMC design configuration (v.2). It has optoisolation on the BNC connectors as with v.1, but the control circuitry was condensed to improve ease of

implementation.

Note: It is likely that the trace lengths must match for each of the transceivers. To accommodate this fact, the wires running from the DIN 1.0/2.3 connectors closest to the output should be lengthened to match that of those further away from the HSMC connector. This is useful in the event that the DIN 1.0/2.3 connectors are being used to read in time associated data in parallel, so as to match the timing. Traces must be matched to ±50 mm. PCB layering was not considered in this section. However, this is a concern that must be incorporated into the design.




Figure—1.10c: 4xCXP-HSMC design configuration (v.3). It has optoisolation on the DIN 1.0/2.3 connectors as with v.1, but the control circuitry was condensed to improve ease of

implementation.

Design V.3

The design provided in Fig. 1.10c was the final design that was chose. The hardware equalization and drivers are providing in a hardware IP owned by the EqcoLogic company.




II. CoaXPress Physical Layer

High-Speed Serial Interface Description

The HSMC specification (owned by Altera) defines the electrical and mechanical properties of high-speed mezzanine card adapters for FPGA-based host processors. The purpose of this standard is for interprocessor communication and high speed data transfer. This design is based on the Samtec 0.5 mm pitch, surface-mount QTH/QSH connector family. The connector is separated into three banks—each having a separate clocking mechanism (CLKINx/CLKOUTx), data pins and special functionality. This section is a summary of the requirements in [13].

HSMC may come in various sizes, but must adhere to the standardized dimensional envelopes. The host processor must also provide 12 V DC and 3.3 V DC to the mezzanine card. The mezzanine card must feature a Samtec ASP-122952-01 connector, which pairs

with the Samtec ASP-122953-01 host board connector. The socket is comprised of 160 total pins, and 12 ground plane connection pins in the center. Bank 1 has 40 pins; banks 2 and 3 have 60 pins. Note: the host board provides transceivers to bank 1 and single-ended signals to banks 2 and 3—the single-ended signals are capable of differential signaling (such as LVDS).

The specification specifies a minimum clearance on the connector (Fig. 2.2a).

Figure—2.2a: Physical layout requirements of the HSMC PCB. The HSMC design must align the HSMC port all the way at one end of the PCB. There are restrictions on the PCB width and

clearance near the connector [13].


Figure—2.1: HSMC logo [13].



High-Speed Mezzanine Card (HSMC) Design

Pins of prime importance on the HSMC port include: pin 1 (XCVR_TXp0), pin 3 (XCVR_TXn0), pin 2 (XCVR_RXp0), and pin 4 (XCVR_RX_n0). The receive signals must also be terminated by 100-Ohms differential; termination should be handled on-die, but board-level termination is acceptable. Trace widths must be 5 mm or greater to reduce skin-effect losses and should reference the ground layer with no split plane crossings. Signal traces should not run more than 8 in on the host or the mezzanine card. The purposes of these specifications are to promote signal integrity. Traces should be simulated if they are designed to run faster than 1 Gbit/s.

Ideally, the FPGA should be capable of providing 50-Ohm output impedances for its driving signal. Bi-directional capabilities must be available on all CMOS class pins. When connected to the HSMC port, the mezzanine card’s load should cause the host processor to light indicate a proper mechanical connection via a PSTn LED. Voltage and current specifications must be met [13]. Traces containing the LVDS or CMOS signals should be closer to their reference plane than they are to each other and should meet specific length requirements.

Figure—2.2b: Cut out underneath Surface Mount Device (SMD) pads

Limited cross-talk is allowed (10% of the signal swing). For example, a 3.3V source should not result in a swing greater than 330mV in any other data line. To ensure this, parallelism rules must be followed during the design phase. The documentation also specifies the recommended wire relative distances for parallel traces that minimizes cross talk to a safe threshold. The host processor must provide the mezzanine card with 1 Amp for 12 V lines and 2 Amps for 3.3 V lines. The complete HSMC is allotted (at a minimum 18.6 W). Cabling within specification is available.

Impedance fluctuation should be closely considered [13]—one technique that is used to adjust the impedance at the connector pads is executed by making cut outs on the plane of the layer just below the SMT pad. Sample pad structure is provided in Fig. 2.2b.




CoaXPress FMC Schematic

Figure—2.3a: Here is presented a rough schematic of the rough schematic of the transceiver interface used for CXP [27]. The interface is presented in two layers, a schematic-wise layout

block (top) and a higher level block layout (bottom).

Mechanical Implications

Due to EMI effects, it may be advisable to shield the complete CXP data reading mezzanine card or the complete system (the host, paired with the HSMC). Furthermore, heat dissipation becomes a more significant challenge, because heat has a negative impact on signal integrity. In the event that the system becomes too hot, the CXP interface may fail. Heat generation is primarily a concern that arises from the design of the host system and the environmental temperature ranges. As for other mechanical concerns, they go beyond the scope of this document.

Note: there may be a tradeoff between shielding the system more effectively and temperature effects.




Bill of Materials

This section contains a list of necessary parts with estimated costs listed as well. Parts that are not necessarily implemented in both designs have been presented. Furthermore, optional components are presented as well.

Part # Part Name Quantity Distributor Unit CostASP-122952-01 HSMC Connector 1x SamTec0805 Resistors 0805 Resistor Unknown Mouser/Bourns

0805 Capacitors 0805 Capacitor Unknown Mouser/BournsLG R971-KN-1 0805 LED ~8x OSRAM Opto Semi $0.05

IL600 Optoisolator 4xGPIO Header 1x-2x

Amphenol 282121-75 DIN 1.0/2.3 Jack 4xPCB

Coaxial CableTPS3422EGDRYT Push Button 4x Texas Instruments

Table—2.1: Component materials listing. Note: lead-times (a very important variable) was not considered in this materials listing).

III. CoaXPress Firmware Layer

CoaXPress Communication Standard

CoaXPress is an asymmetric high-speed serial communication standard over a coaxial cable. This technology comes in several variants (CXP-1 through CXP-6). For this engineering design project CXP-6 is proposed as the desired serial communication interfacing standard.

The CXP receiver is capable of uplink transmission at a rate of 20.833 Mbit/s—this communication may be made as the transmitter is transmitting data. Data is separated using filtering techniques. Its primary application is video analytics. Most devices in this space are frame grabbers. There exists an FPGA IP core for this technology that is available through various vendors (namely S2I, Kaya Instruments, and Demand Creation).




Figure—3.1: Kaya Instruments FPGA CXP IP core [28].

Note: This section does not address the CoaXPress standard in more detail because the standard document was not available online during the time this document was written.

IV. Conclusion

The CXP SerDes interface is a robust interface capable of transmitting data at gigabit speeds. This SerDes interface is only a subsystem within the complete design. This system is anticipated to present considerable electrical and firmware design challenges, due to moderate complexity and unavailability of the CXP specification documentation. This subsystem is a major risk factor for the project. A design has been presented, which is expected to be capable of meeting the electrical-mechanical requirements. The software requirements are the main challenge. To overcome this, it is recommended that a preexisting core be used for the receiver.




References

[1] Reading eye diagrams. http://www.edn.com/design/test-and-measurement/4389368/Eye-

Diagram-Basics-Reading-and-applying-eye-diagrams

[2] Coaxial Cable Basics. https://www.youtube.com/watch?v=kOlQcv8AsWc

[3] TI SerDes presentation. https://www.youtube.com/watch?v=ozVMBcf6VmE

[4] High Speed Serial Data Transmission Integrated Circuits with Half-Rate Clock and Quarter-Rate

Clock in SiGe BiCMOS Technology. Young Uk Yim.

[5] Altera Transceiver Course. http://www.altera.com/education/training/courses/OSIIGX1115

[6] (Fundamentals of Phase Locked Loops, MT-086 Tutorial, Analog Devices).

[7] Wikipedia VCO. http://commons.wikimedia.org/wiki/File:VCO.jpg

[8] Transceiver Basics. http://www.altera.com/education/training/courses/OSIIGX1115

[9] WayTek Wires. http://www.waytekwire.com/products/1459/CAN-Bus-Cable/

[10] SamTec Connectors. http://www.samtec.com/standards/vita.aspx

[11] CoaXPress Website. http://www.coaxpress.com/coaxpress.php

[12] Kaya HSMC for CXP. http://www.kayainstruments.com/hsmc-coaxpress/

[13] HSMC Specification. http://www.altera.com/literature/ds/hsmc_spec.pdf

[14] Kaya FMC-CXP. http://www.kayainstruments.com/fmc-coaxpress/

[15] CoaXPress Presentation. http://www.youtube.com/watch?v=DehCJaHYLS8

[16] Cyton-CXP. http://www.bitflow.com/index.php/CytonCXP

[17] Microchip. http://www.microchip.com/DevelopmentTools/Listing.aspx?

CatID=70&CatText=CoaXPress+(CXP)

[18] Active Syilicon CXP products. http://www.activesilicon.com/products_interface-modules.htm

[19] Optoisolation. https://www.youtube.com/watch?v=6clEQecc4gU

[20] Optocouplers. https://www.youtube.com/watch?v=uRX0OwWjKXA

[21] BNC Connectors. http://www.regalusa.com/bnc_connectors.html#Space-Saver

[22] Coax BNC Connector Tutorial. https://www.youtube.com/watch?v=mtIi5ODxO20

[23] Matrox Frame Grabber.

http://www.matrox.com/imaging/en/products/frame_grabbers/radient_ev_cxp/

[24] Coaxial cable surge protection.

http://cdn1.globalmediapro.com/att/a/2/g/u/a2gun8/manual_sp002.pdf

[25] High-speed Optoisolation.

http://www.digikey.com/Web%20Export/Supplier%20Content/NVE_391/PDF/NVE_ab20.pdf?

redirected=1



http://www.digikey.com/Web%20Export/Supplier%20Content/NVE_391/PDF/NVE_ab20.pdf?redirected=1

http://www.digikey.com/Web%20Export/Supplier%20Content/NVE_391/PDF/NVE_ab20.pdf?redirected=1

http://cdn1.globalmediapro.com/att/a/2/g/u/a2gun8/manual_sp002.pdf

http://www.matrox.com/imaging/en/products/frame_grabbers/radient_ev_cxp/

https://www.youtube.com/watch?v=mtIi5ODxO20

http://www.regalusa.com/bnc_connectors.html#Space-Saver

https://www.youtube.com/watch?v=uRX0OwWjKXA

https://www.youtube.com/watch?v=6clEQecc4gU

http://www.activesilicon.com/products_interface-modules.htm

http://www.microchip.com/DevelopmentTools/Listing.aspx?CatID=70&CatText=CoaXPress+(CXP)

http://www.microchip.com/DevelopmentTools/Listing.aspx?CatID=70&CatText=CoaXPress+(CXP)

http://www.bitflow.com/index.php/CytonCXP

http://www.youtube.com/watch?v=DehCJaHYLS8

http://www.kayainstruments.com/fmc-coaxpress/

http://www.altera.com/literature/ds/hsmc_spec.pdf

http://www.kayainstruments.com/hsmc-coaxpress/

http://www.coaxpress.com/coaxpress.php

http://www.samtec.com/standards/vita.aspx

http://www.waytekwire.com/products/1459/CAN-Bus-Cable/

http://www.altera.com/education/training/courses/OSIIGX1115

http://commons.wikimedia.org/wiki/File:VCO.jpg

https://www.youtube.com/watch?v=kOlQcv8AsWc

http://www.edn.com/design/test-and-measurement/4389368/Eye-Diagram-Basics-Reading-and-applying-eye-diagrams

http://www.edn.com/design/test-and-measurement/4389368/Eye-Diagram-Basics-Reading-and-applying-eye-diagrams


[26] CoaxPress electrical characteristics. http://ww1.microchip.com/downloads/en/DeviceDoc/DS-

EQCO62R20.3-1v2.pdf

[27] CXP article. http://www.vision-systems.com/articles/print/volume-16/issue-1/features/

emerging-standards.html

[28] CXP IP Core example. http://www.kayainstruments.com/coaxpress-multi-link-multi-stream-fpga-

ip-core/

Notes:



http://www.kayainstruments.com/coaxpress-multi-link-multi-stream-fpga-ip-core/

http://www.kayainstruments.com/coaxpress-multi-link-multi-stream-fpga-ip-core/

http://www.vision-systems.com/articles/print/volume-16/issue-1/features/emerging-standards.html

http://www.vision-systems.com/articles/print/volume-16/issue-1/features/emerging-standards.html

http://ww1.microchip.com/downloads/en/DeviceDoc/DS-EQCO62R20.3-1v2.pdf

http://ww1.microchip.com/downloads/en/DeviceDoc/DS-EQCO62R20.3-1v2.pdf

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