ec&pdc lab manual.docx

ELECTRONIC CIRCUITS&PULSE AND DIGITAL CIRCUITS LAB MANUAL

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY,KAKINADAII Year B.Tech. ECE. II-Sem

ELECTRONIC CIRCUITS&PULSE AND DIGITAL CIRCUITS LAB

List of Experiments (Twelve Experiments to be Done):

I)Design and Simulation in Simulation Laboratory using Multisim OR Pspice OR Equivalent Simulation Software.&Verifying the result by Hardware(Any Six) 1.Common Emitte and Common Collector Amplifier-Freq.Response,Impedance Measurements 2.Two Stage RC Coupled Amplifier 3.Current Shunt and Voltage Shunt Feedback Amplifier-Freq.Response, Impedance Measurements(with and without feedback) 4.WienBridge Oscillator using Transistors-Design for different Frequencies 5.RC Phase Shift Oscillator using Transistors-Design for different Frequencies 6.Class A Power Amplifier 7.Class B Power Amplifier (Complimentary Symmetry ) 8.Single Tuned Voltage Amplifier 9.Series Voltage Regulator 10.Shunt Voltage Regulator

II) Pulse and Digital Circuits(Any Six)-By Designing the Circuits 1. Linear wave shaping. 2. Non Linear wave shaping – Clippers,Clampers. 3.Logic Gates with Discrete Components 4. Bistable Multivibrator 5. Astable Multivibrator. 6. Monostable Multivibrator. 7. Schmitt Trigger. 8. UJT Relaxation Oscillator. 9. Bootstrap sweep circuit10.Sampling Gates

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SIET/ECE/II BTECH-II SEM/EC&PDC LAB MANUAL


SoftwareExperiments

List of Experiments

1.Common Emitter and Common Collector Amplifier-Freq.Response,Impedance Measurements 2.Two Stage RC Coupled Amplifier 3.Current Shunt and Voltage Shunt Feedback Amplifier-Freq.Response, Impedance Measurements(with and without feedback) 4.WienBridge Oscillator using Transistors-Design for different Frequencies 5.RC Phase Shift Oscillator using Transistors-Design for different Frequencies 6.Class A Power Amplifier 7.Class B Power Amplifier (Complimentary Symmetry ) 8.Single Tuned Voltage Amplifier 9.Series Voltage Regulator 10.Shunt Voltage Regulator

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1. (a)SINGLE STAGE CE AMPLIFIERAIM:

To obtain the frequency response of single stage CE amplifier using Multisim

Software.

APPARATUS:

1. Regulated Power supply2. Capacitor (10 F) 3. Transistor (2N3904)4. Resistor (470 K, 2.2 K, 0.56 K)5. Signal Generator6. C.R.O

CIRCUIT DIAGRAM:

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THEORY:

An amplifier is an electronic circuit that is capable of increasing the level of the signal applied at its input, with the frequency same as that of the input.

When the transistor is biased in active region it acts like an amplifier. An ac voltage is applied between the base and emitter to produce corresponding collector current. As the transistor is connected in common emitter configuration it is known as CE amplifier. An amplified output signal with a phase shift of 1800 is obtained when this fluctuating collector current flow through a collector resistor Rc. Resistor Re stabilizes Q-point against temperature variations.

TABULAR FORM : FREQUENCY INPUT VOLTAGE OUTPUT

VOLTAGEGAIN= 20 LOG

V0/VI

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using multisim software.2. After connecting the circuit of the amplifier go for simulation settings and set the

analysis type as Ac sweep/noise, start frequency, end frequency, points/decade.3. Place the markers.4. Simulate the circuit and observe the output.

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5. Calculate the gain using the formula 20log (Vo/Vi).6. Set the lower & higher cutoff frequencies and calculate the bandwidth.

MODEL GRAPH :

PRECAUTIONS:

1. Connect the circuit without errors.2. Use the components with proper values.3. Ground the circuit properly.

RESULT:

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1.(b) COMMON COLLECTOR AMPLIFIER

AIM: To observe the operation of common collector amplifier.

APPARATUS:

Components:

Transistor (BC107) - 1No.

Resistors (68k) - 1No.

(33k) - 1No

(10k) - 2No

(4.7k) - 1No

Capacitors (10F) - 1No.

Sources: Vac source - 1No.

Vdc source - 1No.

Ground: (0) source ground - 2Nos.

CIRCUIT DIAGRAM:

THEORY:

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Figure shows the circuit of a single stage cc amplifier using a npn transistor. The emitter base junction is forward biased by power supply VEE and collector base junction is reverse biased by Vcc so that the transistor remains in the active region throughout its operation.

Input signal is given to the base collector circuit and output signal is taken from the emitter collector circuit. As the output signal taken at the emitter terminal almost follows the input signal, the cc amplifier is called as the emitter follower.

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using p-spice software.2. After connecting the circuit of the amplifier, go for simulation settings and set the

analysis type as AC sweep/noise etc.3. Place the markers.4. Simulate the circuit and observe the output.

MODEL GRAPH:

PRECAUTIONS:


RESULT:

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2. TWO STAGE RC COUPLED AMPLIFIER

AIM:

1. To study the Two-Stage RC coupled amplifier.

2. To measure the voltage gains of the amplifier at 1KHz.

3. To obtain the frequency response characteristics and the bandwidth

APPARATUS:

1. Transistors (2N3304)

2. Resistors (15 K, 2.2 K, 4.7 K)

3. Capacitors (20 F,10 F )

4. Function generator (10 to10MHz)

5. Transistorised power supply (0 to30V)

6. Cathode Ray Oscilloscope (0 to 30MHz)

CIRCUIT DIAGRAM:

THEORY:

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In most of the cases the amplification is not sufficient by the single stage amplifier. Hence two or more stages are connected to get required gain through some type of coupling networks, this type of connecting the output of one stage to the input of the next stage in known as cascading. Some times cascading also done for achieving the input and output impedance for specific application. In this circuit the output of the first stage is connected to the input of the next stage through resistor Rc and coupling capacitor Cc. Hence it is called RC coupled amplifier. The voltage source Vs is fed to the input through source resistance Rs and the output of second stage is fed to load resistance RL. By keeping the input voltage (Vi) constant, varying the input frequency from 10Hz to 10MHz and calculate output voltage (Vo). Then calculate the overall voltage gain Vo / Vi and plot the graph.

TABULAR FORM :

FREQUENCY INPUT VOLTAGE OUTPUT VOLTAGE

GAIN= 20 LOG V0/VI

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using multisim software.

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2. After connecting the circuit of the amplifier goes for simulation settings and set the analysis type as AC sweep/noise, start frequency, end frequency, points/decade.

3. Place the markers.4. Simulate the circuit and observe the output.5. Calculate the gain using the formula 20log (Vo/Vi).6. Set the lower &higher cutoff frequency and calculate the bandwidth.

MODEL GRAPH:

RESULT:

Thus the RC coupled amplifier is verified its gain at different frequencies

and plot the graph.

Maximum gain of the amplifier =

Band width =

10


FREQUENCY (Hz)

GAI

N (d

B)

BAND

WIDTH


3. CURRENT SHUNT FEEDBACK AMPLIFIER

AIM: To obtain the frequency response of current shunt feedback amplifier using

Multisim software.

APPARATUS:

Components:

Transistor (Q2N2222) - 2Nos.

Resistors (1k) - 2Nos.

(1.2k) - 1No.

(10k) - 1No.

(100k) - 1No.

Sources:

Vac source - 1No.

Vdc source - 1No.

Ground: (0) source ground - 1No.

CIRCUIT DIAGRAM:

THEORY:11



Feedback means applying a part of the output signal of the transistor amplifier to its input. Depending of the signal feedback, these are two types:

1.positive feedback 2.negative feedback

One of the negative feedback amplifiers is current shunt feedback amplifier. A two-stage transistor CE amplifier with feedback from the second transistor emitter to the first transistor base through the feedback resistor Rf.

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using p-spice software.2. After connecting the circuit of the amplifier, go for simulation settings and set the

analysis type as AC sweep/noise, start frequency, end frequency, points/decade.3. Place the markers.4. Simulate the circuit and observe the output.5. Calculate the gain using the formula 20log (Vo/Vi).6. Set the lower &higher cutoff frequency and calculate the bandwidth.

MODEL GRAPH:

PRECAUTIONS:


RESULT:

4.WEIN BRIDGE OSCILLATOR

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AIM:

To study and calculate the theoretical and practical output frequencies of wein bridge oscillator using Multisim software.

APPARATUS:

Transistor (Q2N 2222) - 2Nos.

Resistors (10K,220,4.7k,56) - 1No.

(47K) - 2Nos.

(56,1.5k,1k) - 1No.

(100K) - 1No.

Capacitors (0.01F) - 3Nos.

(0.1uF) - 1No.

Vdc source - 1No.

CIRCUIT DIAGRAM:

THEORY:

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The wein bridge oscillator is the standard oscillator circuit for all low frequencies I the range of 10Hz to about 1MHz. It is most frequently used type of audio oscillator as the output is free from circuit fluctuations and ambient temperature.

It is essentially a two-stage amplifier with R-C bridge circuit. The bridge circuit has the arms R1C1,R2C2,R3. Resistance R3 is used to stabilize the amplitude of the output. The transistor Q1 serves as an oscillator and amplifier while the other transistor Q2 serves as an inverter (to produce phase shift of 1800 ). The circuit uses positive and negative feedbacks. The positive feedback is through R1C1,R2C2 to the transistor Q1. The negative feedback is through the voltage divider to the input of the transistor Q2.

The frequency of oscillations is determined by the series element R1C1 and parallel element R2C2 of the bridge.

f = 12Π √ R1 C1 R2 C2 Where R1=R2=R, C1=C2=C then

f = 12 Π RC

MODEL GRAPH:

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using p-spice software.

2. After connecting the circuit of the amplifier, go for simulation settings and set the analysis type as time domain (transient), run to time, maximum step size etc.

3. Place the markers.

4. Simulate the circuit and observe the output.

5. Set the minimum and maximum points of the waves.

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THEORETICAL CALCULATIONS:

f = 12Π √ R1 C1 R2 C2

PRACTICAL CALCULATIONS:

f=1/T

Where T= time period of waveform observed in CRO

PRECAUTIONS:

1. Connect the circuit without errors.

2. Use the components with proper values.

3. Ground the circuit properly.

RESULT:

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5.RC PHASE SHIFT OSCILLATOR

AIM:

To observe the operation of RC phase shift oscillator using Multisim software.

APPARATUS:

1. Regulated Power Supply

2. Transistor (2N2222A)

3. Resistors ( 1.5 K, 9.2 K, 920 K)

4. Capacitors (0.02 F)

5. C.R.O

CIRCUIT DIAGRAM:

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THEORY:

RC phase shift oscillators used for very low frequency. In a phase shift oscillator, a

phase shift of 1800 is obtained with a phase shift circuit instead of inductive or capacitive

coupling. A further phase shift of 1800 is introduced due to transistor properties. RC phase

shift oscillators have three sections of RC networks. Each section produces a phase shift of

1800 is produced. The total phase shift of entire loop is 3600 i.e. the feedback voltage is in

phase with input. The gain of the amplifier section it should be slightly more than 29.

f 0=12 π RC √6+4 K

where K=RC

R;

R=R1=R2=R3 ; C=C1=C2=C3 ;

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using multisim software.

2. After connecting the circuit of the amplifier, go for simulation settings and set the

analysis type as time domain (transient), run to time, maximum step size etc.

3. Place the markers.

4. Simulate the circuit and observe the output.

5. Set the minimum and maximum points of the waves.

OBSERVATIONS:

Theoretical Calculation :

f = 12π RC √6+4 K Where K = Rc/R

Practical Calculation :

f = 1T Where T= time period

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MODEL GRAPH :

PRECAUTIONS:

1. Connect the circuit without errors.

2. Use the components with proper values.

3. Ground the circuit properly.

RESULT:

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6.CLASS A POWER AMPLIFIERAIM:

To observe the operation of class A power amplifier using multisim software.

APPARATUS:

1. NPN Transistor (2N3904)

2. Function generator (1 to 10MHz)

3. C.R.O (0to 30MHz)

4. Power Supplies

5. Resistor (1K, 20)

6. Capacitor (100 F)

CIRCUIT DIAGRAM:

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THEORY:

The power amplifier is said to be class A amplifier if the Q-point and the input signal are selected such that the output signal is obtained for full input cycle. For this class position of the Q-point is approximately at the mid point of the load line.

For all the values of input signal, the transistor remains in the active region and never enters into cut-off or saturation region. When an ac signal is applied, the collector current flows for 3600 (full cycle) of the input signal. In other words, the angle of the collector current flow is 3600 i.e. one full cycle.

PROCEDURE:

1. Connect the circuit as per the circuit diagram on computer using multisim software.2. After connecting the circuit of the amplifier, go for simulation settings and set the

analysis type as time domain (transient), run to time, maximum step size etc.3. Place the markers.4. Simulate the circuit and observe the output.5. Observe whether the waveforms are out of phase or not.6. Set the minimum and maximum points of the waves.

MODEL GRAPH:

PRECAUTIONS:


RESULT:

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7.CLASS B POWER AMPLIFIER (COMPLEMENTARY SYMMETRY)

AIM:

1. To observe the operation of a complementary symmetry amplifier.

2. To measure the dc bias current, and waveforms in this amplifier.

APPARATUS:

1. NPN Transistor (Virtual)

2. Function generator (1 to 10MHz)

3. C.R.O (0to 30MHz)

4. Power Supplies

5. Resistor (10)

6. PNP Transistor (Virtual)

CIRCUIT DIAGRAM :

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THEORY:

The complementary symmetry circuit uses two transistors with identical characteristics. However, one transistor is a PNP and other one is NPN.

Q1 is a NPN & Q2 is a PNP transistor, each connected as an emitter follower, with the emitters connected together. The collector of Q1 goes to +Vcc, a positive supply. The bases of Q1 and Q2, connected together, receive the input signal from some external circuit. When sine wave is applied to the input of the amplifier, during the positive alternation the base of Q1 is driven positive relative to its emitter, turning on Q1, the NPN transistor. Q1 remains on during this Positive alternation. During the positive alternation, Q2, a PNP transistor, remains reverse-biased and is cut-off. During the negative alternation, Q2 is forward biased by the signal and turns on while Q1 is cut-off. The circuit shows that current in Q2 is opposite in direction to current inQ1. This is because Q1 is an NPN, Q2 is a PNP transistor. The voltage developed at the output terminals is a sine wave, like the input. Since the Q1 & Q2 complement each other and the circuit is symmetrical. This arrangement is called complementary symmetry. Complementary circuits can be common emitter as well as common collector, and they may be operated class ‘A’ as well as class ’B’.

Complementary-symmetry amplifiers require very careful design to prevent thermal runway and destruction of the power transistors. Unbalance or leakage in power transistors can cause multiple failures. Diode stabilization is frequently employed as thermal compensation. These conditions are mainly found in direct coupling from driver to output stages.

TABULARFORM:

INPUT FREQUENCY

INPUT VOLTAGE

OUTPUT

VOLTAGE

Vo/Vi GAIN=20LOG

V0/Vi

PRODEDURE:

1. Connect the circuit as per the circuit diagram on computer using multism software.2. After connecting the circuit of the amplifier, go for simulation settings and set the

analysis type as time domain (transient), run to time, maximum step size etc.

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3. Place the markers.4. Simulate the circuit and observe the output.5. Observe whether the waveforms are out of phase or not.6. Set the minimum and maximum points of the waves.

MODEL GRAPH:

MODEL WAVEFORMS:

RESULT:

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8.SINGLE TUNED AMPLIFIER

AIM: To observe the operation of single tuned amplifier using Multisim.

APPARATUS:

Transistor (Q2N2222) - 1No.

Resistors (4.7k) - 1No.

Capacitors (0.1F) - 1No.

(0.01F) - 1No.

(0.047F) - 1No.

Function generator - 1No.

CRO - 1No.

RPS - 1No.

CIRCUIT DIAGRAM:

Q2N2222CRO

L

1

2

4.7k

+12V

0.047u

10V ac

0.01u

C0.1u

VCC

THEORY:

An amplifier is said to be class C amplifier, if the Q-point and the input signal are selected such that the output signal is obtained for less then a half cycle, for a full input cycle.

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Due to such a selection of the Q-point, transistor remains active, for less than half cycle. Hence only that much part is reproduced at the output. For remaining cycle of the input cycle, the transistor remains cut-off and no signal is produced at the output.

Signal tuned amplifier circuit used one parallel tuned circuit as a load. The tuned circuit formed by L & C acts as collector load and resonates at frequency of operation. A parallel tuned circuit acting as load impedance is tuned to the input frequency. Therefore, it filters the harmonic frequencies and produce a sine wave output voltage consisting of fundamental component of the signal.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.2. After connecting the circuit of the amplifier apply an input voltage of 10V.3. Now by varying the function generator measure the o/p voltage.4. Find the maximum value of frequency (fi) at which the gain is maximum.5. Tabulate all the values and calculate the gain using the formula

Gain (dB)=20log(Vo/Vi)

6. Draw the graph between (fi) and (A) and mark the resonant frequency (fo).

OBSERVATIONS:

S.No Vin Freq (Hz) Vo Gain (dB)

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MODEL GRAPH:

PRECAUTIONS:

1. Connect the circuit without any loose connections.2. Take readings without parallax error.3. Verify the circuit before switch ON the supply.

RESULT:

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9. SERIES VOLTAGE REGULATOR

AIM: To observe the regulated output series voltage regulator using Multisim.

APPARATUS:

Transistor (Q2N 2222) - 1No.

Zener diode (IMZ9) - 1No.

Resistors (1k) - 2Nos.

RPS - 1No.

Digital Multimeter - 1No.

CIRCUIT DIAGRAM:

THEORY:

The heart of any voltage regulator circuit is a control element. If such a control element is connected in series with the load, the regulator is called series voltage regulator. Here the controlling element regulates the load voltage, based on control signal is in series with the load and hence the circuit is called series voltage regulator circuit. The entire current through the control element and hence control element is high current, low voltage rating component.

PROCEDURE:

1. Connect the circuit as per the circuit diagram. 2. After connecting the circuit apply an input voltage through RPS.3. Now by varying the RPS measure the o/p voltage in DMM.

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4. Tabulate all the readings and draw the graph between i/p voltage and o/p voltage.OBSERVATIONS:

S.No Vin Vo

MODEL GRAPH:

PRECAUTIONS:


RESULT:

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10. SHUNT VOLTAGE REGULATOR

AIM: To observe the regulated output shunt voltage regulator.

APPARATUS:

Transistor (Q2N3904) - 1No.

Zener diode (IMZ9) - 1No.

Resistors (1k) - 1No.

(100k) - 1No.

RPS - 1No.

Digital Multimeter - 1No.CIRCUIT DIAGRAM:

THEORY:

The heart of any voltage regulator circuit is a control element. If such a control element is connected in shunt with the load, the regulator is called shunt voltage regulator. the controlling element maintains the constant output voltage by shunting the current; hence the regulator circuit is called shunt voltage regulator circuit. The controlling element is low current, high voltage rating component.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

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2. After connecting the circuit apply an input voltage through RPS.3. Now by varying the RPS measure the o/p voltage in DMM.4. Tabulate all the readings and draw the graph between i/p voltage and o/p voltage.

OBSERVATIONS:

S.No Vin Vo

MODEL GRAPH:

PRECAUTIONS:


RESULT:

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Hardware Experiments

List of Experiments

II) Pulse and Digital Circuits(Any Six)-By Designing the Circuits 1. Linear wave shaping. 2. Non Linear wave shaping – Clippers,Clampers. 3.Logic Gates with Discrete Components 4. Bistable Multivibrator 5. Astable Multivibrator. 6. Monostable Multivibrator. 7. Schmitt Trigger. 8. UJT Relaxation Oscillator. 9. Bootstrap sweep circuit10.Sampling Gates

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1.LINEAR WAVE SHAPING

AIM: To verify the behavior of a RC high pass and low pass filters where input is square waveform and to calculate percentage of tilt and rise time.

APPARATUS:

1. Resistors [1K,10K,100K ohms] 1 No2. Capacitor[0.1µF] 1 No3. Signal Generator 1 No4. C.R.O. 1 No5. Bread Board 1 No6. Connecting wires

THEORY: A square wave is a periodic waveform which maintains itself at one constant level V1

with respect to ground for a time T1 and then changes abruptly to another level V11 and remains constant at that level for a time T2 and repeats itself at regular intervals T = T1 + T2. The shape of a square wave output depends upon the time constant of the circuit. If the time constant is very small the rise time will also be small and a reasonable reproduction of input may be obtained.

For the input square wave the output waveform will be preserved if the time constant RC of the circuit is small compared to the period of the input waveform. If the time constant is comparable to the time period of the input square wave the output rises and falls exponentially. If the time constant is very large compared to the period of input waveform the output consists of several exponential sections which are essentially linear. Since the average across R is zero, the dc voltage at the output is same at that of input.

CIRCUITDIAGRAM:

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MODEL GRAPHS:

PROCEDURE:

1. Connections should be made as per circuit diagram.2. Switch on the supply for the signal generator to generate square waveform.3. Vary the frequency as per required and observe.4. Calculate the percentage tilt and rise time.

PRECAUTIONS:

1. Connections should be tight.

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2. Readings should be taken without any parallax error.

OBSERVATIIONS:

FOR LOW PASS FILTER:

Frequency Practical Time Period

Amplitude Practical Rise Time Theoretical Rise Time

100 Hz

1 K Hz

10 K Hz

2.2 R x C

Input Amplitude = 10 V

Theoretical Rise time = 2.2 R x C =

Practical Rise Time [tr] = t2 – t1 =

FOR HIGH PASS FILTER:

Frequency Practical Time Period

Amplitude Practical % tilt at (1Khz)

Theoretical % tilt

100 Hz

1 K Hz

10 K Hz

[V1 – V11 / (V/2)] X 100 X 100

Input Amplitude = 10 V

Theoretical % tilt = [T / 2 R x C] X 100 =

Practical % tilt = [V1 – V11 / (V/2)] X 100 =

RESULT:

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2a). NON LINEAR WAVE SHAPING–CLIPPERS

AIM: To observe output wave form of a clipping circuits for a sinusoidal input signal.

APPARATUS:

1. Diodes [IN 4007] 2 Nos2. Resistor [10KΩ] 1 No3. Regulated Power Supply [0 – 30 V] 1 No4. Signal Generator 1 No5. C.R.O. 1 No6. Bread Board 1 No7. Connecting wires

THEORY:

Clippers are used to reduce the amplitude upto a reference voltage. These are used to construct clipping circuits. These circuits are used to select for transmission that part of an arbitrary waveform which lies above or below some particular reference voltage. Clippers are different from attenuators by the fact that in clippers the actual input wave shape is changed at the output end by clipping a part of the wave. Clipping circuits are also referred to as slicers, voltage or current limiters or amplitude selector.

Limiting circuits usually fall into one of the following configuration.

1. Series combination of diode, resistor and reference supply.2. Network consisting of several diodes, resistors and reference voltage.3. Two emitter coupled and cathode coupled triode operating as an over driver

difference amplifier.

The five types of configurations of clippers on we experiment are.1. Series clipper clipping above VR.2. Series clipper clipping below VR.3. Shunt clipper clipping above VR.4. Shunt clipper clipping below VR.5. Two level clipper.

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CIRCUIT DIAGRAM:

36



MODEL GRAPHS:

PROCEDURE:

1. Connections should be done as per circuit diagram.2. Switch on the signal generator and give sinusoidal input wave form.3. Note down the time – period and amplitude of sinusoidal signal input wave form.4. Observe the output wave form in the C.R.O.

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5. Note down the time – period and clipping levels.

PRECAUTIONS:

1. Connections should be tight.2. Readings should be taken without any parallax error.

OBSERVATIIONS:

Input Amplitude =10 V1) Shunt Clippers Clipping Above VR : -

Time Period = _____Output Signal Amplitude = _____

2) Shunt Clippers Clipping Below VR : - Time Period = ______Output Signal Amplitude = ______

3) Series Clippers Clipping Above VR : - Time Period = _______Output Signal Amplitude = _______Series Clippers Clipping Below VR: - Time Period = _______Output Signal Amplitude = _______

4) Two Level Clippers : - Time Period = _______Output Signal Amplitude = _______

RESULTS:

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2b). NON LINEAR WAVE SHAPING – CLAMPERS

AIM: To observe the output waveforms of a clamper circuit when the input is sinusoidal

signal.

APPARATUS: 1. Diodes [IN 4007] 2 Nos2. Capacitor[0.1µF] 1 No3. Resistor [10KΩ] 1 No4. Regulated Power Supply [0 – 30 V] 1 No5. Signal Generator 1 No6. C.R.O. 1 No7. Bread Board 1 No8. Connecting wires

THEORY:

When a signal is transmitted through a capacitive coupling network (RC high pass circuit), it loss its d.c component but a clamper circuit may be used to introduce dc component by fixing positive or negative extremity of that waveform to some reference level for this reason, the clamping circuit is often referred to as dc restore or dc reinserted.

The clamping circuit only changes the dc level of input signal. It does not affect its shape. Clamping circuits may be positive charge voltage clamping circuits or negative voltage clamping circuits. In positive clamping the negative extremity of the waveform is fixed at one level and the entire waveform appears above the reference level.i.e. the output wave is positively clamped with reference to reference level. Where as in negative clamping the output waveform is negatively charged with reference to reference level. The capacitor are essential in clamping circuits is that while clipper cuts off an unwanted portion of the input wave the clamper simply clamps the maximum positive or negative peak of the waveform to a desired level.

CIRCUIT DIAGRAM:

39



MODEL GRAPHS:

PROCEDURE:1. Connections should be done as per circuit diagram.2. Switch on the signal generator and give sinusoidal input wave form.3. Observe the output wave form in the C.R.O.

PRECAUTIONS:1. Connections should be tight.2. Readings should be taken without any parallax error.

OBSERVATIIONS:Input Wave form: -

Amplitude =10 VOutput wave form: -

Positive Amplitude = ________ VoltsNegative Amplitude= ________ Volts Time Period = _________m sec

RESULT:

40



3.LOGIC GATES WITH DESCRETE COMPONENTS

AIM: To realize logic gates using transistor and diodes [or] to construct two input AND,

OR, NOT, NOR, NAND and to obtain the truth tables.

APPARATUS:

1. Transistors [BC 107] 2 Nos2. Resistors [1 KΩ] 4 No’s3. Diodes [IN 4007] 2 No’s4. R.P.S [Regulated power Supply (0 – 30 V)] 1 No5. LED or Digital Multimeter 1 No6. Bread Board 1 No7. Connecting Wires

THEORY:

In a binary logic system a bit is implemented as one of the two voltages levels. The more positive voltage is the 1 level and the other is 0 level, the system is said to employ positive logic. In negative logic the more negative voltage is 1 level and the other is 0 level. The absolute values of the two voltages are of on significance.

In pulse logic systems a bit is recognized by the presence or absence of a pulse. A 1 signifies existence of a positive pulse in a pulse positive logic system. A negative pulse denotes a 1 is pulse negative logic system. In either system a 0 at a particular input or output at a given instant of time designates that no pulse is presents. Logic circuits are those which implement a function for a given set of inputs A and B .

The output of an OR assumes 1 state if any one or both of inputs assume 1 state. In general if A and B are inputs, then output is A + B.

The output of an AND assumes 1 state if and only if all the inputs assume 1 state. The output is A.B .

The output of a NOT circuit takes on 1 state if and only if the input does not take 1

state. The output is

The negation before an AND gate is called NAND gate. The output is

The negation before an OR gate is called NOR gate. The output is

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CIRCUIT DIAGRAM:

PROCEDURE:1. Connection for each gate is made as per circuit diagram.2. Switch on the power supply and give required voltage.3. 1 and 0 levels correspond to 5 V and 0 V inputs respectively.4. The truth tables for each gate are verified.

PRECAUTIONS:1. Connections should be made tightly.2. Before switch on the power supply [DC] we should keep the current knob in

maximum position and voltage knob in minimum position.RESULTS:

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4.BISTABLE MULTIVIBRATOR

AIM: To design a Bi – stable Multivibrator and observe the output wave forms.

APPARATUS:

1. Transistors [NPN] [CL 100] 2 Nos2. Resistors [2.2 KΩ] 1 No3. Resistors [15 KΩ] 2 Nos4. Resistors [100 KΩ] 3 Nos5. Diode [1 N 4007] 1 No6. Capacitors [104 pf] 1 No7. Regulated Power Supply [0 – 30 V] 1 No8. C.R.O. 1No9. Bread Board 1 No10. Connecting Wires

THEORY:

A Bistable multivibrator is one which exists indefinitely in either of the two stable states and which can be induced to make an abrupt transition from one state to the other by the means of external excitation. A bistable multivibration is used for the performance of many digital operations such as counting and storing of binary information and also in the generation and processing of pulse waveform. Because of symmetry of Bistable multivibrator circuit the quiescent currents in each amplifier are the same.

The loop gain for this circuit is grater than unity let one of the transistor say Q2 be ON. The base current which comes from the collector of Q1 to be in the ON state and Q2

remains in OFF state. This situation remains until triggering is applied to the circuit to change the states where Q2 is ON and Q1 is OFF. This remains until another triggering is applied. So this is also called flip – flop circuit since the states are altered between the two transistors.

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CIRCUIT DIAGRAM:

MODEL GRAPH:

44



PROCEDURE:1. Connections should be done as per the circuit diagram.2. A dc voltage of 12 V is applied to the circuit.3. The waveform and the dc voltage levels at the base and collector of the two transistors

are noted.4. Now triggering is applied to the circuit.5. The waveform at the output of the trigger circuit is checked in the CRO for a square

wave input before triggering is applied.6. The waveforms and dc voltage levels at the base and collector of the two transistors

are gain noted.7. Graphs are plotted for the observations made.

PRECAUTIONS:1. Connections must be tight.2. Readings are taken without parallax error.

OBSERVATIONS:Before Triggering After Triggering

VB1 =

VB2 =

VC1 =

VC2 =

VB1 =

VB2 =

VC1 =

VC2 =

RESULT:

45



5.ASTABLE MULTIVIBRATORAIM:

To design an Astable Multivibrator and observe the output wave forms.

APPARATUS:

1. Transistors [NPN] [CL 100] 2 Nos2. Resistors [22 KΩ and 470Ω] 2 Nos3. Capacitors [104 pf] 2 Nos4. Regulated Power Supply [0 – 30 V] 1 No5. C.R.O. 1No6. Bread Board 1 No7. Connecting Wires

THEORY: The Astable multivibrator has two states, both of which are quasi – stable. Without

the aid of an external triggering signal the Astable multivibrator will make successive transistors from one quasi stable state to the other. Astable multivibrator has extensive applications in pulse circuits. The Astable circuit is an oscillator and is used as a generator of square waves and since it requires no triggering signal, is itself often a basic source of fast waveforms. Since the multivibrator generates square wave generator or square wave oscillator or relaxation oscillator or non sinusoidal oscillator.

CIRCUIT DIAGRAM:

MODEL GRAPHS:46



PROCEDURE:1. Connections should be done as per the circuit diagram.2. Switch on the power supply and give required voltage.3. Observe the wave form at the base and collector of the two transistors.4. Note down the values of amplitude and time period.5. The graphs are plotted.6. The waves are drawn to scale.

PRECAUTIONS:1. Connections should be done as per the circuit diagram.2. Readings should be taken with out parallax error.3. Before switch on DC supply are should keep the current knob in maximum position

and voltage knob is minimum position.

RESULT:

47



6.MONOSTABLE MULTIVIBRATOR

AIM: To design a Monostable Multivibrator and observe the output wave forms.

APPARATUS:

1. Transistors [NPN] [CL 100] 2 Nos2. Resistors [22 KΩ] 1 No3. Resistors [1 KΩ] 2 Nos4. Resistors [10 KΩ] 3 Nos5. Diode [1 N 4007] 1 No6. Capacitors [104 pf] 2 Nos7. Regulated Power Supply [0 – 30 V] 1 No8. C.R.O. 1No9. Bread Board 1 No10. Connecting Wires

THEORY:

A Monostable multivibrator is one which has only one permanently stable and one quasi – stable. In Monostable multivibrator a triggering signal is required to induce a transition from the stable to the quasi stable state. The Monostable multivibrator may remain in its quasi stable state for a time which is very long in comparison with the time of transition between the states. Eventually, however, it will return from the quasi stable state to its stable on external signal being required to induce this reverse transition.

Since when it is triggering the circuit returns to its original state by itself after a time T, monostable multivibrator is known as a one shot or a univibrator. Since it generates a rectangular waveform and hence can be used to gate other circuits it is also called a gating circuit. Further more since T, after the input trigger, it is also referred as a decay circuit.

48



CIRCUIT DIAGRAM:

MODEL GRAPHS:

49



MODEL WAVEFORMS

PROCEDURE:

1. Connections should be done as per the circuit diagram.2. A dc voltage of 12 V is applied to the circuit.

50



3. The wave forms and dc voltage levels at the base and collector of the two transistors are noted.

4. The triggering circuit is connected and the waveform at the output is checked in the for a square wave input.

5. Now triggering is applied to the circuit.6. The waveforms and dc voltage levels at the base and collector of the two transistors

are again noted.7. graphs are plotted for the observations made.

OBSERVATIONS:

After TriggeringVB1 =» VB1 [Sat] = 0.7 V VB1 [Cut – off] = 0.6 V VB2 =» VB2 [Sat] = 0.7 V VCC – VBE [Sat] = 11 V Over Shoot δ = 0.2 V VC1 =» VCC = 11 V, VC1 [Sat] = 0.3 V VC2 =» VCC = 11 V, VC2 [Sat] = 0.7 V

PRECAUTIONS:

1. Connections should be done as per the circuit diagram.2. Readings should be taken with out parallax error.3. Before switch on DC supply are should keep the current knob in maximum position


RESULT:

51



7.SCHMITT TRIGGER

AIM:

To measure the LTP and UTP of a given Schmitt Trigger and to observe the output wave form.

APPARATUS:

1. Transistors [NPN] [BC 107] 2 Nos2. Resistors [1 KΩ] 2 Nos3. Resistors [2.2 KΩ] 1 No4. Resistors [4.7 KΩ] 1 No5. Resistors [5.6 KΩ] 1 No6. Resistors [3.3 KΩ] 1 No7. Diode [1 N 4007] 1 No8. Capacitors [0.1 µf] 1 No9. Function Generator 1 No10. C.R.O. 1No11. Bread Board 1 No12. Connecting Wires

THEORY:

Schmitt trigger is a special type of Bistable multivibrator which has several important practical applications. It is moved named after is inverter. It differs from the basic binary circuit in that the resistive coupling between the output Q2 and the input of Q2 of the basic circuit is missing. It exhibits Hysterisis property shown in figure . Additionally Schmitt trigger is a emitter coupled binary.

The output of the Schmitt trigger is a square waveform whatever the input waveform be so it is called a squaring circuit. The arbitrary waveform applied must have its amplitude greater than the UTP value of the Schmitt trigger. It is also used as amplitude comparator.

52



CIRCUIT DIAGRAM:

MODEL GRAPHS:

53



PROCEDURE:

1. Connections should be done as per the circuit diagram.2. Switch on the power supply and give required voltage.3. Switch on signal generator and give sinusoidal input wave form.4. Note down the time period and amplitude of sinusoidal input wave form.5. Observe the output wave form on CRO note down the time period and amplitude of

the output wave form.6. Note down the LTP [Lower Triggering Point] and UTP [Upper Triggering Point]

values.7. Draw the Hysterisis curve.8. And draw the output wave form.

CALCULATIONS:Input Amplitude = 10 VTime Period =Output Amplitude =

Time Period =Hysteresis Voltage VH = UPT – LTP UTP – LTP –

PRECAUTIONS:1. Connections should be done as per the circuit diagram.2. Readings should be taken with out parallax error.

RESULT:

54



8.UJT RELAXATION OSCILLATOR

AIM: To observe an output wave form of UJT Relaxation Oscillator and to calculate the

frequency of Oscillator.

APPARATUS:1. UJT [2 N 2646] 1 No2. Resistors [1 KΩ] 2 Nos3. Resistors [33 KΩ] 1 No4. Resistors [470 Ω] 1 No5. Capacitors [0.1 µf] 1 No6. Regulated Power Supply [0 – 30 V] 1 No7. C.R.O. 1No8. Bread Board 1 No9. Connecting Wires

THEORY:

A UJT sweep generator is also called relaxation oscillator. A relaxation oscillator is a circuit which generates non sinusoidal oscillation. From the operation UJT is OFF as long as emitter voltage VE < VP [peak voltage]. Hence initially UJT is OFF. The capacitor charges through the resistor R from the supply voltage. When the capacitor voltage VS rises to the value VV . Now the UJT becomes OFF and the capacitor again starts to charge to VP. This process continues endlessly.

CIRCUIT DIAGRAM

:

55



MODEL GRAPHS:

PROCEDURE:

1. Connections should be done as per the circuit diagram.2. Switch on the power supply and give required voltage.3. Observe the output wave form on CRO note down the time period and amplitude of

the output wave form.4. And also note down the VP [Peak Voltage] VC [Valley Voltage].

OBSERVATIONS:

VP =VV =Time Period =

CALCULATIONS:VBB =

VP =

VV =

Practical Time Period =

VBB - VV Theoretical Time Period = RC ln -------------

VBB – VP

56



Practical Frequency = =

Theoretical Frequency =

Percentage Error = =

PRECAUTIONS:

1. Connections should be done as per the circuit diagram.2. Readings should be taken with out parallax error.3. Before switch on DC supply are should keep the current knob in maximum position


RESULT:

57



9.BOOT STRAP SWEEP GENERATOR AIM:

To design a Boot Strap Sweep generator and calculate the sweep amplitude and plot the Graphs .

APPARATUS:1. Transistor [BC 107] 2 Nos2. Diode [1N 4007] 1 No3. Resistors [1 KΩ] 2 Nos4. Resistors [10 KΩ] 1 No5. Resistors [470 KΩ] 1 No6. Capacitors [100 µf(2 Nos), 1 KpF(1 No)] 3 Nos7. Regulated Power Supply [0 – 30 V] 1 No8. C.R.O. 1No9. Function Generator 1 No10. Bread Board 1 No11. Connecting Wires

THEORY: 1. The basic principal involved in generating a ramp voltage is that as current an

experimentally decreasing current, the capacitor acts as a short circuit at t = 0 and as an open circuit when steady state has been reached.

2. If the capacitor is kept constant, the voltage developing across the capacitor is a ramp voltage.

3. The capacitor kept constant by incorporating an auxiliary voltage source. 4. Such that the source voltage is equal to the capacitor voltage but acts in opposition to

it .CIRCUIT DIAGRAM:

MODEL GRAPHS:58



PROCEDURE:

1. Connections should be done as per the circuit diagram.2. Switch on the power supply and give required voltage.3. Apply square wave at 100Hz frequency with 10 V [peak to peak] amplitude by using

function generator.4. Connect the square wave generator output to input of the boot strap generator circuit.5. And observe the same square wave on one channel of dual trace C.R.O. 6. Observe the output of the boot strap of the circuit on the second channel.7. Vary the value of the capacitor in steps from 100 pF to 1 mF and second the output

variations according to the variations. 8. Compare the output and input wave forms.

OBSERVATIONS: VS = 8 VT = 4.8 µ secTS = 2 µ secTr = 0.2 µ sec and Tg = 3 µ sec

CALCULATIONS:

Sweep Speed = = = 4 X 10 6 V / S

59



PRECAUTIONS:

1. Readings should be taken without parallax error.2. Before switch on DC supply are should keep the current knob in maximum position


RESULT:

10.SAMPLING GATES

60



AIM: To observe the output of the Unidirectional diode gate for different Control Input

Voltages

APPARATUS:

1. Resistors 1KOhm -2

2. Capacitor – 10Micro Farads

3. 1N4007 Diode

4. Bread board

5. CRO (1Hz-20MHz)

6. Function generator (1Hz-1MHz)- 2

THEORY:

Unidirectional Diode Gates:

At point A receives both the signal Vs and the control input Vc we observe here that while the input signal Vs is capacitively connected to A, the control input Vc is directly coupled. The net signal at point A can be determined by employing superposition theorem .A careful inspection indicates that the input signal Vs is passing through a high pass filter and the control input Vc is passing through a low pass filter to reach point A. It can be seen that the input to the sampling gates has a low duty cycle pulse train. The width of the control pulse is large compared to input pulse width .The diode in the sampling circuit is less reverse biased when the control input rises to its higher voltage level –V2. However the diode is forward biased only during the narrow input signal Vs reaches point A.

The input pulse that lies with in the duration of the control pulse is transmitted through the diode as output .The effect of the level –V2 on the output of the gate waveform can be seen in fig 2 .In fig 2.a we have –V2 = -5V and for a 10V input pulse; a 5V pulse appears as output. Operation in this manner is advantageous when the bottom line of the input signal has a noise signal surrounding it This would enable us to choose a noise threshold appears at the output .When used in this manner , the circuit is referred to as a threshold gate .In fig 2-b –V2 = 0 and the entire input pulse is transmitted to the output , whereas in fig 2-c –V2 is positive and the signal appears super imposed on a 5V pedestal. We have to remind the reader that the waveforms shown above are unrealistic as they do not take the effects of the high pass filter and the low pass filter mentioned at the beginning of this section .We are quite aware of the fact that R1C1 networks constitutes an integrator to the control input Vc .As a consequence , the control input at A would be rising exponentially and exponentially falling at a similar rate .The rates and fall are controlled by the time constant R1C1. The above discussion makes it clear that this form of a sampling gate is not particularly suitable for selecting a portion of a continuous waveform .However when the

61



input signal is a short pulse whose duration is clearly smaller than the width of the control input , the performance of the gate is acceptable .

CIRCUIT DIAGRAM:

PROCEDURE:1. Connect the circuit as shown in the circuit diagram.2. Connect the signal generator at the signal input with a frequency of 10KHz , 10Vp-p .3. Connect the another signal generator at the control input with a frequency of 1KHz , -10Vp-p .4. Vary the control input voltage and observe the output for different control input voltages say 0V, -5V & -10V.

MODEL GRAPHS:

PRECAUTIONS:

1. Readings should be taken without parallax error.

62



2. Before switch on DC supply or Function Generator all voltage knobs should keep minimum and the current knob in maximum position .

RESULT:

63


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