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120.26084 Rev. 2 Copyright © 2001

FEATURES

3-lead or 5-lead ECG front end (one ASIC).12-lead ECG front end (two ASICs).Four 8X gain differential amplifiers per ASIC.Built-in pacer pulse detector.Filtered lead-off detection for each electrode.Programmable input offset for each channel.Selectable reference electrode (5 choices).Patient range neonate through adult.Supports AAMI EC11:1991 and EC13:1992.On-chip RF filtering on all ECG inputs.Supports impedance pneumography (RESP).6 mW typical active power, 1.4 mW sleep

mode.Built-in self-test capability.Bidirectional 3.3 V/5 V serial control interface.Space-saving 0.36 sq. in. 52-pin PQFP pkg.ASIC and notes simplify and accelerate

product development and qualification.100% CMOS technology.

OVERVIEW

The ECG ASIC is a complete front-end for “3-lead” (3-electrode, up to 6-vector) or “5-lead” (5-electrode, 7-vector) monitoring or diagnostic ECG systems. Two identical ECG ASIC devices can be used together to form a complete “12-lead” (10-electrode, 12-vector) ECG system. The ASIC accepts low-level body surface ECG signals and amplifies and conditions those signals to directly feed an external 4-channel sigma-delta A/D converter. The A/D converter output feeds a suitable processor that performs the bandpass filtering, derivation of remaining ECG vectors, QRS-picking analysis, data transmission, display, and other functions.

ECG ASICECG 3-lead, 5-lead, 12-lead and RESP Signal ProcessingECG ASIC Part Number 000.91163

ECG ASIC

Copyright 2001 by Welch Allyn OEM Technologies. Welch Allyn® and Protocol® are registered trademarks, and Pryon™ is a trademark of Welch Allyn, Inc. Welch Allyn, Inc. is protected under various patents and patents pending. Welch Allyn OEM Technologies is a division of Welch Allyn, Inc.Information furnished by Welch Allyn OEM Technologies is believed to be accurate and reliable. However, no responsibility is assumed by Welch Allyn OEM Technologies for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Welch Allyn OEM Technologies.Disclaimers: This document may be wholly or partially subject to change without notice. All rights are reserved. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written permission from Welch Allyn OEM Technologies.Welch Allyn OEM Technologies • 8500 SW Creekside Place, Beaverton, OR 97008-7107 U.S.A.Phone: 503-526-4900 • Fax: 503-526-4901 120.26084 Rev. 2 05/01

ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM Technolgies

This document is proprietary property of Welch Allyn OEM Technologies.Information in this document may not be disclosed without prior written consent of Welch Allyn OEM Technologies

Copyright © 2001 120.26084 Rev. 2

The use of a high-resolution A/D converter for each channel eliminates the need for hardware band-pass filtering, high-gain amplification, sample and holds, and trace restoration. These functions and others can be implemented in software, resulting in a simpler design of associated hardware and achieving improved performance through better matching of gain and phase, and zero time skew between channels. This virtually eliminates possible errors in any additional ECG vectors that are derived by software from the ECG vectors developed by the ASIC hardware.

TERMINOLOGY

AAMI

- Association for the Advancement of Medical Instrumentation. (See Related Documents, page 80.)

ASIC

- Application-Specific Integrated Circuit.

CAUTION statement

- Identification of a possible condition, event, or fault that could result in damage to the equipment or other property.

ESIS

- Electro-Surgical Interference Suppression.

HOST SYSTEM

- The medical device within which the ECG ASIC component is integrated.

IMPEDANCE PNEUMOGRAPHY

- A technique for detecting respiration by detecting the slight changes in electrical impedance of the chest and abdomen that occur during respiratory efforts. The technique involves injecting a psuedo constant current, high frequency (50-80 kHz) carrier between body surface ECG electrodes, and monitoring the slight changes in voltage that occur between those electrodes due to impedance changes during breathing.

LEADS

and

VECTORS

-

“Lead”

is used preceeding a particular ECG vector, such as

Lead II

or

Lead V

.

However,

“lead”

in common usage can mean an ECG vector, an ECG electrode, or an electrode lead wire or connection. Where using a more exact term in this manual might be confusing or would read awkwardly, the term

lead

is kept, but it is either used in quotes (

“lead”

), or its more precise meaning is shown.

VN

(such as

V2

or

V6

) is used in this manual to indicate a particular unipolar chest ECG vector (according to Wilson), such as

Lead V6

.

V

N

(such as

V

2

or

V

6

) is used in this manual to indicate a chest electrode located at physical position “

N

”. This electrode is used to develop the

Lead VN

vector.

R.T.I.

Referred To Input.

WARNING statement

- Identification of a possible condition, event, or fault that could result in personal injury.

NOTEWelch Allyn OEM Technologies has designed the ECG ASIC in accordance with the applicable hardware requirements for this type of component for EC11-1991 and EC13-1992 as described on page 80 of this manual. However, it is the sole responsibility of the device manufacturer who incorporates the ECG ASIC into a host system device to demonstrate and confirm that the device complies with all regulatory, safety, and performance requirements for the device specific to intended use and the applicable market where the device is sold.

Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASIC


120.26084 Rev. 2 Copyright © 2001

SUMMARY OF CHANGES TO THIS MANUAL SINCE REVISION 1

The following information has changed or been added since Revision 1 of this manual.

Description of Change Affected Pages

Information is added about CMR issues while using a 3-wire ECG cable with grounded reference electrode to get 2 simultaneous ECG vectors.

Pages 16-18 of the Reducing 60 Hz Interference section.

Explanations are added for various lead fail recovery and pacer detection anomalies observed while using certain types of patient simulators.

See respectively page 21 of the Lead-Fail Detection Function section, and the Miscellaneous Causes for False Pacer Detection section on pages 28 and 29.

Additional information is provided for successfully dealing with defibrillator discharges. For an overview, see page 21 of the Lead Fail Detection Function section, and all of the Possible Causes for Processor Resets, Etc., During Defibrillator Discharge section on pages 56 and 57. Additional component locations that should use physically larger packages are listed in the Component Voltage and Power Ratings section on page 59. Exclusion of neon bulb currents from the ground plane is discussed on page 73 of the Layout Considerations section. To help prevent circuit board arcovers, minimum board spacings are revised and assumptions are explained on pages 75 and 76 of the Layout Considerations section.

Pages 21, 56, 57, 59, 73, 75 and 76 (see detailed references at left).

A better way of optimizing the proper voltage for CLPIP in the chest-lead-present detector is added. Page 24 of the How the Chest Lead-Present Detector Works section.

Polarity is fixed in the Offset Control table on page 36, and more information is added about why and how to use the additional ECG offset capability.

Dealing With ECG Offset section on pages 61-63.

In the 5-lead ECG/respiration application schematic, a wrong Q2 connection is fixed, U2 reverts to a 74HC4053, component impedances are lowered in the synchronous demodulator, a low-noise VDDRSP supply is added and connections are defined for it, the capacitive loading on +2.5V is reduced, a clamp diode is added on CLPIN, and all neon bulbs share a single point connection to ground.

Page 40.

In the 12-lead ECG application schematic, the capacitive loading on +2.5V is reduced, and all neon bulbs share a single point connection to ground.

Page 41.

Circuit and power supply noise solutions are provided for noise issues in respiration, including circuit changes, and a low-noise VDDRSP supply implementation.

See respectively, page 40 schematic, page 43 of the Respiration Circuit Issues section, and pages 53 and 54 of the ASIC Power Connections and Issues section.

Respiration artifacts from non-patient sources. Pages 44 and 45.

Added are ranges of respiration performance variations that have been observed with a range of different ECG cable designs.

Pages 45-47 of the ECG Cable Design Versus RESP Performance section.

Detail is added for optimizing parts values in respiration’s synchronous detector for a particular instrument and ECG cable design.

Fine Tuning RESP’s Synchronous Detector section on pages 47 and 48.

Considerations are added for using a channel of the AD7716 ADC in a multiplexed application. Page 50 of the Advantages and Disadvantages of the AD7716 section.

Factors are described that affect how well an ECG cable design can tolerate defibrillator discharges. Observed limitations are added on the number of defibrillator discharges that are tolerated by neons and ECG cables.

Pages 59 and 60 of the Defibrillator Issues with ECG Cables section.

Differences in the stress levels caused by various standardized defibrillator-withstand tests are added.

Page 60 of the Defibrillator Issues with ECG Cables section.

Board grounding issues (separate analog & digital ground planes vs a single ground plane) are discussed.

Pages 73-75 of the Layout Considerations section.

All references have been removed to an ECG waveshape distortion hazard caused by actively driving signal electrode LL through an intentional RL-LL short in 3-lead cables. Analysis and experiments have confirmed that this configuration does not actually lead to signal distortion.

(Removed from Rev. 1 Manual, pages 14 and 60.)



Copyright © 2001 120.26084 Rev. 2

BASIC DESCRIPTION

A processor is required to properly control the ASIC and perform QRS-picking, breath-picking, and other signal analysis as desired. The basic features of the ASIC are described below.

ECG Portion

The ASIC directly develops signals for either Lead I or Lead II (switchable), and a fixed Lead III for 3-electrode systems. The ASIC adds to these a fixed Lead V for 5-electrode systems. A pair of ASICs develops a switchable Lead I or Lead II, and fixed vectors for Lead III and Leads V1 through V6 for 10-electrode systems. Additionally, Lead II or Lead I and Leads aV

R

, aV

L

, and aV

F

may be developed algebraically from each system, giving up to 6 total vectors for a 3-electrode system, 7 total vectors for a 5-electrode system, and 12 total vectors for a 10-electrode system.

All ECG lead selection and differential amplification is internal, with all 4 amplifier outputs simultaneously available. When a higher than normal dc offset in the ECG electrodes is a concern, each of the 4 differential amplifiers can have its input offset range individually shifted to accommodate –500 to +100 mV, -300 to +300 mV, or –100 to +500 mV. (A higher-than-normal dc offset occurs following defibrillation, possible during body surface pacing, and while using electrodes of dissimilar materials, electrodes lacking silver/silver chloride, or stainless needle electrodes.) All differential amplifier outputs are continuous-time signals.

A versatile lead (electrode) fail detection system provides connection status information for each of the 5 electrodes used with each ASIC. The detection scheme uses dc current sources, buffer amplifiers, low-pass filters, and comparators with hysteresis to detect a disconnected electrode. The low-pass filters virtually eliminate lead-fail detection problems caused by power line noise pickup. The status of each electrode is stored in a register that may be read by the serial interface. As an additional convenience, the ASIC provides a dedicated output pin that may be polled or used to generate a processor interrupt whenever there is any change in the status of any of the electrodes.

The ASIC uses a unique method to distinguish between “3-lead” and “5-lead” ECG cables. This method works whether the cables are attached to a patient or not, and is not fooled by the RL-LL short built into many “3-lead” ECG cables.

To provide the maximum number of usable ECG vectors from a given number of electrodes (particularly after an electrode becomes accidentally disconnected), any one of the ASIC’s 5 electrodes may be used as a reference electrode. The selected reference electrode may be either connected to the ECG power supply’s common ("gnd"), or may be driven by a common mode signal obtained from any valid ECG vector.

The ASIC includes a built-in pacer pulse detector which can select any one of the four amplifier outputs as its source. It detects 100 µsec-wide pacer pulses of ±3 mV to ±700 mV amplitude, and 200 µsec to 2 msec-wide pacer pulses of ±2 mV to ±700 mV amplitude. A proprietary noise-adaptive detection mode may be enabled when desired. This mode dramatically improves the noise immunity of the detector by automatically raising the pacer pulse detection threshold to slightly greater than the amplitude of most repetitive, ambient electrical noise spikes.

Built-in self-test circuits facilitate testing each ECG vector, the pacer detector, lead-fail detection, offset capability, and other functions under processor control.

Respiration

The ASIC provides all the digital circuitry required to do an optional impedance pneumography respiration monitoring system. It generates 3-level signals for driving two electrodes at a time (one fixed, the other selectable), such as RA and LA, or RA and LL. A digital phase reference signal is provided to control the switching of an external synchronous detector. Timing of all respiration signals is derived from the master clock signal provided to the ASIC.



120.26084 Rev. 2 Copyright © 2001

Communication Link

A 4-line (CS/, DIN, DOUT, and SCLK) serial interface provides easy communication with a wide range of processors. Logic levels may be either 3.3 V or 5 V as desired.

Power

The ASIC operates from ±5 V analog supplies, and either a +3.3 V or +5 V digital supply. It also requires a +2.5 V reference. All ASIC bias currents are determined by the +2.5 V reference and an external resistor, which stabilizes performance over the ASIC’s full operating temperature range.

A power-saving sleep mode is provided which reduces ASIC power consumption to 1.4 mW typically. ECG lead-fail detection remains fully functional during this sleep mode.

SPECIFICATIONS

Specification values shown in

bold

type

are 100% tested at 25˚ and 70˚C. All other values are guaranteed by design and are not 100% tested.

Specifications

a

ParameterValue

b

Units Condition/CommentsMin Typ Max

ECG INPUTS (EIN1-EIN5)

Input offset, normal rangeInput offset, shifted rangeInput bias currentInput referred noise, Leads I, II, III

Input referred noise, Lead V

+Supply rejection-Supply rejection

Common mode rejection, Leads I, II, III

c

Common mode rejection, Primary Lead V

Common mode rejection, Secondary Lead V

d

±219

8060636060

<±1±235NA10

17

9577746767

±5.0±250

mVmV

µ

V p-p

µ

V p-p

dB r.t.i.dB r.t.i.dB r.t.i.dB r.t.i.dB r.t.i.

EIN1-EIN5 all shorted to gnd and offset disabledEIN1-EIN5 all shorted to gnd and offset enabledDominated by lead-fail detection current0.5-100 Hz BW, CLKIN=5.213 MHz, ESIS filter inputs grounded0.5-100 Hz BW, CLKIN=5.213 MHz, ESIS filter inputs groundedAt 60 Hz on VDDA/VDDA1/VDDRSPAt 60 Hz on VSS/VSSAAt 60 Hz on EIN1-EIN3. See footnote c.At 60 Hz on EIN1-EIN5. See footnote c.At 60 Hz on Sec EIN1-EIN4, on Pri EIN1-EIN3, Pri AVG30 to Sec AVG3IN. See footnote c.; footnote d.

Common mode input voltage rangeRF low-pass filter frequencyLead weighting error 0

-2.0 to 4.017

±1.5

VkHz%

-3 dB point, each inputPer AAMI EC11 section 3.2.7.3 test

ECG LEAD-FAIL DETECTION

Lead-fail currentLead-fail current on RL (or V

2

)

Lead-fail threshold V+

e

Lead-fail threshold V-

Lead-fail threshold V+

Lead-fail threshold V-

Low-pass filter

50

0.43

0.46

0.35

0.37

0.68

0.70

0.55

0.58

7000.48-84% of V+-0.73-84% of V+-7

90±50.53

0.50

0.80

0.76

nAnAVVVVVVVVHz

dc, pullup on active inputs (EIN1-EIN5)dc, pullup disabled (EIN5 only)For ±300 mV offset range,

bold

=test limits. See footnote e.For ±300 mV offset range,

bold

=test limit. See footnote e.For -100/+500 mV, or -500/+100 mV range, any input,

bold

=test limits. See footnote e.For -100/+500 mV, or -500/+100 mV range, any input,

bold

=test limit. See footnote e.-3 dB point, each input

LEAD CHANGE OUTPUT (LDCH/)

Output High Voltage

f

Output Low Voltage

2.58

0.002.860.12

3.30

0.25

VV

Iout source

≤

0.5 mA. See footnote f.Iout sink

≤

0.5 mA. See footnote f.



Copyright © 2001 120.26084 Rev. 2

ECG OUTPUTS (ECGO1-ECGO4)

DC gainDC gain matching errorBandwidth (ASIC plus ESIS filter)Bandwidth (ASIC only)Output voltage swingCross talk

7.88

0

±4.5

8.0

0-40-11±4.7<7

8.12±1.5

<10

%kHzkHzVmV p-p

Including internal average of RA, LA, and LLWorst case of all 4 outputsSmall signal using filter in 5-lead schematic (page 40)Small signal

≥

60 k

Ω

to gndIn any enabled x8 output (ECG01-ECG04) when any single input (EIN1-EIN5, AVG3IN), which should not affect that output, is a 600 mV p-p 1 kHz sine wave, and all other inputs = 0 V.

SLEEP CONTROL OUTPUT (ECGON)

Output High VoltageOutput Low Voltage

-0.40

-5.00-0.22-4.90

0.00

-4.67

VV

Iout source

≤

0.5 mAIout sink

≤

0.5 mA

ECG DRIVEN LEAD OUTPUT (LDRVO)

Output voltage swingResistance to gnd

±4.70

±4.9033

67

Vk

Ω

(Reference Electrode Driver)100 k

Ω

load to (virtual) gnd on LDRVOLDRVO to gnd when LDROFF = HI

ECG COMMON MODE INPUT (AVG3IN)

Input voltage rangeInput current

-2.0 to 4.0±1

VnA

ECG AVERAGE OF 3 OUTPUT (AVG30)

Output voltage rangeOutput offsetOutput impedance

-2.0 to 4.0<±10

≈

3.3

±20

VmVk

Ω

Not loadedEIN1-EIN3 shorted to gnd, all modes but 12 lead sec.Except high Z in 12-lead secondary mode

ECG COMMON MODE OUTPUT (CMOUT)

Output voltage range -2.0 to 4.0 V Not loaded

ECG CHEST LEAD DETECTOR

Input offsetInput currentCommon mode input rangeCLPCLK output high voltageCLPCLK output low voltageDetection thresholdCLPCLK frequency

4.60

0.00

±5<±0.02-2.0 to 4.04.750.0816532.58

±20

±1

5.00

0.16

mVnAVVVpF totalkHz

CLPIN - CLPIPCLPIN and CLPIPCLPIN and CLPIPIout source

≤

0.5 mAIout sink

≤

0.5 mAWith circuit in 5-lead schematic (page 40)CLKIN ÷ 160, 50% duty factor

ECG PACER DETECTOR (+PDETO)

Max detection thresholdMin detection threshold

100 µsec pulses200 µsec to 2 msec pulses100 µsec pulses200 µsec to 2 msec pulses

Input currentPDETO output high voltagePDETO output low voltagePDETO pulse durationPDETO delay from input pulse’s leading edge

±700

4.60

0.002.95

±2.8±1.8±0.5±0.35

4.750.08

0.80

±3

±2

±15.00

0.16

3.93

1.00

mV

mVmVmVmVnAVVmsecmsec

100 µsec to 2 msec pulses, all modes

Non-adaptive and adaptive with min thresholdNon-adaptive and adaptive with min thresholdAdaptive with noise-limited thresholdAdaptive with noise-limited thresholdPDFB, PDCAP (checked indirectly)Iout source

≤

0.5 mAIout sink

≤

0.5 mA15360-20480 CLKIN periodsFor 2 mV, 200 µsec pulses. Others are faster.

ECG SELF-TEST

VTST voltagePDTST voltagePDTST width

±119

100

±126-4.25

±134

mVmVµsec

TSTON HI, sign determined by SIGNTSTON HI, PDTST HIMin required for effective ±testing, determined by speed of writing to serial interface (user-controlled).

Specifications

a

(Continued)

ParameterValue

b




120.26084 Rev. 2 Copyright © 2001

RESP OUTPUTS (RSPORA, RSPOLA, RSPOLL)

Output high voltageOutput mid voltage

∆

from RSPMIDOutput low voltageOutput frequency

4.78

0.000.00

4.90±0.180.0965.16

5.00

±0.350.18

VVVkHz

Iout source

≤

0.5 mA| Iout |

≤

0.5 mA (

∆

due entirely to Iout)Iout sink ≤0.5 mACLKIN ÷ 80

RESP Φ REF OUTPUT (RSPREF)Output high voltageOutput low voltagePhase shiftOutput frequency

4.750.00

4.870.054565.16

5.000.15

VVdegreeskHz

Iout source ≤0.1 mAIout sink ≤0.1 mADelayed from RSPORA’s 0 to 2.5 V transitionCLKIN ÷ 80, 50% duty factor

RESP PWR DN OUTPUT (RSPOFF)Output high voltageOutput low voltage

4.600.00

4.750.08

5.000.16

VV

Iout source ≤0.5 mAIout sink ≤0.5 mA

CLKIN INPUT (Schmitt Trigger)Input frequencyCLK LO timeCLK HI timeSchmitt trigger VT+Schmitt trigger VT-Input capacitanceInput current

5.07474

1.50

5.213 5.4

3.00

10±1

MHznsecnsecVVpFnA

See discussion of CLKIN frequency on page 31.

Tested with 5.2 MHz square waveTested with 5.2 MHz square wave

GENERAL PURPOSE OUTPUTS (GPO1-GPO4)

Output high voltageOutput low voltage

4.600.00

4.750.08

5.000.16

VV

(Powered by VDDRSP and RSPGND)

Iout source ≤0.5 mAIout sink ≤0.5 mA

TEST INPUT (HWTST)Input high voltageg

Input low voltageInput pulldown to gndPulse width

2.50-0.3052

3.300.0020

3.601.0060

VVnAµsec

See footnote g.See footnote g.current sink

VOLTAGE REFERENCE INPUT (VREF)Voltage rangeInput currentInput current

2.49 2.5063<3

2.51905

VµAµA

See Voltage Reference Issues section (page 31).While any offset and/or self-test voltage is enabled.For all other conditions.

Specificationsa (Continued)

ParameterValueb


ECG ASIC COMPANY CONFIDENTIAL Welch Allyn OEM TechnolgiesThis document is proprietary property of Welch Allyn OEM Technologies.

Information in this document may not be disclosed without prior written consent of Welch Allyn OEM Technologies

Copyright © 2001 120.26084 Rev. 2

POWER REQUIREMENTSCASE #1

+5 V supply current (+offsets)-5 V supply current (+offsets)+5 V supply current (-offsets)-5 V supply current (-offsets)+3.3 V supply current

CASE #2+5 V supply current-5 V supply current+3.3 V supply current

CASE #3+5 V supply current-5 V supply current+3.3 V supply currentRSPMID current

CASE #4+5 V supply current-5 V supply current+3.3 V supply current

CASE #5+5 V supply current ∆-5 V supply current ∆+3.3 V supply current ∆

9801000930980<3

600580<3

745595<3<3

143125<3

025<9

140014001400140010

95090010

110090010

18017010

µAµAµAµAµA

µAµAµA

µAµAµAµA

µAµAµA

µAµAµA

See also Sleep Mode Issues section (page 52)

CLKIN, ECGO1-ECGO4 (for “12-lead” secondary mode), pacer detector, chest-lead-present detector, and Reference Electrode Driver all active; EIN1-EIN4 = 0 V; all 4 internal offsets enabled, RESP disabled; static serial interface (CS/, DIN, SCLK=3.3 V).

(Typical “12-lead”/no RESP; power same for “5-lead”.) Same as Case #1, no internal offsets enabled.

(Typical “5-lead” with RESP.) Same as Case #2, except RESP is enabled using circuits in “5-lead” schematic (page 40). Currents listed are for ASIC only.(Theoretically = 0 if RSPMID=VDDRSP/2)

(Sleep mode.) ECG differential amps, pacer detector, chest-lead-present detector, Reference Electrode Driver, and RESP all off; CLKIN at 5V or 0V, serial interface static (CS/, DIN, SCLK = 3.3V), internal lead-fail oscillator on.Increase in supply currents due to active serial interface, SCLK = 500 kHz, alternating 1’s and 0’s on DIN, CS/ = 0 V for 15 SCLKs, 3.3V for 1 SCLK.

SERIAL INTERFACEInput high voltageInput low voltageInput pullup to 3.3 VDOUT high voltageDOUT low voltageInput and output capacitance

SCLK TIMINGSCLK T high (t6)SCLK T low (t4)SCLK frequencySCLK rise time

WRITE CYCLE TIMINGCS/ setup time (t1)DIN setup time (t2)DIN hold time (t3)CS/ hold time (t7)

READ CYCLE TIMINGCS/ setup time (t1)DIN setup time (t2)DIN hold time (t3)DOUT delay time (t5)DOUT relinquish time from CS/ (t8)CS/ hold time (t7)

2.50-0.30402.580.00

900900

200200200200

200200200

200

3.300.00902.860.13

18040

3.601.001803.300.2510

50020

VVnAVVpF

nsecnseckHznsec

nsecnsecnsecnsec

nsecnsecnsecnsecnsecnsec

(CS/, SCLK, DIN). See footnote g.(CS/, SCLK, DIN). See footnote g.(CS/, SCLK, DIN) current sourceIout source ≤ 0.5 mA. See footnote f.Iout sink ≤ 0.5 mA. See footnote f.

20 pf load.

a. VDDA = VDDA1 = VDDRSP = +5.0 V; VSS = VSSA = -5.0 V; VDDIO = +3.3 V; VREF = RSPMID = +2.50 V; AGND1 = AGND2 = DGND = RSPGND = 0 V; CLKIN = 5.213 MHz; RBIAS = 1 MΩ ±1% to +2.50 V; outputs not loaded unless otherwise specified.

b. Min and Max values apply over the full operating range of 0˚-70˚C. Typical values apply at 25˚C only. Bold specifications are 100% tested. Other specifications are guaranteed by design but are not 100% tested.

c. The CMR tests of reference documents EC11 and EC13 give much better results than this because they take advantage of the ECG channel’s required isolation.

Specificationsa (Continued)

ParameterValueb


Welch Allyn OEM Technolgies COMPANY CONFIDENTIAL ECG ASICThis document is proprietary property of Welch Allyn OEM Technologies.


120.26084 Rev. 2 Copyright © 2001

d. Proper CMR of the ASIC in 12-lead secondary mode requires the inherent delay in the primary chip’s AVG30 path.e. Settling time issues during automated testing preclude more precise testing of these specifications. However, the test limits do

guarantee satisfactory operation.f. Output range = GND - VDDIO. If VDDIO = +5.0 V, then logic HI = 5.0 V; output drive capability then matches output PDETO’s.

(Speed is not increased as limited by internal logic circuits.)g. Input range = GND-VDDIO. (If VDDIO = +5.0V, then logic HI = 5.0V. Input level characteristics then are VIL = -0.30 to 1.50 V,

VIH = 3.60 to 5.30 V. (Speed is not increased as limited by internal logic circuits.)

Recommended Operating Conditions

Parameter Minimum Maximum

VDDA, VDDA1, VDDRSP 4.5 V 5.5 V

VDDIO 3.0 V 5.5 V

VSS, VSSA -4.5 V -5.5 V

VREF +2.49 V +2.51 V

CLKIN frequency 5.0 MHz 5.4 MHz

Bias setting resistor (RBIAS to VREF) 0.99 MΩ 1.01 MΩ

Operating Ambient Temperature 0 °C 70 °C

Absolute Maximum Ratingsa

a. Operation outside these maximum ratings can affect the reliability of the ASIC.

Parameter Minimum Maximum

VDDA to GND -0.3V +6V

VDDA1 to VDDA -0.1V +0.1V

VDDRSP, RSPMID to GND -0.3V VDDA+0.3V

VDDIO to GND -0.3V VDDA+0.3V

VREF to GND -0.3V VDDA+0.3V

VSSA to GND -6V +0.3V

VSSA to VSS -0.3V +0.3V

GND to any other GND -0.1V +0.1V

Any input except CS/, DIN, SCLK, HWTST to GND VSSA-0.3V VDDA+0.3V

Inputs CS/, DIN, SCLK, HWTST to GND -0.3 V VDDIO + 0.3 V

Storage Temperature -25°C 125°C

Soldering Temperature, 40 seconds maximum 220°C



Copyright © 2001 120.26084 Rev. 2

The ASIC incorporates internal protection circuits that prevent latchup for currents up to 100 mA as tested under EIA/JEDEC Standard EIA/JESD78. Extra care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. After the ASIC is installed into a complete board, the ESD tolerance of the ECG system is determined almost entirely by devices external to the ASIC.

Write and Read Operation Timing Diagrams

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

I2 I1 I0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

HIGH Z

SCLK

CS/

DIN

DOUT

A. WRITE OPERATION (See serial interface specifications for timing definitions.)

t1

t 2 t 3

t 4 t 6 t 7

REGISTER UPDATE OCCURS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

I2 I1 I0 A4 A3 A2 A1 A0

HIGH Z

SCLK

CS/

DIN

DOUT D7 D6 D5 D4 D3 D2 D1 D0

B. READ OPERATION (See serial interface specifications for timing definitions.)

t1

t 2 t 3

t 4 t 6

t 5

t 7

t 8



120.26084 Rev. 2 Copyright © 2001

RESP Circuit Timing Diagrams

PIN CONFIGURATION

ECG ASIC Pin Configuration

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

TIME (PERIODS OF CLKIN)

A. OUTPUT RSPORA

B. OUTPUTS RSPOLA/RSPOLL

C. OUTPUT RSPREF

10 30 3010

80

80

10 30 10

10 4040

VDDRSP

RSPMID RSPGND

VDDRSP RSPMID

VDDRSP

RSPGND

RSPGND

39 38 37 36 35 34

33 32 31 30 29 28 27

40414243444546474849505152

1 2 3 4 5 6 7 8 9 10 11 12 13

26252423222120191817161514

PIN 1 INDICATOR

PD

FB

PD

CM

PIN

PD

CA

PC

LPC

LKV

DD

RS

PR

SP

GN

D

RS

PM

IDR

SP

OLL

RS

PO

LAR

SP

OR

AR

SP

RE

FD

GN

DV

SS

PDETOLDCH/CLPINCLPIP

VDDA1VDDAVSSA

AVG3OVREF

ECGO4ECGO3ECGO2ECGO1

AG

ND

2A

GN

D1

EIN

5E

IN4

EIN

3E

IN2

EIN

1A

VG

3IN

CM

OU

TLD

RV

ILD

RV

OR

BIA

SN

/C

GPO4GPO3GPO2GPO1CLKIN DINSCLKDOUTVDDIOCS/HWTSTECGONRSPOFF

Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment, and can discharge without detection. Although this device features ESD (Electrostatic Discharge) protection circuitry, permanent damage may still occur on this device if it is subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions must be used to help avoid performance degradation or loss of functionality.



Copyright © 2001 120.26084 Rev. 2

Pin Descriptions

PIN NAME I/O TYPE FUNCTION

1 AGND2 Ground Analog ground used for all switched capacitor circuits (0 V nominal)

2 AGND1 Ground Analog ground used for all continuous-time circuits (0 V nominal)

3 EIN5 Analog I/O ECG electrode input 5 (also can be driven lead output)





8 AVG3IN Analog In Average of RA, LA, LL input (from Primary ASIC in a 12-lead system)

9 CMOUT Analog Out Buffered common-mode output (for lead-drive circuit)

10 LDRVI Analog In Inverting input to lead-drive op amp

11 LDRVO Analog Out Output of lead-drive op amp

12 RBIAS Analog In Virtual ground input for external bias resistor (1 Megohm to VREF)

13 N/C ---- Not used. Make no connection to this pin.

14 RSPOFF Digital Out External respiration disable control (0 V, VDDA logic levels)

15 ECGON Digital Out External ECG enable control (VSSA, 0 V logic levels)

16 HWTST Digital In Hardware test control input (0V, VDDIO logic levels, pull-down to 0 V)

17 CS/ Digital In ASIC select I/O input (0V,VDDIO logic levels, LOW True, pull-up to VDDIO)

18 VDDIO Power Positive digital power pin for serial I/O (+3.3 V nominal)

19 DOUT Digital Out Serial data output for I/O (Tristate 0V, VDDIO logic levels)

20 SCLK Digital In Serial clock input for I/O (0 V, VDDIO logic levels, pull-up to VDDIO)

21 DIN Digital In Serial data input for I/O (0 V, VDDIO logic levels, pull-up to VDDIO)

22 CLKIN Analog In External 5.213 MHz clock input (Schmitt trigger input)

23 GPO1 Digital Out General purpose output bit (0V, VDDRSP logic levels)




27 VSS Power Digital VSS (-5 V nominal)

28 DGND Ground Digital ground (0 V nominal)

29 RSPREF Digital Out Respiration carrier phase reference output (0 V, VDDRSP levels)

30 RSPORA Analog Out Respiration drive output for right arm (0 V, RSPMID, VDDRSP levels)

31 RSPOLA Analog Out Respiration drive output for left arm (0 V, RSPMID, VDDRSP levels)

32 RSPOLL Analog Out Respiration drive output for left leg (0 V, RSPMID, VDDRSP levels)

33 RSPMID Pseudo Power Respiration drive mid-level voltage reference input (+2.5 V nominal). See ASIC Power Connections for details (page 53).

34 RSPGND Ground Ground reference for respiration circuits (0 V nominal)

35 VDDRSP Power Positive power for respiration circuits (+5 V nominal). Must have very low noise.

36 CLPCLK Digital Out Chest-lead-present detector reference output signal (0 V,VDDRSP levels)

37 PDCAP Analog I/O Adaptive pacer detector external filter capacitor connection

38 PDCMPIN Analog In Adaptive pacer detector comparator input.

39 PDFB Analog In Adaptive pacer detector feedback input

40 PDETO Digital Out Adaptive pacer detector output (0 V, VDDA logic levels, HIGH True)

41 LDCH/ Digital Out Lead-Fail (electrode connection) status change output (0 V, VDDIO logic levels, LOW True)



120.26084 Rev. 2 Copyright © 2001

ECG ASIC BLOCK DIAGRAM

ECG ASIC Block Diagram

42 CLPIN Analog In Chest-lead-present detector negative comparator input (sense signal)

43 CLPIP Analog In Chest-lead-present detector positive comparator input (dc reference)

44 VDDA1 Power Analog VDD used for all switched capacitor circuits (+5 V nominal)

45 VDDA Power Analog VDD used for all ECG continuous time circuits (+5 V nominal)

46 VSSA Power Analog VSS (-5 V nominal)

47 AVG3O Analog Out Buffered average of RA, LA, LL 3 kohm output (to Secondary ASIC in a 12-lead system)

48 VREF Analog In DC voltage reference input (+2.5 V nominal)

49 ECGO4 Analog Out ECG amplifier output 4




Pin Descriptions (Continued)

PIN NAME I/O TYPE FUNCTION



Copyright © 2001 120.26084 Rev. 2

DETAILED DESCRIPTIONThis section describes the function of the ASIC sub-circuits, guidelines on how each sub-circuit should be used, and design considerations and tradeoffs involved in possible applications.

Sample schematics on page 40 and page 41 provide detailed information regarding connections for “5-lead” ECG, “12-lead” ECG, and respiration system applications. These schematics show examples of the use or non-use of the circuits for sleep mode hardware shutdown, chest-“lead”-present detector, pacer detector, and two types of ECG input filters. Applications information about the schematics follow the schematics.

ECG AmplifiersThe ASIC has five ECG inputs (EIN1-EIN5) and four outputs (ECGO1-ECGO4). Each input is connected to a simple on-chip passive low-pass filter to reduce the effects of high-frequency noise and interference. Analog multiplexers are used to select the desired combination of inputs to be processed in various modes of operation. The outputs are generated by four instrumentation amplifiers, each having a fixed gain of 8. The entire signal path is dc-coupled from input to output.

In a “5-lead” application, the five inputs correspond to Right Arm (RA), Left Arm (LA), Left Leg (LL), Chest (V) and Right Leg (RL) electrodes. An averaging block derives the common-mode value (RA+LA+LL)/3 required to process the Lead V vector. The instrumentation amplifiers then generate the three appropriate output vectors for leads I (or II, switchable), III, and V. The fourth output (ECGO4) is not used in this mode and the corresponding amplifier is powered down.

In “3-lead” applications, the V connection to the patient is not used. The RL connection may or may not be used as described below. The circuits for ECGO3, ECGO4, and the averaging of RA, LA, and LL are disabled.

For a 3 or 5-electrode system, all six vectors which are determined solely by electrodes RA, LA, and LL can be derived from any two of Leads I, II, and III (see the Derived ECG Vectors subsection of the Applications Information section, page 61). If both of these two vectors were permanently selected, a fault condition of the LL electrode that is shared by those two vectors could prevent all ECG monitoring. This is true even while having good connections to the remaining two electrodes. To guarantee monitoring capability of the vector defined by any remaining two of these three electrodes, the ASIC’s ECGO1 channel was made selectable between Leads I and II. (Loss of any of these 3 electrodes naturally prevents monitoring of any Lead V vector; the ability to monitor with just two electrodes requires the use of a cable with an internal RL-LL short; one of the two electrodes must be LL.)

In “12-lead” (10-electrode) applications, two identical ASICs are used. The inputs and outputs of the first (Primary) ASIC are the same as the “5-lead” case, except that input RL is replaced by input from the second chest electrode V2 and a fourth output vector, Lead V2 is generated. Also, the common mode value (RA+LA+LL)/3 is made available at output AVG3O of the Primary ASIC. The second (Secondary) ASIC is connected to the four remaining chest electrodes (V3-V6) and to lead RL. It generates the four corresponding output vectors Leads V3-V6. Here the common-mode value (RA+LA+LL)/3 required for the driven lead is obtained through pin AVG3IN connected externally to output AVG3O of the Primary ASIC.

The instrumentation amplifiers amplify the difference between two selected electrodes (or between a selected electrode and a selected average of other electrodes), while rejecting the common-mode signal as much as possible and maintaining high signal-to-noise (S/N) ratio. The amplifiers provide a constant, well-defined gain in the bandwidth of interest.

The amplifiers also have a programmable offset capability, resulting in a wider overall input dynamic range. Two bits are used to control the presence or absence of this offset and its polarity when enabled. The nominal input-referred offset can be set to 0V, -230 mV, or +230 mV using this approach. (A ±230 mV nominal offset is used instead of ±200 mV so that even with device fabrication tolerances, the ASIC can still accommodate up to ±500 mV input offsets. The indicated ranges are based on an A/D input voltage range of ±2.5 volts.)



120.26084 Rev. 2 Copyright © 2001

The offset capability will not often be used by the majority of the expected users of this ASIC, since the AD7716 A/D can handle with no discontinuities the entire ±300 mV range required by AAMI, etc. The offset feature is included for those users that might, at least occasionally, need to tolerate offsets greater than ±300 mV.

Two conditions that might benefit from use of the ASIC’s offset capability are sustained offset caused by cardiac pacing from (external) body surface electrodes, and the offset transient that follows defibrillation. In the case of a defibrillator discharge transient, having an increased offset range can allow an earlier look at the patient’s ECG to see if the defibrillation or cardioversion was successful. Both of these situations can be an issue, even while using silver/silver chloride electrodes. (See Dealing With ECG Offset, page 61.) Offset conditions which likely will not benefit sufficiently from the ASIC’s offset capability occur when electrode types that are not silver/silver chloride are used. (See Electrode Offsets Versus Electrode Type, page 19.)

The lead fail detection thresholds of all electrodes used by an ASIC are increased while any single ECG offset in that ASIC is enabled because a 500 mV electrode offset might otherwise exceed the (480 mV) lead fail detection threshold all by itself (particularly if a grounded reference electrode is used).

The various modes of operation and appropriate input lead selections are set through the serial interface.

Reference Electrode Drive Circuit and Issues(Note that the Self Test Diagram on page 64 is helpful for study of the Reference Electrode Drive circuitry below.)

The Reference Electrode Drive (“lead-drive”) Circuit establishes a common mode reference point for the ASIC’s differential amplifiers and for its lead-fail detection circuits. It also acts as a current sink for the other electrodes’ lead-fail detection currents. Without that current-sinking action, all the signal electrodes would be indicated as faulted, even if they were all connected to the patient. Any electrode that is attached to the patient may be selected as a reference electrode. Control bits LD1OR2, LDR0, and LDR1 select this electrode. When the Reference Electrode Driver is connected to an electrode, that electrode may either be actively driven by an amplified, inverted, common mode average of the voltages present on a selected choice of signal electrodes, or it may be “grounded”.

Via control bits LDIN0 and LDIN1, an input multiplexer selects the appropriate common mode input from the available values CM1OR2, CM3, and AVG3, as described later in the discussion of the LDR control register. In “3-lead”, “5-lead”, and in the Primary chip in “12-lead” systems, CM1OR2 = (LA+RA)/2 if the LD1OR2 bit in the LDR register is LO, or (LL+RA)/2 if that bit is HI, and CM3 = (LL+LA)/2. In “5-lead”, and in the Primary chip in “12-lead” systems, AVG3 = (RA+LA+LL)/3. (In “12-lead” applications, the Secondary ASIC receives its AVG3 input from the Primary ASIC.) The selected common-mode input is buffered by an internal operational amplifier. The result is made available at the CMOUT output pin for connection to external passive components which, together with a second internal op amp, set the loop gain and compensation time-constants for the reference electrode feedback loop. Placing the components required for this outside the ASIC allows freedom to modify the time-constants and/or loop gain needed in a variety of user applications.

Reference Electrode Disconnect, Active Drive, or GroundingSince in a "12-lead" system all electrode connections to its Primary chip are for signal inputs, it is necessary to disconnect the Primary chip’s Reference Electrode Driver from all the Primary chip’s electrode inputs. This is done by setting that chip’s control bit LDOPN = 1.

In general, while a chip’s LDOPN = 0, its Reference Electrode Driver is connected to the selected reference electrode, which will be driven in response to the selected common mode source if control bit LDROFF = 0, or that reference electrode will be grounded if LDROFF = 1. LDROFF being HI disables the Reference Electrode Driver and CMOUT amplifier, thus saving a small amount of power. It is appropriate to use this mode while putting the chip in its sleep mode, so that the lead fail detection system (which cannot be disabled) will still function, but will take only minimum power.



Copyright © 2001 120.26084 Rev. 2

In the 12-lead schematic (page 41), both ASICs are shown with fully functional reference electrode drive circuits so that any electrode may be selected as the reference electrode. For “12-lead”-only operation where only RL (or V3-V6) would ever be the choice for the reference electrode, R14, R15, R17, and C22 may be removed. In this case, short together pins 10 and 11 of U1, and leave pin 9 unconnected.

The negative feedback employed by a driven reference electrode scheme gives better dc common mode rejection than a grounded scheme. It forces to zero (from the perspective of the differential amplifiers) the average of the voltages on the signal electrodes used by the selected common mode source. A driven reference electrode scheme also eliminates any problems of excess offset developed by the reference electrode itself with respect to the patient. In circumstances where electrode offsets are high, both offset benefits could prevent a false lead-fail indication, since the lead-fail detection thresholds are relative to “ground”. For these reasons, it is preferable to actively drive the reference electrode, as opposed to grounding it. In most cases, this results in the following design scheme: “Actively drive RL if RL is truly a separate electrode and it is connected to the patient. If there is no RL, but there is a V electrode and it’s connected to the patient, then actively drive V. In either case, use AVG3 as the common mode source.”

Reducing 60 Hz InterferenceBesides being required to make the lead fail detection system work correctly, and (if used for active drive) to center electrode offsets, the reference electrode serves to significantly reduce the amount of 60 Hz interference in the ASIC’s ECG outputs. Most 60 Hz noise in a patient’s vicinity is of a common mode nature. However, due to various imbalances in the ECG system’s differential amplifiers and their input circuits, a small portion of that common mode interference gets converted to a differential signal. However, the biggest contributor to imbalances is often the differences in contact impedance of the individual ECG electrodes, and the fact that those impedances must drive the non-infinite impedance of ECG input filters and differential amplifiers. If the magnitude of 60 Hz difference between the electrodes and the ECG circuits’ supply common ("isolated ground") can be reduced, then from the differential amplifiers’ perspective, their 60 Hz common mode voltage is reduced. By reducing the common mode 60 Hz content, a reduced magnitude of it will be converted to differential interference.

Generally, the best way to reduce the 60 Hz voltage difference between the electrodes and the ECG circuits’ supply common is to provide a low impedance path between the ECG circuits’ supply common and the patient. (In terms of order of magnitude, such a connection drops the voltage in question from volts to tens of mV.) For best results, this should be done through an additional electrode connection to the patient – an electrode connection that is not also used for a signal connection.

To explore the reasons for the previous sentence requires examining the pertinent parts of the test circuit that is used for Section 3.2.9.10 of EC13 and other standards’ CMR testing. For the sake of discussion, assume initially that the LL electrode is used as a "grounded" reference electrode. See the following figure.

NOTE: The CMR test defined by EC13 is specifically defined as being done with all electrode inputs tied to the test circuit. In the case of a 5 (or more) electrode system, the RL reference-only electrode will be connected, and the following discussion does not apply. What it does apply to is the use of 3-electrode ECG cables in systems that must generate more than one ECG vector at once.

The dominant current path to earth ground from the CMR test fixture’s 10 VRMS/200 pF 60 Hz source is through the R3/C3 parallel network, to iso supply common through the ASIC’s reference "grounding" impedance "Rgnd", and lastly through the monitor’s isolation capacitance "Ciso" to earth. So long as Rgnd is much lower than the shunt impedances to iso common provided by the ECG cable’s wire-to-shield capacitance and by the capacitors in the ESIS filters, and much lower than the series impedances of Cin and Ciso, this relationship is fundamentally independent of the shielding of the ECG cable per se, and of the ECG circuits. In EC13’s test setup, the only variable even remotely under the control of the circuit designer is the ECG circuits’ isolation capacitance to earth. Reducing the latter is accomplished in part by reducing the total volume and surface area of the ECG circuits, and including the largest possible iso barrier space around them.



120.26084 Rev. 2 Copyright © 2001

Common Mode Rejection

Line-operated monitors must use power supply transformers and optoisolators with the lowest possible capacitances across their patient isolation barriers. Battery-operated portable monitors must be surrounded by the thickest tolerable enclosure of material having the lowest dielectric constant one can find. For isolation capacitances to earth of 50, 100, and 200 pF, the voltages dropped across the R3/C3 network are respectively about 15.4, 25.7, and 38.5 mV peak-peak. Certainly, all of these are manageable net common mode voltages for Lead I’s differential amplifier. (Without going into further detail, actively driving LL instead of grounding it will lower these voltages with respect to iso common by a factor of roughly two.)

Now consider trying to use LL to develop a Lead III signal. The isolation capacitance must drop below 2.6 pF to keep the 60 Hz voltage drop across R3/C3 below 1 mV peak-peak. 1 mV peak-peak is the upper limit for input-referred 60 Hz content allowed by EC13. Note that some additional margin is required for the less-than-perfect common mode rejection of real differential amplifiers. No practical circuit of this configuration with LL grounded will pass EC13’s CMR test except in Lead I. (Nor does it need to, as described in the previous note.)

Note that in the above example, if LL were "grounded" at the node between LL’s ESIS filter and the Lead III differential amplifier’s LL input instead of at the LL electrode, the 60 Hz voltage drop between the right hand side of Cin and the LL amplifier input would be much greater than the numbers listed above. This is because the series impedance of LL’s ESIS filter is then added to the net impedance of R3/C3, and the voltage drop in LL’s ESIS filter contributes to the net voltage difference between LL and either RA or LA. Alternatively in a 3-wire AAMI ECG cable, the LL electrode may be grounded through the cable’s RL-LL short plus the series impedance of RL’s ESIS filter. In the latter case, the added voltage drop contributes to an increase in the common mode voltage seen by all differential amplifier inputs, but does not significantly increase the differential voltage between any of them.



Copyright © 2001 120.26084 Rev. 2

Hypothetically, if instead of being driven or grounded, the RL-LL short were to be (externally) tied to a suitably large resistor to a minus supply so that all electrodes were held at nearly ground potential, the 60 Hz interference currents from the CMR fixture would be more equally divided among the CMR fixture’s networks for RA, LA, and LL. In such a design, the largest portions of the 60 Hz interference currents would flow through the wire-to-shield capacitances of the ECG cable, and progressively less current would flow through the capacitors of the ESIS filters and resistor to minus supply. Because the total interference current would then be more equally subdivided, this would yield lower 60 Hz content across any individual electrode network in the CMR fixture. As a result, 60 Hz content in each ECG output during the CMR tests would also be lower, but results would still greatly exceed EC13’s CMR test limit. Note also that part of the CMR test requires selective shorting of each electrode network (like R3/C3) in the CMR fixture, to cause deliberate imbalanced conditions. Even if all the ASIC’s lead fail detection currents were able to be disabled, lead fail detection was dispensed with entirely, and no reference electrode connection was made at all, EC13’s CMR test would fail. Furthermore, no presently-existing ECG performance standard includes an ESIS test method or requirement, but ESIS performance for all vectors but Lead I will suffer considerably if an RL-LL short is used to provide a reference connection.

To obtain good EC13 CMR test results (or for that matter, good ESIS performance) with a 3-wire cable requires restricting the available ECG outputs to just one vector - namely Lead I, Lead II, or Lead III - and forcing the reference electrode in each case to be the one electrode not used in the desired single vector. Best results will be obtained if that reference electrode is driven rather than grounded. All this must be clearly understood for best design results.

Having stated all this, it is next appropriate to explore why a designer may choose to use a reference electrode connection through a 3-wire cable’s RL-LL short, despite the problems it causes.

1. Many monitoring applications can benefit from being able to obtain or derive a total of 6 ECG vectors from 3 electrodes instead of just one vector.

2. Recall that the ASIC’s differential amplifiers have a gain of 8, and the specified A/D used to digitize those amplified signals has a +/- 2.5 V dynamic input. Thus, the system hardware theoretically has sufficient dynamic range to handle up to 26 mV peak-peak 60 Hz signals on top of +/- 300 mV dc offset during the EC13 CMR test. (If the gain of the ASIC or A/D is slightly high, this range is reduced slightly.) If the software that deals with the ECG signals (including the software notch filters) is properly designed so that it cannot saturate or roll over, then the entire system can truly deal with large interference signals. If no part of the system saturates, the system should be able to remove enough 60 Hz to be left with usable signals. Some telemetry systems do just this when using 3-wire cables.

3. Ambulatory ECG monitoring, whether or not its ECG data is transmitted or stored for later usage, brings up the third item. ANSI AAMI EC38:1998 is the standard for ambulatory electrocardiographs. While EC38 and EC13 (and EC11) all use basically the same fixture design for their respective CMR tests, EC38’s CMR performance requirement is "at least 60 dB rejection at line frequency and at least 45 dB rejection at twice line frequency, both tested with any notch filters enabled". The CMR requirements of EC13 and EC11 amount to at least 89 dB rejection at line frequency only, and use of notch filters during the testing is not discussed. (Note that the upcoming revision of EC13 is expected to include a requirement to disable any notch filtering during EC13’s CMR tests.) Finally, note that ambulatory devices spend most of their operating time in a pouch that has very good capacitive coupling to the patient, and very minimal capacitive coupling to earth ground.

It is outside the scope of this manual to declare whether or not the above rationale is acceptable from a regulatory perspective. However, if this approach is taken with a system that never uses more than three electrodes, but which uses two ASIC outputs simultaneously, it seems reasonable to expect that such a unit’s specifications need to disclose its real CMR performance and how that compares with EC38’s CMR test requirements, and include the rationale behind choosing to do so. Alternatively, a manufacturer may need to restrict the device to use with 5-wire cables, or to provide only one selectable vector when used with 3-wire cables. (Note that using a 5-wire cable with only RA, LA, and LL connected inherently forces the latter restriction.)



120.26084 Rev. 2 Copyright © 2001

Limitations in 60 Hz ReductionFor best reduction of 60 Hz common mode interference, a reference electrode driver needs to apply 60 Hz to the reference electrode with a phase exactly opposite to that of the phase of the 60 Hz present on the patient. The patient’s 60 Hz driving through the electrode impedances into the patient cable’s capacitances introduces some phase shift in the common mode signal obtained from the ASIC’s differential amplifiers and used to feed the driving amplifier. The ESIS filters add a little more phase shift to that incoming common mode signal. On its way back to the patient, the signal intended to drive the reference electrode picks up further phase shift as it goes back through an ESIS filter, and still more due to the low pass filtering action of the ESIS filter’s resistance feeding the cable’s capacitance. Finally, in order to stabilize the reference-electrode-driving amplifier, the latter must have some high-frequency rolloff of its own. This further slows down the loop response back through the reference electrode.

All of these phase shifts between the interfering 60 Hz and the 60 Hz applied to the driven electrode somewhat limit how much common mode rejection benefit a driven reference scheme offers over a grounded reference scheme. (The 60 Hz software notch filter that is almost always present in modern ECG systems should have little difficulty dealing with the remaining 60 Hz with either reference electrode scheme. In tests with circuits like those in the “5-lead” application schematics with the notch filter off, using typical patient cables and always with RL as the reference electrode, the driven scheme improved the 60 Hz common mode rejection by about 2 to 2.5:1 over a grounded scheme. Comparisons with other implementations may vary.)

Electrode Offsets Versus Electrode TypeWith present-day silver/silver chloride electrodes, electrode offsets are usually low enough that they are in little danger of exceeding either the maximum allowable dc input offset specifications or the lead fail detection threshold. However, neonatal ECG monitoring applications sometimes use sets of stainless steel needle electrodes, whose offsets are not only high, but which often drift quite erratically. Also, 12 Lead ECG monitoring is sometimes done with suction cup electrodes (which usually have a rubber squeeze bulb attached to a silver-plated brass hemispherical cup). After their silver plating wears off, these brass cup electrodes can have large offsets. It is noteworthy that EC13 Section 3.1.2.2 , Part (d) requires "a clear warning that electrodes of dissimilar metals should not be used unless the cardiac monitor can handle polarization potentials as high as 1 volt". Offsets from any of these electrode types may be high enough to cause false lead fail indications, despite use of the ASIC’s offset capabilities, particularly with a grounded reference electrode.

(Note that regardless of which reference electrode scheme is used, the reference electrode’s dc offset with respect to the patient will likely be larger than the offsets of the signal electrodes. This is because the reference electrode must sink the sum of the lead-fail detection currents of all the attached signal electrodes. The more signal electrodes that are attached, the higher the offset of the reference electrode. A driven reference electrode scheme’s dc feedback eliminates any problems with this higher offset.)

ECG Cable IssuesThis subsection applies only to 3-wire ECG cables whose instrument connector may also accept 5 (or more)-wire ECG cables. For reasons listed in the Reducing 60 Hz Interference subsection on page 16, it is advantageous to include an added short between the instrument connector’s pins for RL and LL.

Such cables allow two valid ECG vectors to be monitored, and from those two, four more may be derived by software. If LL, and only RA or only LA, are connected to the patient, it is still possible in this manner to monitor the single vector that uses LL and that other electrode. See the Chest-Lead-Present Detector section (page 22) for a description of how to identify this type of cable.

Note that to take advantage of such an RR-LL short, the short must be in the ECG cable plug. The short cannot readily be added via a semi-conductor switch (or even a relay) on the ECG circuit board, because neither of these can withstand the high voltages present during defibrillator discharges.

Yet another alternative for use with 3-signal electrodes is a 4-wire cable with RL as a dedicated reference electrode, and no RL-LL short.



Copyright © 2001 120.26084 Rev. 2

Lead-Fail Detection FunctionThe Lead (Electrode)-Fail Detection function implemented on the ASIC includes low value (nominally 70 nA) dc current sources connected to the input electrodes. If an electrode is disconnected, the current source pulls the corresponding input node towards the VDDA supply. The current source connected to input EIN5 is gated by control bit RLPUP/ which is set by software in the lead-fail control register. This allows the pull-up on RL to be disabled when a “3-lead” cable is used, thereby preventing a doubling of the pull-up current on LL if the ECG cable plug pins for RL and LL are shorted together (as in the AAMI standard “3-lead” ECG cable). Note that RLPUP/ must be LO (for V2) for the Primary ASIC in “12-lead” applications.

Five identical blocks filter and measure the dc offset for each electrode and set a flag in a register if this offset exceeds a predefined value. The input section of this circuit includes a passive low-pass filter (which rejects high-frequency noise and prevents aliasing), followed by a 7 Hz first-order switched-capacitor (SC) low-pass filter which helps remove 50/60 Hz line noise. A backup oscillator is enabled by control bit LFOSC. It provides the clock required to continue operating these SC circuits when the external clock source (in this case from the external sigma-delta converter) is powered down. The output of the SC filter, predominantly a dc value, is compared with a threshold level. The resulting logic value is stored in one of five locations in a register. Note that all 5 lead-fail indication bits are always active and functional, independent of the choice of “3-lead” mode, “5-lead” mode, “12-lead” mode, etc. The comparator used has built-in hysteresis to prevent undesired chatter, and also has an adjustable threshold. The nominal input-referred rising threshold is set at 0.48 V when all ECG amplifiers are set in the zero offset mode. Programming any of the ECG channels with a nonzero offset automatically raises the rising threshold of all the lead-fail comparators to nominally 0.73 V. These values are for positive-going transitions in the input electrode potential. For falling transitions (high to low), the built-in hysteresis reduces each of these thresholds to approximately 84% of the value of the rising threshold. Note that all of these thresholds are relative to ground.

The outputs of the lead-fail comparators are connected to a logic block which contains exclusive OR gates and latches to process the electrode connection status. The logic block generates an output LDCH/ when the status of any electrode changes. The lead-fail status latch that is included in the LFS register always reflects the current electrode conditions. Reading the LFS register via the ASIC’s serial interface always causes output pin LDCH/ to go HI. Any change in the connection status of the 5 ECG electrodes will cause LDCH/ to go LO until the LFS register is read again. The LDCH/ output is held at a HI level during a read operation, thereby preventing any concurrent changes in electrode status from causing additional interrupts during this time.

There are two different categories of speed requirement for the response time of the ECG lead fail detection system. One category needs fast response, but can accommodate some uncertainty. The other category needs more accurate response and can accommodate greater processing delays to achieve that better accuracy.

Applications that use the ASIC to get trigger information for synchronizing an external action to each heart beat (e.g. cardiac balloon pumps, defibrillators in synchronized cardioversion mode, demand pacemakers, etc.) need to know as soon as possible when an electrode comes unhooked so they can prevent an unwanted action or reaction. This is true even if the exact status change may not settle out until a bit later. Those applications almost certainly need to react as soon as LDCH/ goes LO. If there is any problem with the actual electrode connection status, the system can ignore a few beats until it resolves the problem.

The other group of applications deal with what the system should do when it loses monitoring capability and has to give an equipment alert for lead fail, or declare certain vectors invalid (hence affecting their availability as sources for pacer detection, QRS picking, common mode source, and individual electrode’s availability as a reference electrode, etc.). For these circumstances, it is acceptable to have a longer interruption in the trace and data stream in exchange for elimination of “stuttering” in the control response if the condition is erratic for a short time. The 7 Hz low pass filters in the lead fail detectors remove all ambiguities in electrode connection status for all interferences but one – defibrillator discharges.



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While the 7 Hz low pass filters in the lead fail detectors do an excellent job of dealing with large amounts of 50/60 Hz pickup on floating lead wires, there is still a reason to require software debounce on the lead fail status before acting upon a change in it. The issue is what happens during a defibrillator discharge. The voltages at the ASIC inputs during a defibrillator discharge WILL be high enough for a long enough time to trip the lead fail detectors (and the chest-lead-present detector as well).

This behavior would occur even with a lead fail detector that contained a theoretically perfect, linear, 7 Hz low pass filter and comparator, both with infinite dynamic range. During a defibrillator discharge, the voltages at EIN1-EIN5 are rapidly pulled to (and beyond) the ±5V supply rails. For the output of a single-pole, 7 Hz low pass filter to swing from an initial voltage of zero to 0.48 V under these conditions takes less than 2.3 msec. Using the defibrillator test circuit from EC13 (and other standards) yields a discharge time constant of about 3.5 msec.

Actual defibrillators may use larger capacitor values than EC13’s circuit in order to guarantee 360 joules are delivered to a low impedance patient. 40 uF has been observed. This increases the time constant to 4 msec. The IEC (the worst case) defibrillator withstand test develops a peak voltage across its 100 ohm load resistor of 4.5 kV. Assuming a real world capacitor value of 40 uF, a decay time constant of 4 msec, and a final value of 0.4 V (lead reconnection threshold) at the electrodes, this takes about 37 msec for a 10-electrode (worst case) system. However, for a driven reference electrode (at the ASIC pin itself) to drop below 0.4 V, the (~dc) gain (21.5X) of its driver must be considered as well. That consideration requires all electrodes of the selected common mode source to fall below 0.4/21.5 volts during the defib test. This takes a total of about 50 msec. To a first-order approximation, the 7 Hz lead fail low pass filters take an additional 57 msec to settle to the lead reconnection threshold. (For reference, the chest-lead-present detector settles faster than this.) Practically speaking, the system software should probably allow a minimum debounce interval of at least three to four times this 107 msec total (321 to 428 msec) due in part to the lingering voltages that are contributed by dielectric absorption effects in the defibrillator’s storage capacitor (at least for the duration that the defibrillator’s discharge relay is held closed). Besides its being insignificant in most applications, this additional delay should ensure that the monitor passes all defibrillator recovery tests without triggering an automatic ECG vector change in response to a "failed" electrode.

On the subject of delays, note that certain patient simulators can cause a delayed (~10 sec) return of an ECG trace following reconnection of a disconnected electrode. (This is different than delayed detection of a reattached electrode.) For example, at least some models of Dynatek patient simulators have a sort of capacitive coupling of their ECG outputs, although all ECG signal outputs have a 1 Mohm resistor to RL. (Such capacitive coupling necessarily has a long time constant to be able to adequately pass ST segment information.) This arrangement allows the common mode voltage of the simulator’s ECG outputs to float with respect to the common mode output voltage of the simulator’s IBP outputs, etc. With these simulators, all of the connected signal electrodes will be about 70 mV above RL due to the ASIC’s 70 nA lead fail detection current flowing through each of the simulator’s 1 Mohm resistors. Disconnecting a signal electrode will cause the voltage at that electrode to settle to the voltage of the RL electrode. Reconnecting the previously-disconnected electrode causes it to charge back up to 70 mV above RL. It is this latter charging that requires extended settling time. With these input conditions, such settling behavior will be observed whether the reference electrode is grounded or driven. This settling delay does not exist with simulators that have no ac coupling (or with a real patient).



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Lead Fail Detection ExampleThe ECG system cannot tell what electrodes are connected without driving (or grounding) a reference electrode of some sort – the reference electrode is the only path for sinking the lead fail detection currents below the lead fail detection threshold. While it looks like no electrodes are connected, the simplest approach is to use a grounded reference scheme, enable RLPUP/ in the (or both) ASIC(s), and first try using RL as the reference electrode (for a half second to allow the lead fail detector filters to settle). If no electrodes other than RL show in the LFS registers as being connected, it cannot yet be determined whether RL is the only electrode connected or whether RL is simply one of the electrodes not connected. To differentiate, try using one of the V ("C") electrodes as a grounded reference for half a second, then read the LFS registers again. If only this V electrode shows connected, try the same approach with another V electrode and then sequentially through all the electrodes that a given cable type is defined to have. The sequence order is not particularly important. Keep doing this sequence until any electrode besides the reference electrode indicates that it is connected. (Ignore as a reason for halting the sequence any intentional shorts between RL and LL, etc. that may be built into the cable.) When any second legitimate electrode shows as being connected, any subsequently-added electrodes will inherently show up in the LFS registers without further change of choice of reference electrode. Hence, keep that particular reference electrode as the reference, and keep polling the LFS register (or wait for an interrupt from LDCH/) until enough other electrodes show up as connected to be able to generate the simplest vector the ECG system will allow (like lead I, II, or III). Alternatively, with a 10-electrode cable, the system software may choose to not do anything else until at least RA, LA, LL, RL and one of the V electrodes indicate connection.

Due to normal variations in the electrode attachment sequence, there will be instances where RL is not first seen to be connected while other electrodes are connected (so one of the connected electrodes is chosen as the reference electrode). In those instances, it is important to have the ECG system continue checking to see if RL later becomes connected. If RL is later found to be connected, the system should switch over to using RL as the reference electrode so that additional ECG vectors can be obtained.

As part of the ongoing self tests, software should always verify that (after debounce) the reference electrode shows up as being connected. (This applies whether the reference electrode is driven or grounded.) If the reference electrode does not show as connected within 0.5 seconds after being selected, this constitutes an equipment problem, and the user should be alerted.

For ECG lead-fail detection to work during sleep mode, the selected reference electrode must be able to pull down on the signal electrodes through the patient. (Otherwise, there is nothing to pull a connected ECG input below the lead-fail detect threshold.) The Reference Electrode Driver amplifier itself cannot do this while it is disabled, but a FET is included to pull the reference electrode to ground then. Setting the LDROFF bit high in the EMD register powers down this amplifier and turns on that FET. As long as the LDOPN bit in the LDR register is not set, this path to ground is functional for the reference electrode. Depending on the application, it may be best to periodically change the choice of reference electrode to search for the first available combination of connected electrodes. While using a 3-wire cable that contains an internal connection between RL and LL, it always looks like these two "electrodes" are connected to each other, just as it does when not in sleep mode. The chest-lead present detector can sort out this connection, but not while in sleep mode. See Sleep Mode Issues (page 52) for power consumption tradeoffs of lead-fail conditions while not in sleep mode.

Chest-Lead-Present DetectorThe remaining function in the Lead-Fail Detection section is a chest-lead-present detector. (More correctly, it detects the presence in a patient cable of a wire whose intended connection is a “V” or chest electrode.) It is used primarily to confirm whether the chip’s RL lead-fail detection status bit (LF5) is correct. If a chest wire is present (whether it is connected to the patient or not), it is certainly in a cable that contains a distinct RL connection. Based on the answer to that question, it can then be determined if enabling the lead-fail detection current for RL will violate regulatory limits on current through an active ECG electrode (namely LL in this case).



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The “3-lead” ECG cables that meet the requirements of AAMI ECGC 5/83 are required to contain an internal connection between LL and the pin reserved for RL in “5-lead” cables that use the same style 6-pin connector. Other styles of “3-lead” ECG cables also contain this internal connection. Still other “3-lead” cables do not contain such an internal connection. The problem arises of how to distinguish between a “3-lead” cable that has an internal RL-LL short versus a “5-lead” cable that has RA, LA, LL, and RL connected to a patient, yet does not have its chest wire connected for whatever reason. In either case, the LF5 bit will show RL to be present if RA, LA, and LL are all connected to a patient (whether or not RL’s lead-fail detection current is enabled) and one of RA, LA, LL, or RL is used as a reference electrode. Somehow, the system needs to know what is really connected to what.

It is convenient to have the lead-fail detection current for RL be enabled so that if RL is connected after the ECG system has already chosen a reference electrode, it can still detect when RL gets connected. The system can then select RL as the reference electrode. If RL’s lead-fail detection current is disabled, then while RL is unhooked, the status of LF5 is indeterminate. However, there is a regulatory issue to consider which precludes always leaving RL’s lead-fail detection current enabled. As it is pointed out on page 79, the maximum allowable dc current that may be passed through an active electrode is limited (to 100 nA). If RL’s lead-fail detection current is enabled while a “3-lead” cable with an RL-LL short is in use, LL’s current becomes ~140 nA with this ASIC, and is in violation of ANSI/AAMI ES1 (see related documents section). The higher current would cause the LL electrode’s dc offset to rise faster and rise to higher voltages because of it.

In any ECG system that can guarantee no RL-LL (or RL-to-any other electrode) short will ever occur in its cable, NONE of the chest-lead-present detection system is required at all, and RL’s lead-fail detection current should always be enabled. (Be aware that companies like Fogg Systems make many varieties of adapter cables and substitute cables, so an alternative cable design might crop up after product introduction.) In any case, there is no reason to use any portion of the chest-lead-present detection circuitry in the Secondary ASIC in a “12-lead” system. See the Reference Electrode Drive Circuit section on page 15 for more details about the advantages or disadvantages of grounding versus driving the reference electrode.

How the Chest-Lead-Present Detector Works The chest-lead-present detector works by injecting an ac signal from CLPCLK through an external high impedance into the V (chest wire) pin of the instrument’s ECG connector, and having a comparator monitor the peak voltage swing injected into the V pin. The difference in capacitive loading at the chest wire’s terminal due to the presence or absence of the chest wire in an ECG cable affects the amplitude of this signal at the ECG connector. An amplitude greater than a certain threshold (set by an external reference) indicates a low capacitance, implying that a chest wire is absent. A lowered impedance may be caused by the capacitance between a chest wire and the cable shield, or by a conductive path through the patient, or both. If the peak swing at the comparator input is reduced by such loading, the comparator does not trip, and the CLP bit in the ECG lead-fail status register is high. A debounce circuit in the ASIC removes the 32 kHz content that would otherwise be present in that CLP bit.

The frequency of the injected ac signal is exactly half of that used by the ASIC’s respiration circuits, so that the latter’s synchronous detector output is totally unaffected by the signal used by the chest-lead-present detector. This is appropriate since a signal injected on the chest wire gets capacitively-coupled into the wires used by respiration, and could otherwise interfere with the detected respiration signal. Note that the CLP bit is indeterminate while CLKIN is not running, whether or not the ASIC’s internal lead-fail oscillator is running.

It is important to use the status of the CLP bit only at the particular instant in time when software is deciding what electrode is present to be used as a reference, rather than constantly monitoring it for changes. This is because the detector reacts quickly to peak swings above its comparator’s trip threshold, and reacts slowly to peak swings that stay below its trip threshold. Under these circumstances, a single noise spike (from ESD, for example), or multiple noise spikes (from electrocautery, for example) can cause the CLP bit to falsely go low for a time (up to 30 msec or so) even when a 5-wire cable is truly connected.



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The chest-lead-present detector must be able to distinguish between the total of the capacitive loading of the chest (V) electrode’s ESIS (or simple input) filter, capacitance of the instrument’s internal ECG cabling (if any), capacitance of the circuit board’s ECG connector, and other parasitic capacitances, and that total plus the capacitive loading of the ECG cable with the lowest expected capacitance.

Note that the sum of all non-patient cable loading effects can be significant relative to the loading effect of a short patient cable!

The trip point of the CLP comparator may be matched to the system’s needs by setting the dc voltage input at CLPIP, relative to one-half of VDDRSP. Note that the ac voltage at CLPIN will be centered inherently at VDDRSP/2. This is because it is dc-coupled from CLPCLK which swings from 0 V to VDDRSP and it has a 50% duty factor. Ideally, CLPIP’s dc voltage is set at a level that is centered between the peak CLPIN voltage while no cable is attached, and the peak CLPIN voltage while the lowest capacitance cable is connected to the instrument but not to the patient. Because of the high impedance and dc level of the signal at CLPIN, the loading effect of a 10 MΩ scope probe causes too great an error (particularly dc) when trying to directly observe this signal.

Also, the signal applied to the CLPIN input of the comparator has a basically triangular waveshape, and when only brief tips of that triangle exceed the level on CLPIP, the comparator may not respond (due to its finite gain and response time). The most accurate method of determining the required level for CLPIP requires setting up the system so that the status of the CLP bit may be monitored more or less continuously, and temporarily making CLPIP be easily adjustable between 2.5 V and the level of VDDRSP. Monitor the dc voltage at CLPIP. Then, with no cable plugged into the instrument’s ECG connector, determine the trip threshold for CLPIP. Next, with the lowest capacitance ECG cable plugged into the instrument, determine the new trip threshold for CLPIP. Pick suitable fixed resistance values to set the final value of CLPIP at the point midway between these two trip thresholds.

If VDDRSP and the other +5 V supplies are derived from the +2.5 V reference as recommended in the power supply discussion, the CLP threshold accuracy is greater if the CLPIP’s voltage is developed by a voltage divider between VDDRSP and the +2.5 V reference, rather than by a divider between VDDRSP and ground. Note that depending on the design of the actual +2.5 V reference used, it may be necessary to limit the current through this divider to less than the sum of the minimum currents supplied to ground through the reference’s other loads. Alternatively, if the reference cannot sink current, or if its minimum load current to achieve regulation is greater than the sum of its existing loads, it may be necessary to add a suitable load resistor between the reference’s output and ground to maintain the needed minimum loading.

If the Chest-Lead-Present Detector’s function is not needed, connect its pins as shown in the 12-lead application schematic.

Pacer Detector CircuitThe Pacer Detector Circuit is based on a proprietary self-adapting scheme. One of the four ECG channel outputs is selected by a multiplexer that is controlled by two select bits, PDLS0 and PDLS1, and fed to the pacer detector.

WARNING: It is the responsibility of the manufacturer integrating the ECG ASIC into a host system to make sure that the pacer detector’s selected source is only allowed to be an ECG channel which is enabled by the ECG mode bits (MODE0 and MODE1), and which makes use of no electrodes that are not connected.

The Pacer Detector Circuit contains switched capacitor filters whose characteristics facilitate distinguishing pacer pulses from environmental noise pulses and from QRS complexes generated by the heart. The detector includes a full-wave rectifier to deal equally well with pacer pulses of either polarity. A comparator checks the peaks of the filtered signal relative to a threshold level.



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It is important to note that it is the filtered signal which is compared against the comparator’s trip point. This filtering attenuates pulses with widths progressively more narrow than 0.2 msec to a progressively greater degree. In the discussion below, note the distinctions between input-referred pulse amplitudes and filtered pulse amplitudes.

Three Modes of Operation for the ComparatorThe comparator has three modes of operation:

1. Nonadaptive, with a fixed input-referred threshold that detects ≥ 3.0 mV pulses of 0.1 msec pulse width, and ≥ 2.0 mV pulses of 0.2 to 2.0 msec pulse widths.

2. Adaptive, with an adjustable input-referred threshold limit that detects ≥ 3.0 mV pulses of 0.1 msec pulse width, and ≥ 2.0 mV pulses of 0.2 to 2.0 msec pulse widths in the absence of noise pulses whose filtered pulse amplitudes exceed the filtered pulse amplitudes of these pacer pulses. For systems which limit the pacer detector mode of operation to just one choice, this mode provides the best overall choice.

3. Adaptive, with no intentional lower bound on the input-referred threshold (i.e., the threshold is effectively set by the noise level).

NOTE: Be aware that narrow QRS complexes from some neonates may trigger the pacer detector in this third mode.

These modes are set by the control bits ADPT and THMIN. The fixed threshold is proportional to the 2.5 V reference applied to the ASIC. The adaptive threshold is obtained by detecting the peak value of the filtered input signal or noise spikes and setting the threshold slightly higher than this filtered peak value. An external RC network (connected between pins PDCAP and PDFB) holds the peak-adjusted threshold level and slowly decays this level between input pulses, so that the detection threshold returns back to a low level by the end of a normal A/V sequential pacing period. For faster input pulse repetition rates (e.g. due to noise spikes that occur at two times the line frequency), the adapted threshold does not have enough time between consecutive pulses to decay appreciably. Therefore, the detection threshold for pacer pulses is forced to be slightly higher than the filtered peak amplitude of the noise pulses.

Under these conditions, and up until the adaptive circuits saturate, only pacer pulses with filtered peak amplitudes greater than the filtered noise peak amplitudes will cause an output from the pacer detector comparator. Although performance is not included in the specifications, for 50 µsec-wide pulses at 120 Hz into the 2-stage ESIS filter, the detector in either adaptive mode will typically pick an occasional pulse at 14-17 mV referred to input, and generally pick all pulses ≥ 18-40 mV referred to input, depending on polarity. The non-adaptive input-referred threshold for these 50 µsec-wide pulses is about ±5.5 mV.

The adaptive feature of the pacer detector is best at rejecting noise pulses that are of fairly consistent amplitude. (Most line-frequency-related noise spikes are like this.) Noise spikes during sparking of electrocautery are not only more random in amplitude, but may have time intervals between spikes that are long enough for the adaptation to decay. Therefore, it is not realistic to expect the adaptive feature to eliminate false pacer detector trippings during electrocautery.

Also, there is a non-zero response time required for the detection threshold to adapt. The adaptation time depends on the amplitude, width, and time separation of the offending noise spikes. Practically speaking, this means that several spikes may trip the detector before adaptation is complete in instances where noise spikes occur in bursts separated by more than 50 msec or so.

The PDCMPIN pin is a connection to one of the pacer detector’s comparator inputs. There is an internal smoothing capacitor connected to this pin. It is important to prevent capacitive coupling of external digital signals into this pin.



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Pacer Detector Output PDETOPDETO is the output of the pacer detector. In general, the host system’s ECG processor must respond immediately to PDETO to reject pacemaker pulses and their overshoots, and prevent them from being counted as heart beats. To help accomplish this, the rising (leading) edge of PDETO may be used to trigger a fairly high-priority interrupt to the ECG processor. Those users desiring to use PDETO to generate an interrupt should be aware that PDETO’s logic HI=VDDA, not VDDIO. Alternatively, some sigma-deltaA/D converters allow for a digital signal input which PDETO may drive. This digital signal is then embedded in the data stream of the converter’s output along with the A/D conversion value. (The AD7716 converter includes this feature. In the AD7716, DIN1 gets latched into the AD7716’s output register right before its DRDY/ goes LO true.)

This allows tight coupling of the pacer detector output with the first waveform conversion result that is certain to be corrupted by a pacemaker pulse. This coupling is achieved without using an interrupt line. The duration of a PDETO output pulse is stretched by the ASIC to be longer than the expected A/D conversion update interval in the ASIC’s intended applications, so that at least one sample is always flagged with the pacer detection status.

The user should be aware that all pacer pulse detectors have some amount of delay before indicating a pulse is detected. Because of that delay, some corruption may occur in the ECG data conversion sample prior to the pacer detector’s response. Therefore, whether the signal processing system uses a digital input to the A/D converter or an ECG processor interrupt, the system should not consider an ECG sample to be uncorrupted by pacer pulses until the next sample following it does not contain a pacer detector flag. (This causes the display–or other use–of ECG samples to be one sample behind, but that delay is insignificant.)

Pacer Pulse Detection IssuesOne of the two main reasons for using a pacer detector is to tell an ECG system that includes a heart rate meter “function” that a pacer pulse has occurred, and the rate meter shouldn’t count the pacer pulse (or more likely its overshoot) as a heart beat. The second main reason is to discern if a patient’s implanted pacemaker is working properly. For both reasons, the detector must be capable of determining when an actual pacer pulse has occurred and must somehow notify the user. Be aware that from the rate meter perspective, if a pacer pulse in a given ECG vector is too small to be detected, then its overshoot is too small to be counted as a heart beat. (The “area under the curve” in an overshoot cannot exceed the area under the curve of the main pacer pulse, since the pacemaker itself capacitively-couples the pulses. That capacitive coupling creates the actual overshoot.) Following are items that affect the amplitude of pacer pulses at the body surface, and thus their likelihood of being detected.

The monitored ECG vector and the pacer pulse’s electrical vector may be orthogonal to each other through the patient’s body. If so, there will be very little, if any, of the pacer pulse present to be detected in such an ECG vector. If a multichannel ECG system’s only pacer detector is assigned to an ECG vector which is orthogonal to the pacer pulse’s vector, and a second ECG vector that is more nearly parallel to the pacer pulse’s vector is used without benefit of pacer detection, a problem arises. Under these circumstances, pacer pulses and their overshoots can be large enough in the second ECG vector for them to be falsely counted as heart beats, yet no pacer detection is given. To deal with this possibility, some 5-electrode multi-channel ECG systems include a pacer detector permanently dedicated to each hardware-derived vector they offer (usually three).

No matter how many simultaneous ECG vectors have dedicated pacer detectors, there will always be monitored patients (and not just a rare one) on which the pacer pulses are not reliably detectable due to low pulse amplitude at the body surface. Therefore, the clinical users must inevitably be prepared to deal with situations where pacer pulse detection is uncertain. Contributors to this include (at least) the design and settings of the pacemaker, the implant location of the pacemaker if it is a unipolar type, the location and contact impedance of its implanted electrode(s), the location of the monitoring electrodes, how much body surface fat or scar tissue, etc., underlies those electrodes, and the ECG vectors used.



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While having a detector per channel improves the chances of detecting real pacer pulses, it also carries liabilities. The most notable liability is how to decide which detector output(s) to use. (For telemetry systems, this decision perhaps must be made at a central station, if it is not made in the monitoring device.) The outputs of detectors on invalid channels (ones without enough electrodes connected to develop the intended vector, or ones with an electrode that has too much offset for the system to deal with) must somehow be ignored, whether by hardware or software means. Lead-fail detection and offset measurements drive those decisions.

A more difficult situation is one in which a channel has all its electrodes connected and they have sufficiently low offset, but their contact with the patient is poor (due to insufficient skin preparation, dry skin, oily skin, dried-out electrolyte, or the electrodes have been worn for days and they’re peeling off, etc.). These conditions may not cause an ECG lead-fail indication, but they cause a much greater likelihood of picking up environmental noise spikes, and thus yielding a much higher rate of pacer indication. Noise pickup problems may be exacerbated by using non-shielded electrode lead wires. The question then arises of how to ignore the noisy channel’s detector, yet use the detector output from channels that “work better”. In some systems, a “voting scheme” may be established, whereby at least two of the channels must give an indication before using their outputs. However, a voting scheme cannot really take full advantage of multiple pacer detectors, since only one may be providing an accurate output. If the user has to make the choice of which channel’s detector to use, it may be most appropriate to let that choice be consciously made at the time of connecting the monitor.

For the above reasons, it is beneficial to consciously dedicate the ASIC’s single pacer detector to the primary ECG vector on which rate monitoring is to occur. There is arguably a chance that using lead II for this purpose provides a better likelihood of including a decent portion of the pacer pulse’s electrical vector, but that may not always be the case. If a different ECG vector is used for rate derivation, that vector should feed the pacer detector.

WARNING: ANSI/AAMI EC13 requires the inclusion in the operator’s directions for use of various warning statements, such as a warning about not leaving unattended those patients who have implanted pacemakers, and relying on heart rate meters on such patients.

It is also appropriate to consider sources of “internal” ambient noise spikes. Among these are models of implantable pacemakers which inject narrow (< 30 µsec wide) pulses into the body for the purpose of doing impedance pneumography. From these, the pacemaker is able to extract respiration rate and minute volume information. When the minute volume is seen to increase (usually due to increased exertion), the minimum pacing rate is also increased to cope with that increased exertion.

The response of the ASIC’s pacer detector to these pulses depends on several factors. The basic technique used in (almost any) pacer detector hardware to decide what is and what is not a pacer pulse consists of a band pass filter/amplifier, followed by a full wave rectifier and comparator. Because of the filtering, pulses more narrow than 100 µsec can still trip the detector if their amplitudes are increased sufficiently. In fact, the more troublesome environmental noise spikes are often more narrow than 50 µsec, yet they can trip many pacer detectors. The band pass filter in the ASIC’s pacer detector is designed to do a better job of rejecting narrow pulses than are pacer detectors that will detect 2 mV tall, 100 µsec wide pulses. (Note that its detection threshold for 100 µsec pulses is specified at 3 mV, and the ASIC’s typical detection threshold for that width is closer to 2.8 mV.)

If an incorrect filter is used between an ASIC ECG output and the input of the A/D, such a filter causes peaking of the ECG output due to capacitive loading. If the pacer detector is set to use such a peaked-up ECG output for its input, the detector’s response to narrow pulses may also be affected. Finally, the ESIS filters used in front of the ASIC attenuate and stretch noise pulses to a degree dependent on the ESIS filters’ design. All of these items contribute to how the ASIC and associated circuits respond to narrow pulses.



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Pacer Detector Trip Thresholds for Very Narrow PulsesWhen coupled with the designs of ESIS filter and output low pass filter given in the “5-lead” application circuit, the ASIC pacer detector’s trip thresholds at any human heart rate are roughly as follows for the nonadaptive and adaptive-with-min-threshold modes (amplitudes are R.T.I.):

25 mV for 10 µsec pulses

13 mV for 20 µsec pulses

8.7 mV for 30 µsec pulses

5.2 mV for 50 µsec pulses

Note that “threshold” means different things to different people. For some, if you feed the circuit 100 pulses of the same amplitude and it picks 2 of them, that amplitude is the threshold. For others, it must pick 98 out of 100 at that amplitude to constitute the threshold. The ASIC pacer detector’s band pass filters use switched capacitor technology, and therefore have a variable in addition to amplitude that effects whether this detector will trip or not on a particular pulse. More specifically, the particular instant in time the peak of the (filtered) pulse occurs with respect to the sampling of these filters can also affect whether tripping occurs. With that sampling variability, plus the circuit’s internal noise, plus the additive environmental noise spikes that inevitably get into the system to some degree, there is always some uncertainty in pulse detection for pulses whose amplitude is near the detection threshold. The above thresholds are for picking about 50% of the pulses on the average.

While the ASIC’s detector is used in its adaptive mode, the rate at which such pacemakers inject these very narrow pulses may affect how well they are rejected. In the case of one particular pacemaker, this pulse rate is 20 Hz, which is too slow a rate to get any benefit from the adaptive mode. If a pacemaker uses a pulsing rate that is faster than about 80 Hz, and the detector is used in its adaptive-with-min-threshold mode, then the ASIC’s pacer detector will probably not trip on them for amplitudes approaching 1.6x those listed above. Even higher amplitudes will not trip the detector in this mode if the pulse repetition rate is higher. Such rates continue to change as pacemaker technology evolves.

The design of the ASIC’s single pacer detector is intended to maximize its utility in a wide variety of monitoring situations. Its adaptive feature allows it to ignore most repetitive ambient environmental (both internal and external) noise spikes, while still tripping on real pacer pulses whose amplitude (after being filtered by the detector) is above that of the noise spikes. The filtering used in the pacer detector attenuates the more narrow environmental spikes more than it attenuates real pacer pulses anyway, so even high amplitudes of very narrow noise pulses do not significantly change the adaptive detector’s sensitivity to real pacer pulses.

Furthermore, the detector’s sensitivity to moderate-width pacer pulses is noticeably greater than that required by AAMI EC13, so it is more likely to pick up low amplitude pulses of those moderate widths even when the pacer and ECG vectors are nearly orthogonal with respect to each other. By comparison, the sensitivity of the pacer detectors in some ECG systems available today are notably less sensitive than EC13 requires or suggests, possibly to reduce their being tripped by many environmental noise spikes. Even using three such detectors does not guarantee better overall detection of real pacer pulses relative to the use of the ASIC’s single optimized detector.

Miscellaneous Causes for False Pacer DetectionReconnecting an electrode can cause a false tripping of the ASIC’s pacer detector, even when the reconnected electrode is not used in developing the ECG vector which feeds that pacer detector. Disconnection of such an electrode does not trip the pacer detector. During connection, a transient is produced in the ASIC’s ECG output which feeds the pacer detector, and that transient is large enough to legitimately trip the pacer detector. Conclusive experiments have shown that this problem is not due to inter-wire capacitive coupling in the ECG cable, but is one of capacitive coupling between physically-adjacent ECG input pins of the ASIC itself (and perhaps between interconnection traces on the ASIC’s actual die). When an electrode is disconnected, its ASIC input will rise to very nearly +5 V. A disconnected input is pulled up only by a ~ 70 nA current source inside the ASIC, and when that 70 nA must drive the capacitance of the ESIS filter and of the ECG cable’s signal wire, the rise time is relatively slow.



120.26084 Rev. 2 Copyright © 2001

It is slow enough, in fact, that the capacitive current injected by a rising signal pin into a physically adjacent input pin can nearly all be bled off (to the potential of the reference electrode) through the ESIS filter of a connected input. Hence, the net disturbance to the adjacent input pin’s signal is only a brief, negligible, voltage shift. (This is why no pacer detection occurs at electrode disconnect.) While an electrode is connected, the voltage at an ASIC ECG input is nearly zero. Reconnecting an electrode through a relatively low impedance to ground, etc. pulls the affected ASIC ECG input quite rapidly back to approximately ground. During this much faster fall time, the capacitive current injected into a physically adjacent pin cannot be bled away rapidly enough through the ESIS filter of an already-connected input, and that current forces the adjacent input negative by several mV or more. When only one of an active vector’s ASIC inputs gets this current injection, a large-enough differential signal results, and the pacer detector "legitimately" fires.

Causing a several mV shift in a high impedance input pin adjacent to a pin that rapidly drops by 5 volts is not unusual. Even if the ASIC’s package and die were revised to fix this particular issue, unsnapping an electrode that is used by the pacer detector’s input would still always fire the detector. Hence, the system must deal with a portion of these events anyway. Besides, electrodes do not get continually reconnected, so the incidence of such problems should be satisfactorily low.

From a software perspective, note that depending on which vector is selected as the pacer source, changing any bit in the LDR register may trigger the pacer detector because the change truly causes a small, fast differential signal to be injected. Any change to LD1OR2 naturally will affect the ECGO1 output signal, and consequently the pacer detector if that is the detector’s source. Changing LDR0 and LDR1 to change the choice of reference electrode from RL to LA will cause the LA "electrode voltage" to drop by about 8.4 mV (120 Kohm ESIS filter resistance times the 70 nA lead fail detection current that then goes into the reference electrode driver inside the ASIC instead of through the ESIS filter resistance). Changing LDOPN determines whether or not an electrode used by that ASIC is or is not used as a reference electrode, which can cause at least as much delta in that electrode as the previous 8.4 mV example. Changing LDIN0 or LDIN1 will change the voltage that needs to be applied to the reference electrode, and that may or may not be large enough to trip the pacer detector (depending on the magnitude of change, any electrode impedance mismatches and the common mode rejection of the ASIC). In the PDL register, using PDLS0 and PDLS1 to change the source used by the pacer detector will almost certainly trip the detector. Possibly changing CLPOFF can cause a large enough transient to trip it also, but this is less likely. Other than possibly PDOFF, changing the other bits in the PDL register seem unlikely to cause spurious detector trippings.

ECG Self-Test CircuitsTo help understand the following discussion, refer to the ECG Self-Test Control Register description on page 38, and the figures on page 13 and page 64. The ECG self-test circuits aid in the power-up diagnostics of the ECG section of the instrument. While these circuits are not intended to provide a complete test to the published specifications of this ASIC, they do facilitate verification of the proper functionality of most of the ASIC’s basic ECG functions. Making use of these self-test capabilities can satisfy many of the needs identified by an “FMEA” (Failure Modes and Effects Analysis; the REGULATORY AND SAFETY ISSUES section on page 78 refers to an FMECA, which adds an analysis of probability and criticality to the basic FMEA). An FMEA analyzes what problems can occur in a system, and how the instrument can detect those problems. The internal circuit nodes shared by the RF low pass filters, lead-fail detection pullups, lead-fail detectors, and inputs to the ECG mode-select multiplexers (which feed the four differential amplifiers) can be fed by several different signals.



Copyright © 2001 120.26084 Rev. 2

During normal ECG operation, these internal nodes are fed by the patient electrode signals, via the external passive ESIS filters and input pins EIN1-EIN5. When control bit INOPN is HI, the internal circuit nodes are disconnected from the electrode signals. This allows ECG testing to be done whether or not a patient is connected. While INOPN is HI and control bit TSTON is LO, the lead-fail detection pullup current sources will pull the internal circuit nodes nearly to the VDDA supply, simulating a lead-fail condition on all five inputs. While INOPN and TSTON are both HI, combinations of these internal nodes are fed by either internally-generated test signal VTST, or ground. Control signal TSEL selects which internal nodes are grounded and which receive VTST.

The VTST signal is the summation of two internally-generated dc signals. One signal is nominally +130 mV or -130 mV, with its polarity being determined by control bit SIGN. The other signal is approximately -4.25 mV with fixed polarity, which is turned on by control bit PDTST. Both signals are zero volts while control bit TSTON is LO, regardless of the states of SIGN or PDTST. Besides serving as an input to the differential amplifiers, VTST is also selectable as an input to the Reference Electrode Driver Circuit.

For more details about how to use the self-test capabilities, refer to the Applications Information section on page 39.

Respiration FunctionThe Respiration function includes circuits for generating three-state, high-frequency (approximately 65 kHz) signals for driving a selectable pair of electrodes, and circuits for generating Lead-select control for the external respiration circuits. The associated external hardware must include circuits for applying, amplifying, and measuring the resulting signal across the selected pair of electrodes, for performing a synchronous demodulation of the received signal, and for filtering the result and providing an output voltage related to thoracic impedance. The portions of this system implemented on-chip include the differential drivers for injecting currents through patient electrodes, a digital phase reference for the synchronous demodulator, and logic circuits to control the external respiration circuits. Portions of the impedance measurement circuit (synchronous demodulator, amplifier, etc.) have been left off-chip since their parameters need to be adjusted for different implementations.

The on-chip driver circuits generate a simple step approximation to a sine wave in order to reduce the low-pass filtering requirements for the drive signals. (Refer to the RESP Circuit Timing Diagrams on page 11.) The output signal levels in the low, middle, and high states are respectively at the voltages of ground (0 V), RSPMID (2.5 V), and VDDRSP (5 V). The circuits present a relatively low output impedance in all three states. The circuits generate drive signals at the output RSPORA for driving the RA electrode, and a complementary (inverted) drive signal at either one of the outputs RSPOLA or RSPOLL, depending on the setting of the SEL bit in the respiration control register. The circuits also generate a square-wave phase reference signal at the respiration carrier frequency at output RSPREF for use by an external synchronous detector.

Developing a respiration monitoring waveform by the impedance pneumography technique requires injecting into the ECG electrodes a current whose frequency is high by physiological standards, and generating an output wave form that is responsive to the changes in the impedance between electrodes. The total impedance seen by the impedance pneumography circuit is the sum of the defibrillator protection resistances in each wire of the ECG cable (often 1 kΩ per wire), the impedances of the electrode-to-skin interfaces (typically about 50 to 700 Ω each), the body’s bulk tissue impedance between the electrodes (about 100 to 500 Ω), and the variations in the latter that occur during a breath (0.2 to 5 Ω peak-to-peak). Except for the resistors in the ECG cable, all other impedances are frequency-dependent, and the stated values are given for the range of frequencies typically used for impedance pneumography (50 to 80 kHz). The wire-to-wire and wire-to-shield capacitances in the ECG cable appear as impedances in parallel with most or all of these other impedances, depending on whether the ECG cable’s defibrillator protection resistors are at the cable’s instrument end or at the patient end respectively. Such shunting has a much greater affect on total perceived impedance when electrode-to-patient impedance is high, which typically occurs when the electrode gel has dried out or the adhesive is letting go.



120.26084 Rev. 2 Copyright © 2001

The Respiration Circuit Issues section of the Applications Information section (page 39) provides more details about how the external respiration circuits function.

Voltage Reference Input and Bias GeneratorThe 2.5 V reference input is used by the ASIC to scale all of its voltage-related functions. Independent of the 2.5 V reference, the external 1 MΩ RBIAS resistor is used to scale all internal currents. The ECG lead-fail detection thresholds and their hysteresis, the switchable ECG offsets, the pacer detector threshold, and the self-test voltages are all ratiometric to the voltage reference input. Because 2.5 V is also the mid-point of the +5 V analog supply, it is appropriate to use that same voltage reference as the mid-level voltage supply for RESPMID, and as an external reference point for use by the chest-lead-present detector. For the most stable performance of RESP in particular, it is advisable to have the VDDRSP analog supply proportional to that same 2.5 V reference, and to also use that 2.5 V reference as the voltage reference for the A/D converter used by RESP.

For most modes of ASIC operation, the current drawn by the VREF input is about 50 nA. However, when any input channel has an offset enabled (EOS register), or the self-test voltage is enabled (EST register), its current draw increases to about 63 µA. The user’s system needs to allow for this.

Clock Divider CircuitThe Clock Divider Circuit uses an external clock signal CLKIN (nominally 5.213 MHz) and on-chip frequency dividers to generate all the various clock signals required by the ASIC.

The frequency chosen for CLKIN was dictated by the needs of the AD7716 A/D converter in Welch Allyn Protocol’s initial application of the ASIC. That converter’s oscillator frequency needed to be 5.213 MHz to provide the desired converter filter bandwidth and sample update rate in that application. The ASIC was designed to directly use that oscillator’s output. Note that the CLKIN input has Schmitt-trigger characteristics so that it will work equally well with a sine wave clock input (assuming voltage levels are sufficient), or with a full logic swing square wave input. The timing of all digital signals inside the ASIC is derived from this CLKIN input. The frequency of all the respiration signals is CLKIN divided by 80. The frequency of CLPCLK is CLKIN divided by 160. The frequency responses of the ASIC’s switched capacitor filters for the pacer detector and for the lead-fail detector’s low-pass function are also directly proportional to CLKIN. Finally, the pulse width of the pacer detector’s PDETO output is inversely proportional to CLKIN. Any changes to the CLKIN frequency affects all of these functions.

WARNING: The frequency for respiration needs to be one that cannot beat with a frequency that is present elsewhere in the application system (such as a switching power supply frequency, for example) or in the end-user’s operating environment, so that a resultant beat signal falls within the respiration pass band. If care is not taken to prevent this, it is likely that such a beat note signal will occur, and will sufficiently resemble a breathing signal so that it may prevent apnea detection by the host system.

Changes of ±5 % or so to the CLKIN frequency will not affect pacer detector performance significantly, but larger changes should first be investigated by the designer to determine their acceptability for the intended application. The low-pass filters in the ECG lead-fail detectors are –3 dB at 7 Hz when CLKIN is 5.213 MHz, so they still provide reasonable rejection of power line frequencies for any change in CLKIN that causes acceptably small changes in pacer detector performance.



Copyright © 2001 120.26084 Rev. 2

Miscellaneous Control FunctionsThe ASIC provides a way to power down its various functions through the serial interface by writing the appropriate control bits to the appropriate registers. In this way, portions of the ECG circuits and the respiration circuits can be turned ON or OFF independently under software control. The only circuits that cannot be turned OFF are the bias generator and lead-fail detection circuits (these consume very little current). Also provided is a hardware test input, HWTST, which can be used to force the ASIC’s control registers into known states where most circuits are active. (HWTST is only used during manufacturing testing. It does not need to be asserted like a power-up reset signal, but should be tied to ground.) HWTST does not affect the serial interface, and does not force any output into a high impedance state. Details of this are discussed in the Control Register Description on page 33.

Serial Interface DescriptionThe serial interface provides read/write access to the on-chip control registers which set the ASIC in its various operating modes. Communication with an external controlling agent such as a host processor or controller is achieved through four signal lines as shown below.

Serial Interface OperationOperation of the serial interface can be explained with the help of the timing diagrams for the WRITE and READ functions as shown on page 10. Initially, while CS/ is held at a logical high (HI) level, the serial interface is disabled and held internally in a reset condition. Communication is enabled when CS/ makes a transition to a logical low (LO) state. It is required that the serial clock input SCLK be held HI just prior to and during this transition. Considering the WRITE operation first, the host processor is required to set up a string of 16 bits on signal line DIN in the following sequence:

1. The first three bits (I2, I1, I0) define the instruction to be executed. Note that I2 is ignored, and from I1 and I0, only two instructions (READ and WRITE) are defined as shown below:

2. The next five bits (A4-A0) define the address of the on-chip register to be accessed. Bits A3 and A4 are not decoded. Only the lower 7 of the addresses defined by A0-A2 contain actual registers.

3. The last eight bits (D7-D0) constitute one byte of data to be written to the desired on-chip register.

In each input field (instruction, address and data), the bits occur in sequence with the most-significant bit (MSB) first. It is convenient, but not required, for the bits to be generated by the host processor on the rising edges of the serial clock (SCLK). The ASIC loads these bits in sequence into an intermediate register on the falling edges of SCLK.

For the WRITE operation, the selected on-chip register is updated with the new data on the 16th rising edge of SCLK while CS/ is still LO. The WRITE operation is safely aborted (i.e. the register is not updated) if CS/ goes HI before the end of this required interval.

Serial Interface Control Lines

Signal Function

CS/ Not Chip-Select

SCLK Serial Clock

DIN Serial Data In

DOUT Serial Data Out

Read/Write Bits

Function I2 I1 I0

READ x 0 0

WRITE x 1 1



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For the READ operation, the first eight bits on DIN define the instruction and register address fields, just as for the WRITE operation. The data from the addressed on-chip register is made available on the data-out line DOUT on the falling edges of SCLK (starting at the ninth falling edge of SCLK after CS/ goes LO). Again, the data is presented in sequence with the MSB occurring first. It is convenient, but not required, for the host processor to read the data on DOUT on the rising edges of SCLK. The DOUT output of the ASIC is held in a high-impedance condition at all times except when data is being read out, and is returned to a high-impedance state when CS/ goes HI during or at the end of a read cycle.

NOTE: It is highly recommended that the host system do its shifting out and clocking in of data on the rising edges of the SCLK it generates, and leave SCLK HI between transfers. If constraints of the host processor dictate that it shift and latch data on the falling edge of SCLK, then the host software will need to compensate for what may be perceived as a one-cycle delay in ASIC communications. Note that from a data-transfer perspective, the ASIC cares only about 16 falling clock EDGES of SCLK while CS/ is low, not necessarily SCLK cycles.

Serial Interface TimingSince the serial interface is used only to set the ASIC in specific operating modes (and verify the desired settings), fast operating speed was not a primary design requirement. Also, the fact that the ASIC is implemented in a primarily analog process with fairly conservative design rules (compared with a sub-micron digital process, for example), the operating speed of the interface is fairly slow. This limits the maximum toggle frequency of SCLK to 500 kHz. See the Specifications for more timing details. The logic levels for the serial I/O pins SCLK, CS/, DIN, and DOUT are 0 V (LO) and VDDIO (HI). ASIC input HWTST does not affect the serial interface.

Register MapThe following table defines the address mapping of all on-chip control/status registers:

Control Register DescriptionAs mentioned previously, the ASIC can be set-up in several operating and test modes by writing to several registers through the serial interface. The following describes the various registers used to set the various ECG modes. The "R/W" notation in the boxes below indicates bits that were included as spares in the ASIC design. They have read/write capability, but do not affect any ASIC operation. Note that "x" terms in the boxes below are for bits that do not exist in the indicated registers. Writing to those bits has no effect. Even though those bits act like high impedance nodes when read, each read cycle precharges those nodes LO so that they always read back LO. The default condition is the collection of states to which all bits are forced while HWTST is asserted. (Logic HI for HWTST=VDDIO.)

Control/Status Registers

A2 A1 A0 READ/WRITE REGISTER DEFINITION NAME

0 0 0 R/W ECG mode and lead-select register EMD

0 0 1 R/W ECG lead-drive control register LDR

0 1 0 R/W ECG offset voltage control register EOS

0 1 1 R/W Pacer detector and lead-fail control register PDL

1 0 0 R Lead-fail status register LFS

1 0 1 R/W ECG self-test mode control register EST

1 1 0 R/W Respiration circuit control register RSP

1 1 1 - Not Used -



Copyright © 2001 120.26084 Rev. 2

ECG Mode Control Register (EMD, Read/Write, Address=0):This register sets the ECG operating modes and enables the Reference Electrode Driver Circuit as shown:

ECGOFF: Turns OFF all ECG differential amplifiers, effectively forces PDETO LO, forces ECGON LO, and forces RSPOFF HI for ECGOFF=1. If ECGON is connected (externally) to also disable CLKIN, then setting ECGOFF=1 also halts CLPCLK, RSPREF, RSPORA, RSPOLA, and RSPOLL in their previous states.

MODE0, MODE1: Control operating modes of the ECG circuits according to the following table:

These mode control bits set the various input multiplexers and turn ON (or OFF) the appropriate ECG amplifiers to provide the required input-output relationships for the different modes of operation listed above. They do not affect functions such as the the Reference Electrode Driver, pacer detector, etc. However, the pacer detector output will inherently stay LO while its source is selected from a differential amplifier which is turned off by the ECG mode selection, since then there is no signal to trigger the pacer detector.

The resulting input-output relationships in the different modes are listed in the table below, where the following Lead and signal definitions apply: I = LA - RA, II = LL - RA, III = LL - LA, AVG3 = (LA+LL+RA)/3, V(n) = V(n) - AVG3 (n = 1…6). Note: In the “12-lead” Secondary mode, AVG3 is obtained from AVG3IN which must be connected to the AVG3O pin of the Primary ASIC.

When AVG3IN is disabled, this external input is disconnected prior to the common mode selection multiplexer. When AVG3O is disabled, it goes to a high impedance condition.

ECG Mode Control Register

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

x x R/W R/W LDROFF MODE1 MODE0 ECGOFF

Default x x 0 0 0 0 0 0

Mode Control

MODE1 MODE0 Mode Definition

0 0 “12-Lead” Primary Mode

0 1 “12-Lead” Secondary Mode

1 0 “5-Lead” Mode

1 1 “3-Lead” Mode

Inputs/Outputs for “3-Lead”, “5-Lead”, and “12-Lead” Modes

Inputs/Outputs “12-lead” Primary “12-lead” Secondary “5-lead” “3-lead”

IN1 LA V3 LA LA

IN2 LL V4 LL LL

IN3 RA V5 RA RA

IN4 V1 V6 V Disabled

IN5 V2 RL RL Disabled

OUT1 Lead I / II Lead V3 Lead I / II Lead I / II

OUT2 Lead III Lead V4 Lead III Lead III

OUT3 Lead V1 Lead V5 Lead V Disabled

OUT4 Lead V2 Lead V6 Disabled Disabled

AVG3IN Disabled Enabled Disabled Disabled

AVG3OUT AVG3 Disabled AVG3 AVG3



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LDROFF: Turns OFF the Reference Electrode Driver amplifier and common mode output buffer for LDROFF=1. It also sets the output level of that driver to analog ground (0 V) through a FET. Note that if LDOPN is set HI in the LDR register, LDROFF cannot ground the selected reference electrode, but can still turn off that driver amplifier.

ECG Reference Electrode (Driven-Lead) and Lead-Select Control Register (LDR, Read/Write, Address=1):This register is used to select the reference electrode and the common-mode input source to the Reference Electrode Driver as described below:

LD1OR2: Selects Lead I (LA-RA) for LD1OR2=0 as the output of ECG channel 1, or selects Lead II (LL-RA) for LD1OR2=1. This bit is ignored by ECGO1 (but not by the Reference Electrode Driver output multiplexer or by the common mode source multiplexer) when the ASIC is set to the 12-lead Secondary mode.

LDR0, LDR1: Determine the selection of the reference electrode according to the following table:

In the last column of the previous table, driven-lead DRVi is equivalent to the ith ECG input pin of the ASIC. The selected input and reference electrode pin definitions correspond to the actual patient electrodes as defined in the table below.

LDOPN: Making LDOPN=1 disconnects the Reference Electrode Driver circuit from all of the EIN1-EIN5 pins of the ASIC (regardless of the state of LDROFF in the EMD register). For LDOPN=0 the reference electrode is selected by LDR0, LDR1 as described above.

ECG Reference Electrode and Lead-Select Control Register


x x LDIN1 LDIN0 LDOPN LDR1 LDR0 LD1OR2

Default x x 0 0 0 0 0 0

Selection of Reference Electrode

LDR1 LDR0 LD1OR2 Reference Electrode

0 0 x DRV5

0 1 x DRV4

1 0 x DRV3

1 1 0 DRV2

1 1 1 DRV1

Reference Electrode and Patient Electrodes

Input Pin Reference Electrode 3- Lead System 5-Lead System 12-Lead System

(Primary ASIC)12-Lead System

(Secondary ASIC)

EIN1 DRV1 LA LA LA V3

EIN2 DRV2 LL LL LL V4

EIN3 DRV3 RA RA RA V5

EIN4 DRV4 - V V1 V6

EIN5 DRV5 RL-LL cable short RL V2 RL



Copyright © 2001 120.26084 Rev. 2

LDIN0, LDIN1: Select the common-mode source for the Reference Electrode Driver according to the following table:

CM1OR2 = (LA+RA)/2 when Lead I is selected (LD1OR2 = 0), CM1OR2 = (LL+RA)/2 when Lead II is selected (LD1OR2 = 1), CM3 = (LL+LA)/2, and AVG3 = (RA+LA+LL)/3. AVG3 is obtained from the internally-generated signal (the same that drives AVG3O) except while in 12 lead Secondary mode when AVG3 is obtained from input pin AVG3IN. The signal VTST is the internally-generated test signal that is enabled by the EST register. The VTST test voltage generator is enabled, then that generator’s outputs affect all four of the above common mode selections, not just VTST. Also note that the CM1OR2 and CM3 selections still function, but are not appropriate for use while in “12-lead” Secondary mode.

ECG Offset Voltage Control Register (EOS, Read/Write, Address=2):This register individually controls the offset voltage (and hence the input range) for each of the four ECG amplifiers as described below:

The values OSONi (i=1-4) respectively turn ON (or OFF) the offset for each individual ECG channel (outputs ECGO1-ECGO4) while OSGNi (i= 1-4) determine the polarity of the offset according to the following table:

Note that while any channel has its offset turned on, the lead-fail detection thresholds are raised for all four channels. (See the Lead-Fail Detection Function section on page 20.)

Pacer Detector Mode, Lead-Fail Control Register (PDL, Read-Write, Address=3):This register sets the pacer-detector and lead-fail detector operating modes as described below.

PDOFF: Turns OFF the pacer detector and forces PDETO to stay LO when PDOFF=1. Bits PDLS0, PDLS1, THMIN, and ADPT are ignored while PDOFF is HI.

Reference Electrode Driver Common-Mode Source

LDIN1 LDIN0 Common-Mode Source

0 0 AVG3

0 1 CM1OR2

1 0 CM3

1 1 VTST

ECG Offset Voltage Control Register


OSGN4 OSON4 OSGN3 OSON3 OSGN2 OSON2 OSGN1 OSON1

Default 0 0 0 0 0 0 0 0

Offset Control

OSON OSGN Offset Definition ≈ Input Range

0 x No Offset -300 mV to +300 mV

1 0 -230 mV Offset -70 mV to +530 mV

1 1 +230 mV Offset -530 V to +70 mV

Pacer Detector and Lead-Fail Control Register


RLPUP/ LFOSC CLPOFF PDLS1 PDLS0 THMIN ADPT PDOFF

Default 0 0 0 0 0 0 0 0



120.26084 Rev. 2 Copyright © 2001

ADPT: Selects adaptive pacer detector mode when ADPT=1. The pacer detector is in fixed-threshold mode (VTH≈1.8 mV for 0.2 and 2.0 msec pulses) when ADPT=0.

THMIN: Sets minimum threshold in adaptive mode. VTH≈1.8 mV for 0.2 and 2.0 msec pulses when THMIN=1, and VTH≈0.5 mV (noise-floor in practice) when THMIN=0. This bit is ignored in non-adaptive mode (ADPT=0).

PDLS0, PDLS1: Selects the pacer detector source (from the outputs of the ECG amplifiers) as defined in the following table:

Note that if an "off" channel is selected (like ECGO3 or ECGO4 while in “3-lead” mode), PDETO stays LO.

CLPOFF: Turns OFF the chest-lead-present detector and forces the CLPCLK output and CLP bit in the LFS register both LO when CLPOFF=1.

LFOSC: When LFOSC=1, the switched-capacitor circuits in the on-chip lead-fail detector operate from an internal clock oscillator. This allows the lead status to be continuously monitored even when the rest of the ECG system is powered down, including the external sigma-delta A-D converter which generates the 5.213 MHz clock. When LFOSC=0, the required clock is derived from CLKIN.

RLPUP/: Enables the RL lead-fail pull-up current source for RLPUP/=0 and disables this current source for RLPUP/=1. (Note that this affects the pull-up on EIN5, regardless of that pin’s definition based on ECG mode. More specifically, it is necessary to set RLPUP/ to LO to do lead-fail detection on V2 when in “12-lead” Primary mode.

Lead-Fail Status Register (LFS, Read Only, Address=4):The bits in this register represent the outputs of the lead-fail detector and chest-lead-present detector. An open electrode connection on any input EINi (i=1...5) causes the corresponding lead-fail bit to be set (LFi = 1, i=1...5). Conversely, a good electrode connection to the ith input results in LFi=0. LF1-LF5 are indeterminate while CLKIN is stopped and LFOSC is LO. CLP=1 indicates the presence of the chest (V) wire in a 5-wire ECG cable, whether or not the V electrode is connected to the patient. All lead-fail detectors are fully functional, even on inputs not used by “3-lead” ECG mode. The LFS register always reflects the current status of electrode connections. When any input changes connection status, output bit LDCH/ goes LO and stays LO until the LFS register is read, at which time LDCH/ goes HI again. CLP functions whether or not respiration is enabled. CLP is indeterminate if CLPOFF is LO while CLKIN is stopped, regardless of the state of LFOSC.

Pacer Detector Source

PDLS1 PDLS0 Pacer Detector Source

0 0 ECGO1

0 1 ECGO2

1 0 ECGO3

1 1 ECGO4

Lead-Fail Status Register


x x LF5 LF4 LF3 LF2 LF1 CLP



Copyright © 2001 120.26084 Rev. 2

ECG Self-Test Control Register (EST, Read/Write, Address=5):This register controls the operation of the ECG self-test functions built into the ASIC:

TSTON: Turns ON the ECG self-test signal-generator for TSTON=1. Its output is internal signal VTST. PDTST, SIGN, and TSEL are ignored while TSTON is LO. See note below.

TSEL: Selects the inputs to which the generated test signal VTST is applied according to the following table:

INOPN: Opens (disconnects) all five input pins (EIN1-EIN5) for INOPN=1. This allows the internal input nodes to float and be pulled up by the lead-fail current sources which allows testing of lead-fail functionality. See the note below.

SIGN: Determines the polarity of the dc test signal. VTST = +130 mV for SIGN = 1 and VTST = -130 mV for SIGN=0. SIGN does not affect the polarity of the PDTST signal.

PDTST: Adds a minus ~4.25 mV dc shift to the test signal when PDTST=1. Does not affect test signal when PDTST=0.

NOTE: The output of the self-test circuits feeds the lead-fail detectors and X8 differential amplifiers. (See the Self Test Diagram on page 64.) These self-test outputs are controlled by VTST, SIGN, and PDTST only while both INOPN and TSTON are HI simultaneously. Because EIN1 and EIN3 are controlled together, no output change should occur in Lead I. However, verifying no change in Lead I plus verifying proper changes in Leads II and III constitutes a complete test of the first ECG channel. VTST may also be selected by the common mode source multiplexer as the input to the Reference Electrode Driver amplifier.

Respiration Circuit and General Purpose Output Register (RSP, Read-Write, Address=6)

RSPON: Turns ON respiration circuits. Also affects the RSPOFF output bit for turning off all external respiration monitoring circuits. When RSPON is LO, it forces RSPREF and RSPORA to 0 V, and forces RSPOLA and RSPOLL to VDDRSP. Note that while the RSPON register bit itself is not affected by it, having the ECGOFF bit set HI in the EMD register forces the RSPOFF output pin HI. Also, if the ECGON output is connected (externally) to stop CLKIN when ECGON is LO, then RSPORA, RSPOLA, RSPOLL, and RSPREF will be halted in their last states.

SEL: Selects the pair of electrodes to be driven by the respiration drive signal outputs. SEL=0 causes outputs RSPORA, RSPOLL (right arm, left leg) to be selected, while SEL=1 causes outputs RSPORA, RSPOLA (right arm, left arm) to be selected.

ECG Self-Test Control Register


x x x PDTST SIGN INOPN TSEL TSTON

Default x x x 0 0 0 0 0

VTST Input Selection

TSEL VTST applied to inputs Inputs grounded (0V)

0 EIN1, EIN3, EIN5 EIN2, EIN4

1 EIN2, EIN4 EIN1, EIN3, EIN5

Resp Circuit and General Purpose Output Register


x R/W GPO4 GPO3 GPO2 GPO1 SEL RSPON

Default x 0 0 0 0 0 1 1



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GPO1-GPO4: General-Purpose Output bits are made available externally through pins 23 to 26 to control the lead selection of external respiration circuits and other user-defined circuits.

CAUTION: Because these pins are pulled to VDDRSP or RSPGND, changes in the output currents supplied by GPO1-GPO2 can couple into the respiration outputs. If any loading other than logic inputs will occur, it is strongly recommended to avoid cycling these pins at rates within the (external) respiration channel’s passband to avoid such problems. (Avoid repetitive cycling at rates slower than about 10 Hz.)

Note that even though the above descriptions call out the use of the RA, LA, and LL electrodes, the user can choose to connect any other combination of ECG electrodes to the external respiration circuits.

APPLICATIONS INFORMATIONFollowing are representative schematics for “5-lead” and “12-lead” ECG circuits and their A/D converters. Also shown are peripheral circuits (like respiration, hardware shutdown control, pacer detector, chest-lead-present detector, etc.) that may be added or deleted in whatever combination the user desires. ECG input filtering sufficient to suppress most common-mode electrocautery noise is shown, as well as a simpler filter to use when ESIS is not required. Where appropriate, instructions are included to adapt the designs to a particular user application. Many additional application details are included that have been gained through decades of experience with these applications.

Respiration Circuit IssuesThe external respiration circuits perform the following functions: bandpass filtering of the respiration carrier to achieve a more nearly sine wave signal for driving the patient, providing series capacitors to the patient for fault protection, bandpass filtering the carrier signals from the patient, providing defibrillator discharge protection clamping, and providing respiration lead selection, synchronous demodulation, final low-pass filtering, and respiration circuit power-down.

Respiration circuit signal conditioning begins by subtracting a fixed offset from the rectified (demodulated) average magnitude of the signal developed across the patient. The difference is greatly amplified, bandpass filtered, and then processed by a breath-picking software algorithm. The subtraction must be done to remove the portion of the total carrier signal magnitude that is dropped across the defibrillator protection resistors in series with each of the ECG wires. Because the gain is significant after the subtraction, slight changes in the applied carrier amplitude, changes in the attenuation or phase shifts of any filtering in its path, or changes in the gain or phase shift of amplifiers prior to the subtraction can have a larger effect on the dc output level of the synchronous demodulator.

That dc level is used as an indication of total impedance in the measurement path. It determines the threshold for indicating a lead failure unique to respiration, etc. Although it is not a highly accurate ohmeter, this dc level still needs to be reasonably consistent from unit to unit. For this reason, many of the capacitors in the filtering circuits require tighter tolerances than one might otherwise expect.

Note that the respiration channel is highly sensitive to noise on its VDDRSP supply, and will include much of that noise in the channel output at U3, pin 1. See ASIC Power and Connections and Issues (page 53) for more details.

WARNING: Portions of the respiration circuits are subject to high voltages and currents during defibrillator discharge. See Component Voltage and Power Rating (page 59), and Layout Considerations (page 73) for more details.

WARNING: The 0.1 µF capacitors (C1, C4, C7) between the respiration carrier generators and the patient cable connections for RA, LA, and LL normally do not contribute significantly to signal conditioning. They are also not required to block dc from the ECG signals. Instead, they serve only as a secondary means to prevent a single fault (like a shorted 220 pF capacitor from a carrier generator) from causing excessive dc currents through the patient while a respiration driver like RSPOLA is at 5 Vdc (either due to respiration being turned off completely, or due to the respiration vector being RSPORA and RSPOLL). This redundant protection is a regulatory requirement.



Copyright © 2001 120.26084 Rev. 2

Sample Schematic for “5-Lead” ECG with RESP and Power Shutdown



120.26084 Rev. 2 Copyright © 2001

Sample Schematic for “12-Lead” ECG



Copyright © 2001 120.26084 Rev. 2

The low-pass filtering of the carrier that occurs between the patient connection and the synchronous demodulator is only slight, and uses mostly parasitic capacitors. Additional capacitance would lower the level of the incoming signal and add phase shift, both of which are undesirable. Typically, it is not practical to achieve sufficient low-pass filtering here to achieve good electrosurgery interference suppression (ESIS) in a respiration circuit. This is because the respiration carrier’s frequency is high enough that a simple low-pass filter cannot begin to provide enough rolloff to sufficiently attenuate the cautery output frequency (of ~500 kHz) of most electrosurgery machines.

Therefore, the slight filtering is useful only to attenuate high-frequency (>tens of MHz) RF. C6, the 15 pF capacitor to ground, is used to approximately match the parasitic input capacitance of the U4A multiplexer when that mux channel is on. Note that U4 is a 4053B component. A 74HC4053 component has too large a capacitance for U4A’s circuit location. Multiplexers made by different manufacturers can have sufficiently different capacitance to noticeably affect the dc level of the total patient impedance output.

WARNING: The designer should be aware that pacer pulses of high enough amplitude to saturate U1 in the reference circuit will propagate into the RESP channel output. Such pulses will be significantly rounded off and stretched by the RESP channel’s low pass filtering, and may sufficiently resemble breaths that they could be counted as such. (Virtually any impedance pneumography design will exhibit this behavior for the bigger pulses in the AAMI-specified range.) The host system software that deals with rejecting cardiovascular artifact must also be able to deal with this phenomenon. Switching to the RESP vector that has smaller pacer artifact may be helpful in reducing such interference. Making the system behave differently following the firing of the pacer detector may also be helpful.

Synchronous Demodulator DetailsC16 in the LF353 (U1) circuit is used not only to block dc, but also to provide a phase lead in the outputs of the LF353. This phase lead contributes to matching the timing of the zero crossings of the outputs of the LF353 with the transitions of RSPREF. The timing of the incoming signal is important because the synchronous demodulator is basically a reversing switch that, when properly timed with the zero crossings of the signal it is detecting, accomplishes a precision full-wave rectification. Mismatches of zero crossings relative to the transitions of RSPREF reduce the gain of the demodulator. This causes the size of breathing signals to decrease and the dc level of the average demodulator output to not be as expected.

However, the total patient impedance itself affects the phase shift of the detected carrier with respect to RSPREF. Phase shifts get larger for higher total patient impedances than they are for low total patient impedances. This is even more pronounced for higher-capacitance patient ECG cables than for lower-capacitance cables. The shunting effect of cable capacitance not only affects phase shift, but also inherently reduces the perceived peak-to-peak amplitude of a given “size” breath at higher total patient impedances. To partially compensate for this, it is desirable to have a circuit that can somewhat increase the peak-to-peak breath size as the total patient impedance increases.

One way to do the latter is to design the synchronous demodulator so that its gain increases as the patient impedance (and, consequently, the phase shift of the received signal) increases. A synchronous demodulator has maximum gain when the zero crossings of its received signal coincide with the transitions of its phase reference (“reversing command”) signal. For sine wave input signals, the gain is proportional to the cosine of the phase difference between the input signal and the phase reference. To bias the gain range to fall on a more linear segment of this cosine behavior, the value of C16 is chosen to cause the zero crossings of the detected carrier to coincide best with the transitions of RSPREF while total patient impedance is 10-15% above the highest level for which the circuit must operate. This compensation is not perfect, but it does help.

When one or more of the ECG electrodes used for respiration are disconnected, the phase shift of the received carrier signal may become so great that the gain of the synchronous demodulator falls off significantly (especially with high capacitance cables). In this case, the averaged dc output actually begins to fall for increasing total “patient” impedance instead of rising further, making respiration lead-fail indications incorrect. (This has nothing to do directly with ECG lead-fail indications from the ASIC itself.) To prevent such occurrences, transistor Q2 has been added.



120.26084 Rev. 2 Copyright © 2001

For normal total patient impedance ranges, the peak positive signal swing at pins 1 and 5 of multiplexer U2 does not exceed a diode drop, since the normal waveform looks like a negative full-wave rectified signal there. Under the open electrode conditions, the positive peak signal swing would, without intervention, dramatically exceed a diode drop, even though its averaged value would not. Because of the capacitive coupling of C3 and C22, the diode action of Q2’s b-c junction forces the averaged value of the signal applied to U3A to drive the latter’s output toward positive saturation and give the correct the high impedance indication.

A transistor used in this manner has a slightly higher diode turn-on voltage than do many small signal silicon diodes. This is desirable because it keeps the diode off during normal impedance ranges. (For high temperature operation, this extra margin is especially needed.)

To prevent having leakage currents from nearby parts or traces couple into U3’s input on the board’s outside layers, surround that input and the ends of all components that connect to it with grounded guard traces. To be effective, those guard traces need to be free of solder mask.

U3A and the respiration channel’s passive filter at the A/D input both accomplish low-pass filtering. However, the low-pass filter function intrinsic to all sigma-delta A/D converters is set in this application to approximately 95 Hz in the 5-lead application circuit (all four channels have the same filtering) for the sake of ECG’s frequency response. The user’s respiration channel software should include a software low-pass filter (single pole is acceptable) to give a net -3 dB frequency of about 6 Hz to optimize the respiration channel’s noise floor without undue attenuation of rapid breathing signals. (This yields a net -3dB point of about 4 Hz.)

Depending on the manufacturer, 4053B parts have a maximum ON resistance of about 250 ohms to 500 ohms at 25 degrees C and 10 V total supply voltage. Their total capacitance to "ground" for an ON channel (sum of capacitances of the "wiper" by itself and a switch I/O pin by itself) range from about 14 pF to 27 pF. It is recommended that the designer select two vendors that have (nearly) the same capacitance for this part.

74HC4053 parts have a maximum ON resistance of about 100 ohms at 25 degrees C and 10 V total supply voltage. Their total capacitance to "ground" for an ON channel (sum of capacitances of the "wiper" by itself and a switch I/O pin by itself) range from about 35 pF to about 60 pF.

The U4A circuit location needs the lowest possible capacitance (to minimize signal attenuation by low pass filtering) and to a first order does not care about the higher ON resistance, since it drives only the high Z FET input of op amp U1A. The U2B and U2C circuit locations do not care particularly about the higher capacitance of a 74HC4053 (since the Z of the sources driving them is low), but their ON resistance is in series with two resistors of about 7 kohms (R8 and the series combination of R18 and R23). A 50 ohm increase (a worst case variation range for an HC4053) in the ON resistance of U2B and U2C has the effect of shifting a -2 V output of U3A by roughly -57 mV, and shifting a +2V output by roughly -86 mV. With a 4053B part (which can have a worst case variation of about 320 ohms), that variation at U3A’s output yields -365 mV and -550 mV variations respectively. All of these variations increase with changes in temperature, and the effects of tolerance in the series resistors in the patient cable also contributes to the variations. Out of a total A/D input range of 5 volts (actually, only about 4 volts are used), these variations are nearly intolerable. Using the higher capacitance of a 74HC4053 for location U4C likely would prevent the crystal from oscillating.

This version (Revision 2) of this manual specifies multiplexer portions U2B and U2C as being type 74HC4053, as they were in Revision 0. Revision 1 of this manual listed all multiplexer portions as 4053B type parts, in the interest of parts commonality, particularly for applications that do not use the illustrated sleep mode circuits. Five times higher values of resistance for R3, R8, R9, R18, and R23, and 0.2 times value of capacitance for C9 were used to allow the 4053B’s higher mux resistance in the U2B and U2C locations. In subsequent studies, it was found that the signal to noise ratio at U3 pin 1 suffered as a result of those changes. For this reason, Revision 2’s circuit values revert to those used by Revision 0. Revision 2 also revises the use of U2A, leaves U3 always powered, adds a low noise VDDRSP supply, separates out the connections for VDDRSP, adds D31 to CLPIN, and corrects the connection of Q2.



Copyright © 2001 120.26084 Rev. 2

Respiration Signal Output LevelsThe approximate characteristics of the application circuit’s respiration signal to the A/D converter are given below for the following conditions: ECG cable is 5-lead, has approximately 370 pF capacitance from each wire to the overall shield, uses DIN (pluggable) non-shielded lead wires, has a 1 kΩ resistor in each lead (located in the instrument end of the ECG cable) and uses the application schematic as shown. Actual performance is affected by board layout details, parasitic capacitances, and ECG cable design, so each implementation requires slight adjustments. See Fine Tuning RESP’s Synchronous Detector (page 47), and ECG Cable Design Versus RESP Performance (page 45).

A/D input ≈ -2.2 V for lead wires shorted and 1.0 kΩ resistors in each lead≈ -0.6 V for 500 Ω between the electrodes≈ 0.9 V for 1 kΩ between the electrodes (lower V for higher capacitance cables)≈ 2.3 V for 1.5 kΩ between the electrodes (lower V for higher capacitance cables)

The volts/ohm sensitivity is the derivative of the “ohmeter” response curve on which these points fall. Note that a “breath” of fixed delta ohms will appear smaller at high total impedance than it does at low total impedance.

For patient safety and to help prevent ECG machine damage during defibrillation, it is important that the user be given a warning message for “Inappropriate Cable” when this input is more negative than -2.4 V. Such an input is usually caused by using an ECG cable which does not contain 1 kΩ series-limiting resistors.

If it is desired to have respiration circuitry but no respiration lead selection, keep the input circuits for RA and either LA or LL, but delete the circuits for LL or LA respectively. Also, do not use U4A in the signal path, but do connect either R11 or R16 directly to U1 pin 3, and add a 15 pF capacitor to ground from U1 pin 3.

Clamp diodes are needed in the respiration circuits. The series resistance in a respiration input circuit is only 4.75 KΩ (e.g. R1) or 17.8 KΩ (e.g. R12) prior to a clamp diode. Although the time constant of a current spike from a defibrillation discharge is very short here (C2 x R1 = 1 µsec), the peak current involved could possibly latch up U1B, U4A, or the ASIC. R1 cannot be significantly increased in value because larger resistance values coupled with circuit parasitic capacitances would then cause too much attenuation at the respiration carrier frequency. The resistance in series with each ECG input is about 122 KΩ. Consequently, this limits the current through the ASIC’s input protection networks to a value much lower than that through D1, etc.

Respiration Artifacts from Non-Patient Sources

WARNING: Any ac signal, or harmonic thereof, whose frequency falls within approximately 10 Hz of the respiration carrier frequency is at risk of creating a beat note with that carrier. If the beat note falls (or drifts) within the respiration channel’s passband, the beat note may prevent the detection of apnea, and must be avoided. Common sources of such beat notes are switching power supplies, the fast axis of magnetic CRT deflection, oscillators of clock/calendar ICs, etc. Note for completeness, that a beat note may come from a source outside the monitor in question. Instead, it may come from another monitor or other piece of electronic equipment that is in the same physical vicinity.

Changing which electrode is used as ECG’s reference electrode produces a transient which can interfere with the respiration waveform, even when all electrodes are well connected.



120.26084 Rev. 2 Copyright © 2001

The respiration channel will show a small change when any ECG electrode is connected or disconnected. This is true even for electrodes that are not used by the respiration channel because all electrode wires are in close proximity to each other inside the ECG cable. The net capacitive loading on each of RESP’s wires in that cable to all the other wires is a mixture of series and shunt capacitances. Using an oversimplified explanation, the loading effect of a V wire (while V is not connected to the patient) on RESP’s RA wire is the series combination of the capacitance between the RA and V wires and the V wire’s shunt capacitance to the cable shield. When the V wire is hooked to the patient, the patient impedance parallels the V wire’s capacitance to the cable shield. This causes the net loading effect on the RA wire to increase, which in turn causes the respiration output signal to decrease a bit. The high frequency respiration carrier is extremely sensitive to any and all small impedance changes, since that is what all impedance pneumography systems are designed to be sensitive to. Therefore, there will be an effect on the respiration signal whenever any ECG electrode gets connected or disconnected, and that channel’s high pass filtering ensures that such effects are temporary. The preceding discussion is concerned only with the steady state implications of such impedance changes.

Because the dc level on disconnected electrodes rises relatively slowly to almost +5 V, lead reconnections (with their lower patient impedances) will affect RESP more than lead disconnects. This is because of the dramatic differences in rise and fall times of the ECG input voltages during such transitions. Because the respiration carrier signals are (and must be) ac-coupled, the faster voltage transitions during reconnection are more likely to affect RESP’s output than the slower voltage transitions following disconnection.

ECG Cable Design Versus RESP PerformanceThe patient cable shield is tied to the common of the system’s isolated supplies, i.e. to “ground”. There are both penalties and benefits of the cable’s capacitances and this “ground” connection. The capacitance from each wire in the cable to that “ground”, plus the capacitance to each other wire (unless a rather special and expensive design with a separate shield for each wire is used), provides more than one return path to “ground” for respiration carrier currents. (Even with separately shielded wires, the capacitances are not extremely well-matched.) Wire-to shield capacitance is not dramatically greater than the capacitance from one wire to all other wires in a cable, and the capacitance models for multiwire cables are far from simple. For these reasons, some degree of mismatch is unavoidable in any cable design.

The range of capacitance variations in “3-lead” and “5-lead” cables with a common shield is typically less than a 15 or 20% spread from the lowest to the highest capacitance in any given cable. Consequently, respiration behavior is somewhat variable due to differences in capacitance among the wires in the patient cable.

Variations in the values of resistors in each wire also contribute to respiration monitoring performance variations. However, the variations caused by differences in electrode-to-patient impedances are far greater than those caused by most cable variations.

Flexing the patient cable will generally cause some respiration signal artifact. However, cable designs that pass the EC13 cable ECG noise test are also relatively low in the amount of respiration artifact caused by flexing the cable. “Vibration” of the cable (e.g. due to patient transport) is most likely to occur at frequencies well above the respiration waveform channel’s low frequency filter cutoff, so this generally does not show up in its waveform. Using a two-pole low pass filter as in the application schematics further reduces such problems. Much bigger contributors to respiration channel artifact are the wiggling of the cable connectors (whether at the yoke or at the monitor end), and especially wiggling that disturbs the electrode-to skin interface. Impedance pneumography thus inherently detects the motion of any part of its measurement system.



Copyright © 2001 120.26084 Rev. 2

To give the reader a better idea of the range of variations in dc voltage at U3 pin 1 versus patient impedance due to differences in ECG cable design, six ECG cable designs were tried. All data was taken from the same board. Patient impedances were symmetrically distributed amongst RA, LA, and LL, i.e. for an impedance stated as 500 ohms, the impedance network used was a three "point" star, each of whose "points" was 250 ohms. (The center of the "star" was not connected to any respiration circuit, nor was it grounded.) For each cable, measurements were made in both RA - LA and RA - LL vectors, but the same two electrode connections on the test fixture were used in conjunction with swapping LA with LL to get data for the second vector. (This assured truly equal "patient" impedances for both vectors.) Capacitances indicated are from each single lead to the cable shield. Values of the series resistors are also included.

Note that ECG cables or lead wires that include series chokes to reduce the chances of RF burns at electrode sites during cautery will not work for respiration monitoring.

1. A 5 wire cable, approximately 11 feet long, plus detachable 2-foot long non-shielded lead wires. Only RA, LA, and LL were connected. Resistors were in the branch block.

RA = 1.018K/332pF, LA = 1.038K/357pF, LL = 1.020K/327pF

2. A 3 wire cable with non-detachable fully-shielded lead wires. Total length approximately 14 feet. Resistors were in the instrument plug.


3. A 3 wire cable, approximately 11 feet long, plus detachable 2-foot long non-shielded lead wires. Resistors were in the instrument plug.


4. A 5 wire cable with non-detachable fully shielded lead wires. Total length approximately 12 feet. Only RA, LA, and LL were connected. Resistors were in the instrument plug.


5. A 5 wire cable, approximately 11 feet long, plus 2-foot long detachable non-shielded lead wires. Only RA, LA, and LL were connected. Resistors were in the instrument plug.


6. A 3 wire cable, approximately 9 feet long, plus 2-foot long detachable non-shielded lead wires. (This unit’s branch block would accept either shielded or non-shielded lead wires, but it was tried only with the non-shielded ones.) Resistors were in the branch block.


Following are deviations from the previous patient impedance-versus-voltage listing:

At zero ohms patient impedance, total variation around –2.2 V was +/-0.1 V.

At 500 ohms patient impedance, total variation around –0.6 V was +/-0.07 V.

At 1.0 Kohms patient impedance, total variation around +0.9 V was +0.1 V to -0.2 V(+/-0.1 V except #6)

At 1.5 Kohms patient impedance, total variation around +2.3 V was +/-0.1 V if #1 and #6 are excluded; relative to +2.3 V, cable #1 was -0.2 to -0.25 V, and #6 was -0.3 to -0.4 V.

Multiple samples of cable #6 showed consistent results. At patient impedances higher than 1.5 Kohms, the spread of outputs further increased. As can be seen in this small sampling, it is highly advisable to try the design with the full range of cable types that may be used by the customer, and base "message thresholds" (for messages like "Check Electrodes", and "Inappropriate Cable?") accordingly.



120.26084 Rev. 2 Copyright © 2001

Not only does the dc level of U3 pin 1 versus patient impedance vary with ECG cable design, but so does the apparent "breath size", or ac component. The following data is provided for the same six ECG cable designs described above. A 1.0 ohm "square wave breath" was injected in series with the RA electrode. Again, all data is taken from the same board. Patient impedances were still symmetrically distributed among RA, LA, and LL as above. For each cable, measurements were again made in both RA-LA and RA-LL vectors, but the same two electrode connections on the test fixture were used in conjunction with swapping LA with LL to get data for the second vector. Results are normalized relative to the average (specifically, the average of cables #1 through #5 above) peak-to-peak ac signal produced at U3 pin 1 by the "square wave breath" while patient impedance was zero.

At zero ohms patient impedance, total variation was +3.5% to –3.9% for all but #6, which was -7.6%.

At 500 ohms patient impedance, total variation was +3.5% to –7.6% for all but #6, which was -9.4%.

At 1.0 Kohms patient impedance, total variation was +1.7% to –9.4% for all but #6, which was -18%.

At 1.5 Kohms patient impedance, total variation was –3.9% to –17% for all but #6, which was -26%.

At patient impedances higher than 1.5 Kohms, the exhibited rolloffs got worse, and #6 worsened more rapidly than did the others. Together with how well a unit’s breath-picking software can reject cardiogenic artifact, be sure to consider such behavior when specifying the minimum breath size that a design will "pick".

Fine Tuning RESP’s Synchronous DetectorThe following paragraphs illustrate the process of adjusting component values in the respiration channel’s synchronous detector to achieve the intended voltage at U3 pin 1 versus total impedance characteristics given in the previous subsection. The procedure given is for a "5-lead" ECG cable, but it is applicable to any cable. Begin with all component values as per the application schematic included in this manual. Time spent verifying that all parts in the respiration circuit are correctly loaded will be well spent!

Checking the synchronous detector’s phasing should be done first. Short together the RL, V, and LA electrode connections of a representative ECG cable. (Soldering together several snaps removed from disposable ECG electrodes is helpful for this.) Connect an 820 ohm resistor from the RA electrode to the shorted combination of the other three. Connect another 820 ohm resistor from the LL electrode to the shorted combination of three. Set the respiration circuit for the RA to LL vector. Monitor the signal at U2 pin 3. It should look basically like a (positive) full wave rectified signal. Ideally, each half sine wave will never dip negative, and the beginning edge and ending edges of each half sine wave will be symmetric with each other. Adjust the value of C16 to achieve the best symmetry. Perfection is NOT required here!

Note: Do not use R7 to change phase shift. Since C16 has <5% of the impedance magnitude that R7 has (net phase shift of R7/C16 = 12.7 degrees), for a required additional small phase shift, U1’s gain will be far less affected if that additional phase shift is obtained by changes in C16 than it would be if the required additional phase shift is obtained by changes in R7. Do not increase U1’s gain, because doing so makes U1’s gain somewhat more dependent on the op amp’s open loop gain and less dependent on the passive components in its external circuit. Minimizing changes in U1’s gain also reduces the amount of iteration that may be required with the other component changes, and keeps U1 in an operating region which has shown good experimental results.

Short all electrodes together, and adjust the value of R3 to achieve –2.2 V at U3 pin 1.

Next, separate the RA and LL electrodes from the other three. With RL, V, and LA electrodes still shorted together, add a 750 ohm resistor from RA to the combination of RL, V and LA. Add another 750 ohm resistor from LL to the combination of RL, V, and LA. If U3 pin 1’s output is too high (higher than +2.2 V or so), increase the values of R8 and R23, keeping R18+R23 = R8, until +2.2 V is obtained. (It is not necessary at this stage to maintain R18 = R23.)



Copyright © 2001 120.26084 Rev. 2

After this is achieved, short out both of the 750 ohm resistors (so all 5 electrodes are once again shorted together). Readjust R3 as required to obtain –2.2 V output. Iterate this process until a fixed set of resistor values yields a -2.2 V output for zero patient Z, and +2.2 V for 1.5 K patient Z. Only then readjust the values of R18 & R23 to have the same total as R8, but R18 and R23 each = (R8)/2.

Now swap the roles of LL and LA, set the respiration circuit for the RA to LA vector, and verify that the results obtained are within about +/-0.15 V of those for the first vector. Variations in the cable’s resistor values, variations in the wire-to-cable shield capacitance, and tolerances of the 390 pF and 220 pF circuit capacitors all affect the degree of consistency here. That is why the latter are specified as having tight tolerances. Do NOT try to save money here by using looser tolerance capacitors! Many variables over which the designer has no control will affect performance consistency of the synchronous detector. To achieve a tolerable limit on performance variations, control these capacitors!

A/D (and Its Input Filter) ConsiderationsThe stated range of tolerable dc offset at the ECG inputs EIN1 to EIN5 is governed by several factors. When the ASIC’s analog supplies are ±5 V, the fundamental limiting factor on the system input offset range is the input voltage range of the sigma-delta A/D converter. For the AD7716 converter shown, the input range is ±2.5 V. With the 8X gain of the ASIC’s differential amplifiers, this translates into the ECG system being able to tolerate just over ±300 mV of dc offset at the patient electrodes without having to use the built-in offset capability.

Note that to meet the requirements of EC13 Section 3.2.9.1, an ECG system must be able to accommodate the full range of ±300 mV of dc input offset with no discontinuity ≥ 30 µV. Therefore, an A/D input range of at least ±2.4 V is required.

If an A/D converter with an input range of ±5 V is used instead, the limitation is how close to its ±5 V supply rails the ASIC’s ECG outputs can swing. Under those conditions, the ECG system is able to tolerate approximately ±560 mV of dc offset at the patient electrodes without resorting to using the ASIC’s offset capability.

Note that the noise floor (specifically peak-to-peak noise, not RMS noise that is often listed in A/D specifications) must yield better than 14.5 bits of usable (noise-free) resolution to barely meet the 30 µV p-p maximum noise for the ±300 mV dynamic range referred to input. Also, the ASIC contributes its own noise, so the A/D needs to have at least 16 bits of noise-free resolution at the sample update rate needed by the OEM system.

It is convenient, although not required, to choose an A/D converter that features a digital input with a status that is sampled once per sample update period and included in the conversion output stream. This is an ideal way to get the PDETO status to the processor. Otherwise, PDETO must be applied to a processor interrupt pin.

Other Sigma Delta A/D ConvertersSubject to the requirements of the previous section, sigma-delta A/D converters other than the Analog Devices AD7716 may certainly be used, and the user may desire to have a sample update rate different than the 364 Hz (or an upper frequency limit different than 95 Hz) that the applications circuit provides. If (three or) four separate A/D converters are used to replace the AD7716, the designer must deal with how the host processor is to communicate with each of them. As long as the ASIC still receives a CLKIN frequency of about 5.2 MHz, such changes are acceptable. Whether the A/D converter operates in master mode or slave mode depends on the user’s processor interface. The applications circuits shown in this document use the A/D converter in slave mode (where the A/D converter interrupts the processor when it has a new conversion, and the processor clocks out the data). Note that while the AD7716 has the smallest total board space required for 4 channels, it requires much more operating power than does the ASIC, and it requires external parts to accomplish its power-down (sleep mode).



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Further note that the AD7716 uses a 5 V logic interface. Designs that intend to set VDDIO at 3.3 V in order to interface the ASIC with a 3.3 V processor must deal with the 5 V needs of the AD7716, typically by using open drain drivers with pullup resistors to +5 V, and processors that tolerate 5 V inputs. The designer may wish to investigate the actual logic HI levels generated by the AD7716. (They do not appear to supply much pullup current above 3.3 V anyway, and a 3.3 V logic input will be properly interpreted by the AD7716, although at a slight increase in supply current.)

RC Low Pass Input Filters The use of RC low pass filters at the inputs of the A/D converter are highly recommended to obtain the best low-noise performance. They also provide a very effective limiting of RF susceptibility by directly bypassing the A/D inputs to ground. The closed loop output impedance of the ASIC's ECG outputs does not stay low for radio frequencies that are significantly above the bandwidth of its internal op amps. (This same phenomenon applies to discrete op amps, too, of course.)

Also, the AD7716 inputs have some amount of dynamic loading, caused by switching of their sampling capacitors. By its injecting current spikes into the source, such dynamic loading could adversely affect the stability of the ASIC's op amp outputs. The latter are designed for low power and rail-to-rail output swing, both of which cause the open loop output impedance to be higher than for output stages that use source followers. Consequently, they have relatively low bandwidth and are more affected by capacitive loading. (Op amp output stages that use source followers give up rail-to-rail output swing in exchange for lower Z drive characteristics.)

The combination of all these things is best dealt with by having a series R and shunt C at the A/D inputs. To avoid the possible instability and peaking of the ASIC op amps’ high frequency response (the latter may affect the pacer detection characteristics) that will typically occur if the series resistor used is in the 1 kΩ or less range, use a 10 kΩ resistor to sufficiently decouple from the ASIC outputs the capacitive loading effect of the shunt C. A 10 nF shunt C then provides good RF bypassing without reducing the net upper frequency response. (Because sigma delta converters use a very high oversampling frequency, the filter is not needed to prevent aliasing of high frequency noise into the converter’s pass band, so this filter’s frequency limit may be noticeably higher than the intended ECG bandwidth. Also note that the net -3 dB upper frequency limit of the ECG channels’ frequency response is affected not only by the low pass response of these filters, but also by the low pass response inherent in a sigma delta A/D.) Finally, it is beneficial to have the low pass filter frequency for respiration be much lower than that for ECG.

Advantages and Disadvantages of the AD7716As far as choices of topology are concerned, the AD7716 was chosen for the A/D to use with this ASIC because it handles four channels at a time. And since the ASIC and A/D constitute most of the total ICs required, it saves a lot of board space. (Though its cost is an issue, the AD7716 does a lot in its small package, and in the ASIC’s original application, space was a prime issue. When computing total costs, it can be very enlightening to investigate the true costs for purchasing, stocking, inventorying, placing, soldering, testing, and occasionally reworking many so-called inexpensive parts. Also, fewer parts means fewer opportunities for mis-loads, fewer solder joints to possibly be intermittent, and, in general, fewer warranty costs.)

For reference, at the time of this writing, there was a long lead time for purchasing AD7716s in either package style. Note that the AD7716 uses two’s complement data format.



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If the designer has one channel of an AD7716 left over, it is possible (with much care) to use that spare channel for multiplexed self-test measurement functions. If the signals being multiplexed do not need to be sampled rapidly, and are basically dc levels, then allowing three or more (ECG) sample intervals while at each signal will allow sufficient settling time to make the multiplexing work. However, beware of crosstalk issues within the A/D. See the A/D’s data sheet for specifications. Multiplexed signals that differ from each other by volts will sufficiently couple into at least one other A/D channel to a degree sufficient to prevent passing EC13’s ECG channel noise test. If the designer needs to do this, make the multiplexed channel be either channel number 1 or channel number 4, and expect the worst coupling into channel 2 or channel 3 respectively. (The crosstalk appears to be due to physical proximity of the individual channels on the die, and the channels appear to have a physical layout sequence like their assigned numerical sequence.) A technique that minimizes crosstalk is to substantially attenuate the multiplexed signal before feeding it into the A/D. Because the AD7716 has so many bits of resolution, sufficient self-test resolution may still be obtained despite the external attenuation. Depending on the nature of the signals that are multiplexed, it may be necessary to include "ground" as one of the multiplexed signals, so that offset errors may be compensated for by software.

Other A/D ApproachesOther approaches may certainly be used, however, and they have two principal differences from the proffered designs. One difference involves using a discrete band pass amplifier and associated circuits for each channel, followed by a successive approximation A/D, whether one per channel, or a sample-and-hold per channel followed by a shared converter of this type. The other involves simply limiting the circuits to deal with only one channel (whether it uses a sigma delta or successive approximation A/D) and making the choice of ECG vector be selectable. Which, if any, of these alternatives are acceptable depends entirely on the user’s application.

In some applications, only one vector may be needed at a time, whether for display, telemetry transmission, analysis, or a mixture of these things. (Note that single vector operation does not allow for deriving the vectors for aVR aVL, and aVF .) For “12-lead” diagnostic applications in the United States today, all vectors need to be simultaneously sampled, i.e., sequential snapshots of each of the 12 total vectors are not considered acceptable for diagnostic purposes. These are the two extremes.

For all instances in which the user expects to derive additional ECG vectors (e.g. aVR, aVL, and aVF) from the hardware-derived ones, the sampling of the hardware-derived vectors needs to be effectively time-synchronous (even a millisecond of time skew between two signals can be significant in diagnostic applications). They also need to have matched gain and frequency response characteristics, particularly in the 0.05 Hz region. These issues are more important in diagnostic ECG systems than in monitoring ECG systems. Using an A/D with four matched channels running in parallel guarantees the time synchronization of sampling of all waveforms without adding a sample and hold. Along with this, forcing the band pass filtering to be done in software guarantees the matching of all channels' frequency response.

For the successive approximation converter alternative, perhaps the most likely converter choices have 12-bit resolution. (The AD7716 has 22 bits, with 17 to 18 of them usable in this application.) Be aware that even though an A/D is specified as providing X bits of output resolution, its effective resolution is limited by its noise performance. The overall system noise performance is a function of the ECG analog circuit noise and the conversion noise of the A/D. When all other performance specifications are equal, for noise considerations, a converter with serial outputs is preferred over one with parallel outputs. If a parallel interface A/D is to be used, better noise performance will be obtained if an intermediate (external) latch is connected between the A/D's digital outputs and the processor data bus.

Alternatively, if the processor data bus is to be directly connected to the A/D's digital outputs, the processor should optimally be put to sleep during each conversion. When a processor is dealing with other things during a conversion, its data bus is very noisy. Having 8 (or 12) of its data bus lines toggling during the conversion time will definitely couple digital noise into the actual converter portion of such chips. Serial interface converters, with their fewer interface lines, usually have less of this coupling. Therefore, they yield more usable bits of resolution above the noise floor, i.e., the converter’s one or two least significant bits are more likely to be truly useful.



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Independent Channel Hardware RequirementsFor each independent channel that is required, certain circuit functions are required as follows:

Ac coupling is needed to remove the dc offset from the signals at ASIC outputs ECGO1-ECGO4 prior to further amplification. The ac coupling (high pass filter) must typically be -3 dB at 0.05 Hz in a straightforward design. A refinement of this approach is to do the high pass filtering at 0.3 Hz or so (where it is easier to get tight tolerance filter capacitors and use software filtering techniques to yield a net 0.05 Hz response). This approach adds processing delays that are acceptable in many situations, but not in instances where a balloon pump, pacemaker, or synchronized cardioversion defibrillator is to be controlled by the ECG signal. Note that in order to get accurate ST segment appearance in any vectors that are to be derived by software from algebraic manipulations of hardware-derived outputs, all of the high pass filters must be well matched (within 5%). The high pass filter capacitors' dielectrics must be chosen for very low dielectric absorption as well as very low leakage. Mylar (polyester), or polystyrene dielectrics are preferable over ceramic (particularly over “Z5U” dielectric ceramic). Electrolytic capacitors are totally out of the question here.

How the ac coupling is implemented affects the range of input dc offset that the system can tolerate. If the high pass capacitors are truly in series with the ASIC outputs, then better than ±500 mV of ECG input offset can be tolerated without a problem while the ASIC is powered by ±5 V supplies (without resorting to using the ASIC’s offset circuits). When the ac coupling capacitor is used inside an op amp loop, the ECG dc offset that can be tolerated is a function of the high pass circuit topology. No matter how the ac coupling is done, it is important that the A/D converter be able to measure the dc level coming out of the ASIC’s output, so that the user can be given an alert when the dc level has reached a point where further dc increases may cause attenuation (typically clipping) of the ECG signal. This is a regulatory requirement of clause 51.103 of EN60601-2-25 and EN60601-2-27. Note that depending on circuit topology, the positive and negative limits for this alert need not be equal, if inequality provides more usable offset range. (However, an input-referred range of at least ±300 mV is required in any case.)

As a part of the ac coupling, a trace restore circuit is required. This is a means for temporarily increasing the high pass frequency in order to rapidly pull the amplifiers out of saturation following large step changes in input voltage (following defibrillation or change of reference electrode, e.g.). It typically involves using a moderate ON-resistance FET in parallel with the resistor that determines the high pass frequency. The host processor must turn on the FET when the A/D has been saturated at either end of its dynamic range for about 100 msec or so, and hold it on for about 250 msec. The FET switch must be a very low leakage part, and its circuit must be implemented in such a way that its leakage currents into the high pass filter’s large resistor do not contribute significant offsets following the ac coupling–even at elevated temperatures. It is important to "guard" such circuitry areas on the circuit board in order to prevent sneak leakage paths across the board surface. Guard traces must not be covered with solder mask if they are to function effectively.

Following the ac coupling and its trace restore, additional gain is required prior to feeding the successive approximation A/D. (Low pass filtering is almost always included in this amplifier section, but in this paragraph, discussion is limited to the gain issue.) Recall that the gain of the ASIC’s differential amplifiers is 8X. In order to reproduce a 10 mV p-p ECG input signal (required by EC13 and other standards), the total nominal gain of the band pass amplifier must be equal to the A/D's input range divided by 80 mV. This amplifier must deal with any offset required by the A/D, i.e., no offset is required if the A/D accepts +/- input, but it must provide 1/2 scale offset if the A/D accepts only positive voltages. Note that the ASIC provides +/- outputs.

As part of the above amplifier, some low pass filtering is required. The low pass filter frequency should typically be slightly above 40 Hz for monitoring applications, or slightly above 150 Hz for diagnostic applications. Note that the A/D sampling rate used interacts with the low pass filtering frequency in terms of how the overall system will perform when tested to the ECG regulatory requirements for high frequency response (the triangle wave test). When single pole low pass filtering is used, it will likely be necessary to use corner frequencies about 20% higher than 40 Hz or 150 Hz to pass these tests (as well as to deal with tolerances in the filtering components).



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When more than one ECG channel is to be used simultaneously, time skew between the A/D conversions of the hardware-derived vectors must be minimized. This is typically accomplished by using a sample and hold on each hardware-derived signal, followed by a multiplexer and the shared A/D. Alternatively, separate successive approximation A/Ds with internal sample and hold features may be run in parallel (one per channel) and synchronized.

Sleep Mode IssuesA sleep mode is included to minimize power consumption while the user desires to disable ECG/RESP monitoring in general, and while no patient is connected in particular. The sleep mode shuts down all circuits on the ASIC that are not required to detect when a patient gets reconnected, and also provides output pins to disable power to any external ECG/RESP circuits. To put the ASIC in sleep mode (but keep lead-fail circuits active), set LDROFF and ECGOFF HI in the EMD register, set LDOPN LO in the LDR register, set LFOSC, CLPOFF, and PDOFF HI and RLPUP/ LO in the PDL register, set INOPN LO in the EST register, set RSPON LO in the RSP register, and stop the cycling of CLKIN.

Be aware that when an ECG input is left floating during a lead-fault condition, the differential amplifier it connects to will saturate (if the latter is enabled by the mode setting of the EMD register). Saturation puts nearly full supply voltage across the differential amplifier’s internal feedback resistors, and substantially increases the ASIC’s power consumption. 27 mW has been observed with all four differential amplifiers enabled under total lead fault conditions, and proportionally less with fewer amplifers enabled and in lead fault. These numbers are also dependent on chip-temperature, and on the tolerance of the internal feedback resistors (±25% typically). During sleep mode, or for active mode with one or two amplifiers disabled by the mode selection, the power consumption is considerably lower.

In an initial implementation, shutting down the external circuits (the 4-channel sigma-delta A/D converter in particular) provided a much bigger power savings than just shutting down the ASIC. That AD7716 converter provided no direct sleep mode, so circuits were added outside it to allow ASIC output ECGON to shut off the convertor’s minus supply (thus disabling its operating bias) and to stop its oscillator. The former substantially reduced the power consumption of the A/D converter’s analog circuits, and the latter did the same for its digital circuits. Because the A/D converter’s oscillator also provides clocking for the ASIC, stopping that oscillator eliminates the power consumption of most of the ASIC’s digital circuits as well. When the ASIC is disabled, its four ECG analog outputs go to 0 V. The RESP signal (from the synchronous detector) is forced to 0 V (mostly so it cannot pull the A/D converter input below ground). The 2.5 V reference to the A/D converter is also forced to 0 V during sleep mode.

Regarding RESP, note that turning the ASIC’s ECG circuits off overrides the function of the RSPON bit in the RSP register by halting all of RESP’s clocked signals and forcing the output pin RSPOFF high. (If ECG is turned off because there is no ECG patient connection, then there is no point in looking for a RESP connection.) The RSPON bit itself is still independent of ECG.

Note that CLKIN is divided down inside the ASIC, and is used for clocking the switched capacitor low pass filters of the ECG lead-fail circuits. Without such clocking, it is not possible during sleep mode to detect when patient ECG connections are established. To fill that need, yet still allow all other ASIC and A/D-clocked circuits to be shut down, an internal oscillator is included for clocking the ECG lead-fail detection circuits. That oscillator is enabled by the LFOSC bit in the PDL Register. No other clocked ASIC circuits are fed by that oscillator, including any RESP circuits and CLPCLK. LFOSC should be set LO while not in sleep mode.

In the 5-lead ECG schematic, if the respiration circuits are not included but sleep mode shutdown of the A/D converter is still desired, the functions of U4B and U4C are still required. U4 must be a 4053B, rather than a 74HC4053, because of the need for a low capacitance part in the U4C location.



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ASIC Power Connections and IssuesThe operating voltages for the ASIC are selected to be compatible with power supplies typically available in the host system. Thus, the on-chip analog circuits are powered by +5 and -5 V (required by the external sigma-delta A/D converters). The digital I/O pins swing between 0 and 3.3 V (specifically, between 0 and VDDIO which can be 5 V if desired) for interface to the processor (serial interface, and interrupts), and between 0 and 5 V to drive external 5 V logic circuits for respiration lead selection. Inside the ASIC, the digital circuits (except for ASIC I/O) operate between VSS and GND. This gives the best low-noise performance, since the substrate is connected to VSS. The positive level in the digital circuits is constrained to 0 V to minimize on-chip digital noise generation. Appropriate digital level-shifting circuits are used at the boundaries between these various mixed voltage sections.

CAUTION: Because the ASIC has many power connections, a brief description of how they relate to each other is beneficial for understanding noise management and power sequencing. (See also the Absolute Maximum Ratings, page 9.) AGND1, AGND2, DGND, and RSPGND are all independent of each other. Diode connections exist between RSPGND and AGND1/AGND2. These diode connections are for protection of the internal circuits. Lack of ohmic connections prevents noise-coupling from one ground to another inside the die. Outside the ASIC all grounds should be well-connected to each other. VDDA and VDDA1 are ohmically connected to each other inside the ASIC, and should be well-connected to each other outside the ASIC as well.

CAUTION: VSS and VSSA are ohmically connected inside the ASIC, and should be well-connected to each other outside the ASIC. VREF and RSPMID are not ohmically connected to each other. RSPMID should be equal to VDDRSP/2 for proper RESP operation and RSPMID should never exceed VDDRSP. If RESP is not to be used in a design, RSPMID should be connected to RSPGND. VREF should never exceed VDDA/VDDA1. VDDIO sequencing relative to VDDA or to VDDRSP is not critical, but should never be lower than any of the logic inputs. VSS/VSSA sequencing relative to any other supply is not critical. During sequencing, VDDRSP may be higher than VDDA, but should be prevented from going more than a silicon diode drop lower than VDDA. Because the gate drive for RESP output transistors is generated from VDDA, not VDDRSP, these two supplies should be equal after settling occurs.

Adequate supply decoupling is necessary for minimizing the noise in ECG and RESP outputs. Notice the power supply rejection specification given for the ECG amplifiers. In particular, notice that rejection of noise on the +5 V supply is about 12 to 16 times better than the rejection of noise on the -5 V supply. Those specifications are given for 60 Hz ripple on the VDDA/VDDA1 and VSS/VSSA supplies. Rejection is slightly better at dc and worse at frequencies higher than 60 Hz. Typically, supplies in microprocessor-based instruments have a small amount of noise related to the timing of the task sequence executed by the processor, so supply filtering and decoupling designs must take this into account.

Noise in the respiration output at U3 pin 1 is extremely affected by noise in the ASIC’s VDDRSP supply, and additionally has a somewhat unusual relationship to the dc voltage level at U3 pin 1. The nature of the respiration circuit is such that VDDRSP-supply-related noise at U3 pin 1 as a percentage of the (magnitude of the) dc level at U3 pin 1 is always equal to the percentage of noise in VDDRSP. For example, if there is 10 mV of noise on the 5 volt VDDRSP supply (0.2%), this will give 4 mV of noise at U3 pin 1 for dc levels of +/-2 volts at U3 pin 1, 2 mV of noise at U3 pin 1 for dc levels of +/-1 volt at U3 pin 1, 1 mV of noise for+/-0.5 mV dc levels, and "zero" VDDRSP-supply-related noise for a zero dc level at U3 pin 1. Considering that a 1 ohm breath causes on the order of a 3 mV change at U3 pin 1, this amount of noise is a disaster. (Many other respiration circuit implementations have a similar supply noise sensitivity.)

While most of the ASIC +5 V analog supply needs can usually be met by low pass filtering a +5 V digital supply, the VDDRSP supply’s needs absolutely cannot be, due to the reasons above. Digital supply loading normally varies dramatically depending on what software is running at any given instant, and will cause low frequency ripple on the digital supply. It takes quite a low pass filter to eliminate this ripple sufficiently from an analog supply that is obtained by filtering such a digital supply. Noise on the analog supplies can have some noise contribution to the ECG outputs, but supply noise levels that scarcely bother ECG can have a disastrous effect on respiration.



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Applications that do not have a sufficiently-clean supply for VDDRSP will need to actually create a separate quiet VDDRSP supply. To obtain the lowest possible respiration channel noise all the way through the A/D system, it is highly recommended to develop VDDRSP as twice (or slightly less than twice, if necessary) the voltage of the 2.5 volt source that is used for the A/D’s reference. A sufficiently low noise, low dropout linear regulation scheme, powered by +5V, is included in the 5-lead ECG plus RESP schematic on page 40. (It is imperative that the minimum valley voltage of the +5 V supply used here not drop below 4.95 V, if noise on the new VDDRSP is to be kept low!)

If this approach is taken, pay attention to the ASIC’s absolute maximum supply ratings from VDDRSP to VDDA, and add a Schottky diode accordingly between them. Note that a small readjustment of component values may be necessary for VDDRSP below +5 V. Refer to Fine Tuning RESP’s Synchronous Detector (page 47) for details.

After getting VDDRSP sufficiently quiet, the designer should also do a respiration noise comparison with and without a 2.5 V source connected to the ASIC’s RSPMID pin (its bypass capacitor remains as is, in any case). The action of the respiration circuit drive makes the RSPMID pin behave like a charge pump output. As such, if the RSPMID pin has a bypass capacitor, but no connection to a supply, it will force itself to almost exactly VDDRSP/2 anyway. A net current will flow into or out of the RSPMID pin only when it is connected to a supply voltage that is not exactly equal to VDDRSP/2. Depending on the details of the power supplies actually used, there may be no need to literally connect RSPMID to a supply, and respiration channel noise may be lower with no supply connection there. Try it both ways to determine which way has the least noise.

In addition to the supply noise issues with RESP’s synchronous detector, there are possible respiration noise issues inside the ASIC itself. The path for supply noise causing interference in the RESP waveform is more complicated than it is for ECG. Supply variations not only directly cause noise in the RESP wave form, but variations in VDDA/VDDA1, VSS/VSSA, VDDRSP, and RSPMID manifest themselves as variations in the gate-to-source voltages of the FETs that generate the 3-level outputs RSPORA, RSPOLA, and RSPOLL. Variations in gate-to-source voltage cause variations in drain-to-source on resistance, and this leads to slight variations in the RESP currents supplied to the ECG electrodes. Those current variations lead to variations in the sensed voltage between electrodes, and these show up in the RESP waveform output. The supply rejection of the A/D converter used also affects the overall system noise level.

The 2.5 volt reference used must have very low low-frequency noise output. Quite a range of noise levels exists from one type of 2.5 volt reference to another! (An Analog Devices AD680 works very well for this 2.5 volt reference.) Be sure to observe the reference’s maximum capacitance loading specification. This version of this manual resolves that issue in the application schematics.

An estimate may be calculated for the power supply currents attributable to the operation of the serial interface as follows:

Compared with a totally static serial interface, the power increase will be approximately equal to (∆s listed for Case #5 of Power Requirements specifications) X (duty factor for the actual use of the interface) X (actual SCLK frequency) / 500 kHz. (Actual currents vary somewhat based on the actual data stream by up to ±50% of the calculated ∆s.)

NOTE: During defibrillator discharges, the defibrillator protection clamp diodes shunt currents that occur through the respiration input circuits (and through the ASIC’s internal protection circuits on ECG inputs) into the ±5 V power supplies. If the currents from the defibrillator discharges are higher than the total load currents on those supplies, those supply voltages may rise during the discharges. The 5.6 V zener diodes across these supplies are to limit such rises to safe levels.

NOTE: It is recommended that the bypass capacitors on the VDDA and VSS supplies be large enough so that by themselves they limit the voltage rise that may occur during a defibrillator discharge. (See the ECG ESIS Input Filter and Defibrillator Protection Considerations section, page 55, for voltages and timing to expect during defibrillator discharges.)



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CAUTION: There is one additional problem that can arise during defibrillator discharges despite the use of high value supply bypass capacitors and shunt clamp zener diodes. This problem can occur if either the VDDA or VSS supply is used as the sensed voltage to control the operation of a multi-output switching supply, and that supply is pulled above the hysteresis point of the switching regulator during a defibrillator discharge. If so, the switching supply will cease operation until the sensed supply voltage drops below the switcher’s hysteresis point. If the interval of no switching is long enough, the other outputs of the multi-output switcher will sag – perhaps enough to disrupt operation of the circuits they power.

Considerations Unique To “12-Lead” OperationSeveral clarifications are appropriate concerning how the ASIC operates differently in “12-lead” ECG modes. Only one electrode out of ten should be grounded or driven at a time. The reference electrode should be RL (if connected), its common mode source should be AVG3 for the Secondary ASIC, and the Primary ASIC should have LDROFF and LDOPN both HI. Internal test voltages may be controlled together or independently for the two ASICs as desired (depending on user software). The RLPUP/ bit in the PDL register controls the lead-fail detection pullup for V2 in the Primary ASIC, and should always be on. Typically, pacer detection will be done only by the Primary ASIC, though both ASICs’ detectors may be used if desired. Typically, the chest-lead-present detection would only be done by the Primary ASIC if “3-lead” cables are allowed in a “12-lead” design, or would not be used at all if only “5-lead” and “12-lead” cables are allowed.

Both ASICs’ lead-fail oscillators must be enabled during sleep mode, and all other sleep mode considerations apply to both ASICs as well. The LDCH/ outputs of the two ASICs may be OR’d (not wired-OR) or provided separately to the processor as desired. All RESP functions are totally independent of the ECG mode of either ASIC, and may be incorporated in “12-lead” ECG systems if the user desires. In “12-lead” systems that also allow “3-lead” and/or “5-lead” cables, if the RL connection is the same for all cables (i.e. is to always be driven via EIN5 of the Secondary ASIC), the Secondary ASIC’s driven lead amplifier must be kept on to drive RL (including the “RL” used only as part of an RL-LL short in “3-lead” cables), even though the rest of the Secondary ASIC’s ECG functions are turned off for “5-lead” operation.

To achieve the upper end of the diagnostic bandwidth’s frequency response (nominally 150 Hz), the A/D converter must run faster than it does for the application’s 5-lead circuit. With the clocking circuit shown, the “12-lead” circuit’s -3 dB frequency is 143 Hz, and its sample update rate is 545 Hz.

ECG ESIS Input Filter and Defibrillator Protection Considerations

WARNING: The ESIS filters limit current through the patient to safe levels during ASIC fault conditions (discussed in the Regulatory Issues section on page 78), and together with the neon bulbs, they distribute the voltage drops and limit the input currents to the ASIC during ESD and defibrillator discharges.

In addition to the preceding safety and protection features, the ESIS filters significantly attenuate common mode electrocautery and RF interference, help shape the overall pacer detector response to narrow pulses (both from pacemakers and from environmental noise), and keep the respiration carrier from affecting the pacer detector’s sensitivity. If the ECG input filters limit the filter/ASIC bandwidth to significantly lower than 4 kHz net, the detection specification for 100 µsec-wide pacer pulses may not be met. Finally, to some extent they also limit how fast a lead-off condition can be detected.

Note that a two-stage input filter may be required to keep the pacer detection threshold from being reduced when the RESP carrier is present on the electrodes. Lead-fail detection time is a function not only of the 7 Hz low pass filter response time, but also of how long it takes for the lead-fail current to charge the combined capacitance of the input filter and patient cable to the lead-fail detection threshold. (Recall that the latter is increased for all channels in an ASIC if the offset function is enabled for any channel in that ASIC, so detection time then increases slightly.) For reference, the amount of line frequency noise that is coupled into a disconnected lead also has a noticeable effect on lead-fail detection time.



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Possible Causes for Processor Resets, Etc. During Defibrillation DischargeItems that have been observed to cause processor resets or other disturbances following defibrillator discharge include the following:

1. Falsely tripped supply over-voltage or under-voltage detectors.

Suggested solutions: Add bypass capacitors directly at the inputs of such voltage monitors, keep trace lengths very short and loop areas small for supply and ground connections of voltage monitors, and do not make their reaction time any faster than they absolutely need to be.

2. Glitches in the operating frequency of crystal oscillators–for both the processor and the A/D– especially if used in a phase-locked loop.

Suggested solutions: Keep oscillators far from neon bulbs, ESIS filters, and chest wire connection to chest-lead-present detector inputs, keep all discrete components for the oscillator circuit on the same surface of the board as the IC that contains the oscillator, minimize total board area used for the oscillator components and crystal, use a crystal type which has a metal case or lid that can be grounded, and include a well-grounded shield over the entire collection of oscillator components and oscillator IC.

3. Glitches coupled into board traces used by open drain outputs, whether used to achieve 5V outputs from a 3.3V processor or other reason.

Suggested solutions: Use lower value pullup resistors, keep traces for such signals buried between circuit board planes, keep such traces well separated from traces that "spike" during defibrillator discharge, and for signals that are open drain to achieve voltage translation, examine the power tradeoff of directly driving a 5V input part from a 3.3V push/pull output instead of sticking with an open drain drive but using a lower value pullup resistor).

4. Outputs of opto-isolators glitching to a false state.

Suggested solutions: Use higher LED current and lower value pullup resistors–being careful to allow plenty of margin for the worst case current transfer ratio of the opto, bypass the opto output with a suitable capacitor if its speed of operation will tolerate the capacitor loading.

5. Insufficient lead fail debounce time so that a displayed ECG trace changes vector following a defibrillator discharge.

Suggested solution: Make debounce interval at least 0.1 seconds).

6. During defibrillator discharge, small currents flow through discrete RESP input clamp diodes, or through the ASIC’s ECG input protection diodes and may cause the +/-5 V supplies to which these diodes connect to exceed their regulated voltage, perhaps only slightly. Note that multiple clamp diodes are likely to be delivering currents to the same supplies simultaneously. If all the following additional conditions are met, this can cause a problem. (1) These supplies are delivered by a multi-output switcher, (2) one of them serves as the voltage regulation feedback point for that switcher, and (3) an additional output from the same switcher also produces a separate logic supply for the processor. While the feedback-point supply exceeds its regulation voltage, the switcher may stop, which likely will cause the logic supply to sag low enough that an undervoltage reset will occur inside the processor or from an external undervoltage detector.

Suggested solutions: Use big enough capacitors on the logic supply to ride through the defibrillator discharge, and make sure that the minimum load on the voltage feedback supply always exceeds the sum of the maximum expected peak currents through all protection diodes.



120.26084 Rev. 2 Copyright © 2001

7. High amplitude, fast rise time currents that pass through the neon bulbs during defibrillation couple into other portions of the ECG front end (particularly digital portions), and cause processor resets or error conditions.

Suggested solutions: Keep neon bulbs in a tight cluster away from all other circuitry. Make the ground-side connection of all neon bulbs be grouped together in an “island” of ground plane. Surround that “island” almost completely by a void in the ground plane, so that connection between the island and the rest of the ground plane occurs at only one point. This prevents any high currents from circulating outside the “island”. Locate the connection point to the “island” as far as possible away from all digital circuitry.

ECG Front End ShieldingWhile the passive ESIS filters shown in the “5-lead” applications schematic are absolutely necessary to obtain good suppression of electrocautery noise, a second absolute requirement to obtain good electrocautery noise suppression is adequate shielding around the ECG front end. Metal (or metalized) shields must completely enclose all portions of the ECG and A/D circuitry on both surfaces of the circuit board for optimal results. The shields should be tied to the common (“ground”) of the isolated power supplies. They effectively “guard” these circuits so that as they are being driven up and down by common mode electrocautery signals, parasitic capacitances from ECG circuit elements to non-isolated portions of the monitor cannot cause the creation of differential electrocautery signals in ECG circuit portions inboard from the ESIS filters. Be aware that the neon bulbs basically bring the interference signals inside the shield, and as such, the bulbs should not be folded over on top of any other circuitry. Otherwise, they will couple some of that interference directly into later circuit portions. While the respiration circuits should also be enclosed by shielding, there is very little suppression of electrocautery interference in the respiration channel. This is because too much energy of the electrocautery interference falls within the frequency pass band required by the respiration front end.

Neon Bulbs and ECG Input ProtectionNOTE: Also see the previous paragraph’s discussion about neon bulbs, and item 7 above.

CAUTION: ANSI/AAMI EC53, the standard for ECG Cables and Leadwires, requires that ECG cables contain 1 kΩ current-limiting resistors to prevent damage to an ECG device that is left connected to a patient while that patient is defibrillated. ANSI/AAMI EC13 specifies that an ECG system shall not reduce the energy delivered by a defibrillator to a patient by more than 10%. Both of these requirements dictate proper resistors in the ECG cables for devices that are specified as being protected against damage from defibrillator discharge. A more conservative approach is to require them if the ECG device has any reasonable chance of being subjected to defibrillator discharge. Be aware that in the applications circuits shown, the neon bulbs will NOT protect the ECG circuits from catastrophic damage if they are subjected to defibrillator discharges through ECG cables that contain no such limiting resistors. It is the responsibility of the manufacturer of the host system to include appropriate hazard information in the operator’s directions for use.

Neon bulbs are circuit elements that are commonly used to protect ECG inputs from damage while the ECG-connected patient is being defibrillated. On the benefits side, neon bulbs offer low cost, very low leakage and shunt capacitance, and the ability to briefly handle currents that are large for their physical size. On the liabilities side, they are not available in surface mount styles, they do wear out, and they usually do not turn on immediately. In the following discussion, voltages indicated are peak or dc, not RMS, and voltages are dependent on gas mixture and concentration. Several details are glossed over, but the essence is correct.



Copyright © 2001 120.26084 Rev. 2

In the “normal” usage of a neon bulb (low currents, and dc-60 Hz operation), as the voltage across it is increased from zero, the bulb remains unlit until the voltage first reaches the bulb’s “striking” (first turnon) voltage (at 64 to 92 V). Special “emissive coatings” have been applied to the surfaces of the bulb’s electrodes to minimize this striking voltage, because without those materials the striking voltage would be much higher. After its initial turnon, the bulb voltage drops to its “maintaining” voltage (60 to 75 V). The light these bulbs generate is then yellow or orange (if the gas in them is literally neon rather than argon, etc.). This behavior applies for peak bulb currents that are limited to less than a milliampere or two. This is the mode in which neon bulbs are used as visual indicators. So called “high brightness” bulbs have higher listed values for the first turn-on and maintaining voltages. For much higher currents, bulb conduction becomes an arc, bulb voltage drop is a few volts, and the color of light is violet. The bulb will self-destruct if these conditions persist very long.

During bulb conduction, neon atoms become highly excited and lose an electron, thereby becoming positively charged. They slam into the negative electrode and dislodge molecules of the emissive coating. Over time, this ionic bombardment removes enough of the emissive coating to expose some of the base metal of the electrodes, and the striking voltage increases. With small conduction currents, this increase takes thousands of hours. With the currents reached in the ECG lead wires during defibrillation, the process occurs at a much faster rate, but defibrillation occurs very infrequently, so the net increase is generally not a problem.

Neon bulbs require some free charged particles to be present to initiate the glow discharge when an operating voltage is applied. When the bulb is operated in a normally-lit environment, that room light can cause photoemission from the emissive coatings on the electrodes to serve this purpose. Unfortunately, neon bulbs used in ECG devices are almost never exposed to room light while in normal operation. Without free charged particles present, there will be some ignition delay. (This phenomenon is termed “dark effect” and may take minutes under the usual visual indicator operating conditions.) For those applications, this problem may successfully be countered by doping the gas in the bulbs with small amounts of radioactive materials. Within the short time interval taken for a defibrillator discharge, however, the radioactive doping has not been observed to help much.

Finally, neon bulbs may not turn on at all during electrocautery because the cautery voltage’s polarity reverses at approximately 500 kHz, and it takes a finite time to get the ionization going in each direction.

Neon Bulb Test ResultsThe voltages actually observed across neon bulbs in ECG equipment under (EC13, etc.) simulated defibrillation conditions are as follows. The particular bulb style tested had an electrode length of approximately 0.12 in. Many tests were run on non-radioactively-doped bulbs, and a few on doped ones. The simulation is as described in EC13 for checking defibrillator protection of ECG monitors, and its peak output voltage is 5 kV. The patient cable contained 1 kΩ series resistors. Voltage measurements were made using a 500 MHz digital storage oscilloscope and a properly compensated, 1000X, 3 pF, 13 kV, 75 MHz ac/dc scope probe. Current measurements were made with a dc-50 MHz active clamp-on current probe. Note that no two discharges produced the same results, so general ranges are listed instead. Initial voltages reached 500 to 800 V peak, looking roughly like a half cycle of sine wave (the 0 to 180 degree portion) with lots of high amplitude, high frequency noise on its 90 to 180 degree sub-portion. The base width of the half sine wave was 0.8 to 1.5 µsec. Following this large spike, either of two types of behavior occurred prior to the arcing conduction mode. In one behavior (mostly with, but not limited to, the non-doped bulbs), the next portion of note had a peak voltage of 425 to 700 V. It looked roughly like the 45 to 135 degree portion of a sine wave, with that portion having a width of about 16 µsec. After that, the voltage chattered rapidly back and forth between 125 and 250 V for a duration 45 to 70 µsec.



120.26084 Rev. 2 Copyright © 2001

In the other behavior (mostly with, but not limited to, the doped bulbs), bulb voltage transitioned from the big spike to a gently down sloping pedestal whose average amplitude was between 180 and 270 V, and whose duration ranged from 150 µsec to 2 msec. Only after one of these behaviors did the bulb enter its arcing mode of conduction, drop its voltage to less than 10 V, and stay there for 4 to 6.5 msec. Following the arcing conduction mode (when bulb current dropped below 0.4 to 0.5 amperes), the voltage popped abruptly up to between 90 and 120 V for the non-doped bulbs, and between 150 to 180 V with the doped bulbs. (These doped bulbs were so-called “high brightness” types. From there it started an exponential decay to about 75 V in 4 to 10 msec.

Below 75 V the exponential decay was more rapid, and settled to zero. Unless otherwise specified, these results were not significantly different between doped and non-doped bulbs. Results with other models of neon bulb will undoubtedly vary, but in summary, neon bulbs do NOT clamp ECG inputs at a fixed 60 to 80 V during defibrillation!

When selecting a neon bulb model, pick ones rated for 120 VRMS operation, not for 250 VRMS operation. The latter are designed for higher striking and maintaining voltages. Physical size of the neon bulbs probably affects the clamping voltage somewhat, with smaller bulbs (actually, smaller electrode surface areas) likely having higher clamping voltages. Possibly in ECG/defibrillator combinations, bulbs with larger electrodes may be needed for sufficient life expectancy. Avoid types with a built-in series resistor. For the benefit of lead-fail detection, pick a model that guarantees very low electrical leakage (with ~ zero bias voltage), even under high humidity conditions. (The latter must apply after the board assembly, and the residue from that soldering operation may contribute leakage to not only the neon bulbs, but to all other circuit components.) Some manufacturers offer a special wax coating (Chicago Miniature A1C type, special P/N 04-0722) that seems to help somewhat. It was found that for some vendors, purchasing the bulbs with tinned leads (Lamptronix P/N LTXNE38H-T), rather than tinning them at the board assembly stage, helped reduce electrical leakage problems. Electrical leakage problems manifest themselves as difficulty in detecting ECG lead-fail conditions in high humidity environments.

Component Voltage and Power RatingsBecause the ECG input voltages reach the levels discussed above during defibrillation, it is necessary to scale the voltage and power ratings of the ESIS filter components accordingly.

Make sure the power rating of all the ESIS filter resistors is not less than 0.1 W (and, for voltage withstand reasons, not less than “1206” in physical size if surface mount parts are used) to avoid possible arcing and cumulative changes in resistance during defibrillator discharges through the neon bulbs. This also applies to R29 and R30 in the C.L.P. circuit, and to R1, R4, R6, R10, R12-15, and R19 in the respiration circuits. In the two-stage ESIS filter, the first capacitors (220 pF in the schematic diagrams) should have an NPO dielectric, not be less than “0805” size, and be rated at 200 V. This also applies to all 220 pF capacitors in the respiration circuits, and to C33 in the C.L.P. circuit. NPO dielectric ceramic capacitor manufacturers specify a dielectric withstand voltage for NPO parts in excess of 2.5 times their rated dc voltage. (For board spacing recommendations, see Layout Considerations on page 73.)

Defibrillator Issues with ECG Cables

CAUTION: For the ECG system to tolerate defibrillator discharges, the ECG patient cable must include series resistors in each electrode path. These resistors must be 1 kΩ or greater, and have adequate size and construction to survive the peak energy surge during the discharges. If respiration is to be monitored, these resistors must be 1 kΩ to work properly with the applications circuit. Finally, the ECG cable construction must prevent internal arcs from occurring during defibrillator discharge.

Defibrillator discharge can cause two basic types of electrical failures in ECG cables: failed-open series resistors, and arc-overs due to inadequate insulation or spacings. Failed-open resistors are obvious, but arc-overs are not. This section will deal only with the latter.



Copyright © 2001 120.26084 Rev. 2

Arc-overs leave behind a carbon track that greatly enhances the likelihood of future arc-overs in the same place, and those carbon tracks often are electrically conductive (< 20 megohms) even at low voltages. Such leakages often prevent lead fail detection, and if severe, can lower input impedances enough so that ECG signals from high impedance electrode connections may be distorted. After a leakage path occurs, it never truly leaves, since the carbon particles remain (although its resistance increases with time–sometimes during tens of minutes). The hipot tests of EC53 will usually still fail because of past arc-overs, even if an ohmmeter no longer shows the leakage.

There are differences between the test methods used for the EN60601-2-25, etc. (IEC) instrument defibrillator withstand test and the EC13 instrument defibrillator withstand test. To add to the complexity, the test requirement for cables alone is AAMI EC53. Each test has its place, but they are not interchangeable. Of the two instrument defibrillator withstand tests, the IEC method is more severe than the EC13 method, because the IEC method applies greater electrode-to-electrode peak voltages and currents, and the voltage rise times are faster. It is best to test instruments using only the IEC method, since those instruments’ designs need to pass the IEC requirement for European markets.

Below is a summary of the approximate peak theoretical voltage differences to be expected at different locations in the cable during the three different testing methods. Numbers are based on spice modeling of 1.00 K series resistors in the cables, a 10 ohm series defibrillator output resistance, a 5 kV charge on the defibrillator’s capacitor, a 100 ohm defibrillator dummy load resistor, and neon bulb front end clamps that reach a peak voltage of 500 V (800 V+ has been recorded) before turning on. Results do include the differences in loading on the 100 ohm defibrillator dummy load.

This comparison illustrates what has been observed experimentally, that from a voltage breakdown standpoint, a cable that can pass the EC53 test may still prevent passing an instrument defibrillator withstand test! It also illustrates a need for a change in EC53, plus making EC13 match the IEC test. Both issues are being pursued with the appropriate AAMI committees.

Finally, be aware that damage to ECG cables due to the high voltages of defibrillator discharge is a progressive, cumulative thing. If the designer ends up doing many defibrillator discharges while trying to isolate any system glitches that occur then, it is highly recommended to not try to do them all with the same cable. Some cables have been observed to withstand literally hundreds of defibrillator discharges without apparent failure, but finally developed an amazing amount of internal carbon tracks after 300 discharges. Despite this, no leakage paths showed up in ohmmeter tests of the cable. Where arc-overs will eventually occur within a cable, and how many discharges it will take is all dependent on the particular cable’s design. The insidious issue is that such arc-overs can effectively temporarily shunt the series resistors (yet low voltage ohmmeter measurements do not show a problem), thus giving huge currents through the neons, which may rapidly cause their clamping voltages to rise. If that happens, arc-overs may start occurring on the ECG board, and the problems snowball. Beware!

Defibrillator Discharge Tests

Test Electrode-Electrode

Electrode-Shield

Instrument Signal-Signal

Instrument Signal-Shield

EC13, 3-lead, in a monitor 3.24 kV 1.99 kV 1 kV 0.5 kV

EC13, 5-lead, in a monitor 3.14 kV 2.21 kV 1 kV 0.5 kV

IEC, 3-lead, in a monitor 4.21 kV 2.64 kV 1 kV 0.5 kV

IEC, 5-lead, in a monitor 4.15 kV 3.02 kV 1 kV 0.5 kV

EC53, 3 or 5 lead. 2.67 kV 2.67 kV 0 0



120.26084 Rev. 2 Copyright © 2001

Derived ECG VectorsCertain ECG vectors are developed directly by the ASIC hardware. Other ECG vectors may be derived algebraically by the user’s software from the hardware-developed ones. Note that channel one of the ASIC may be selected to be either Lead I or Lead II (except in “12-lead” Secondary mode), and that you cannot derive any Lead V from any other vectors (at least not by any non-proprietary techniques).

Following are the definitions of all directly and indirectly-derived ECG vectors handled by these ASICs:

It is important to do the software high pass filtering and line frequency notch filtering prior to the algebraic manipulations above. The high pass filtering removes dc content so that no (software) saturation or wraparound can occur in the derived vectors. Doing the notch filtering on the original vectors prevents any possible overloading of such filters. In systems that offer a choice of upper end frequency response (such as 40 Hz monitoring bandwidth or 150 Hz diagnostic bandwidth), the low pass filtering to achieve 40 Hz bandwidth may be done either on the original vectors or on the derived vectors, so long as the derived and original vectors all end up with the same phase delay. (Depending on the implementation, this may require delaying the original vectors appropriately.)

WARNING: The user’s software must disable the use of any software-derived ECG vector that is derived from any invalid ASIC-generated vector.

Dealing With ECG OffsetNote: See ECG Amplifiers (page 14), and Electrode Offsets Versus Electrode Type (page 19) for situations where additional offset capability may be beneficial. Note that offset ranges are based on an A/D input range of +/-2.5 V, as discussed in A/D (and Its Input Filter) Considerations (page 48).)

For basically steady state situations, dealing with excess offsets must be properly coordinated with the lead fail detection threshold. Consider that if an electrode has high offset because its electrolyte has dried out, or because its adhesive has partially let go, restoring the connection in either case will involve "mashing on the electrode" to fix it. Physically disturbing the electrolyte gel and the body surface it contacts will, at least temporarily, reduce the electrode’s offset. In either case, the user needs to be encouraged (by requiring a lower offset in order to recognize reconnection, i.e. hysteresis) to actually replace the electrode or electrodes responsible for offset.

However, to get the benefit of the ASIC’s offset immediately following a defibrillator discharge, it is recommended to enable the offset in an affected vector for 10 seconds or so after one of its electrodes has first shown a disconnect. If the electrode is detected again during this time window, then treat offset enabling based on amplifier saturation. If the electrode does not get "reconnected" (i.e. its offset doesn’t sag enough after a defibrillator discharge), then disable the offset. This approach provides the desired benefits following defibrillator discharges and while electrodes are continuously connected, yet prompts the user to fix electrodes with real problems.

Derived ECG Vectors

Lead Sel Formula Derived Formula

I LA - RA II - III

II LL - RA I + III

III LL - LA Always directly created

aVR RA - (LA+LL)/2 - (I + III/2) or (III/2 - II)

aVL LA - (RA+LL)/2 (I - III)/2 or (II/2 - III)

aVF LL - (RA+LA)/2 (II + III)/2 or (I/2 + III)

VN VN - (RA+LA+LL)/3 Always directly created



Copyright © 2001 120.26084 Rev. 2

Note that because the software should eventually disable all offsets during a lead fail condition, the lead-reconnect threshold will be set at the lower value that is appropriate with no offsets enabled. During laboratory testing, this can cause unexpected behavior of lead reconnection detection with positive offsets between nominally 410 and 600 mV. These offsets are enough to trigger adding the appropriate offset, which raises the "rising edge" lead fail detection (for ALL electrodes used by that ASIC) to about 0.73 V, and raises the "falling edge" lead fail reattachment detection threshold to about 0.61 V. However, if the offset control algorithm disables the offset during lead fail, the threshold for detection of reattachment becomes roughly +405 mV, so electrodes with these offsets would not be detected. Such a situation can arise only with positive offsets. Negative offsets will always show as reconnected, since the lead fail detection thresholds are always positive.

A sustained excess offset condition needs to be treated (by some parts of the software and by the user) almost like a total lead fail condition. Note that offset tests are based on vector outputs, not individual electrodes, so it cannot always be determined which individual signal electrode(s) has(have) an excessive offset. Furthermore, in real cases where excess offset occurs, it is most likely to occur in more than one electrode at once. Hence, in many cases it will not be possible to use any ECG vectors. For this reason, and also because the ASIC’s 550 mV input offset capability greatly exceeds the 300 mV capability required by ECG standards, it is recommended that when one sustained excess offset condition occurs, all ECG vectors must be considered invalid, including all derived vectors. This practice avoids many difficult decisions like choices of waveform display, lead selection, pacer detection source, and driven electrode’s common mode source, etc.

Following is a control scheme that appears to do the required things. (It has been reviewed and implemented, but not yet fully tested.) The process is shown for ECGO1, and may be iterated with all other channels.

1. There may be instances in which proper history does not exist to determine the polarity of an over range sigma delta A/D output. (Recall that when an AD7716’s output is over-ranged, it sets an over-range status bit in its data stream, but the provided conversion result is indeterminate under over-range conditions.) Since one cannot always count on that history (at least for purposes of offset control), it makes sense to periodically toggle the offset polarity if necessary to try and sort out the “polarity” of over-range.

2. The low pass filtered ECG signal in the accompanying diagram is one that is required anyway for use in display centering software.

3. The +/-2.45 volt (instead of +/-2.5 volt) decision points are used to keep them within the dynamic range of the A/D, yet make them have a high enough margin outside the effects of +/-300 mV offset at the inputs. This avoids problems with EC13’s Section 4.2.9.1, parts f & g.

4. Regarding "trace restore", this action should affect both the low pass filtered ECGOx signal in this diagram as well as the band pass filtered ECG that is used for display traces. The display trace will also impose other requirements for trace restore because of display zone size versus waveform height, etc. The latter requirements can, but do not have to, affect the low pass filtered signal in this flow chart.

5. Trace restore needs are due in part to the behavior of actual electrodes after being subjected to a defibrillator discharge. To explain, electrode offset voltages will decay for awhile following the discharge. It may be helpful to have a higher high pass frequency (greater than or equal to 0.5 Hz) than usual during this decay so that there is a better chance of keeping the trace on screen, albeit somewhat distorted during the decay interval. Such behavior will not occur during the defibrillator tests defined in the ECG standards, since those tests do not utilize actual electrodes.



120.26084 Rev. 2 Copyright © 2001

Offset Control Diagram

How To Do Self TestingIt is useful to define two types of reactions to changes in the ECG system. The power up and ongoing self tests need to distinguish between these two types and react accordingly.

1. Equipment alerts - These basically notify the host system that a change has occurred which requires operator attention (e.g., an electrode has become disconnected, an electrode has too large an offset to be accommodated, the system has changed an ECG vector (due to losing an electrode) and the operator should be alerted to avoid misdiagnosis, etc.).

2. Equipment faults - These notify the host system that a problem has occurred which has (at least potentially) sufficient severity to warrant disabling the device from further use. Examples of such faults might be that the pacer detector, the lead fail detection system, or ECGO1’s LD1OR2 selection has failed its self test.

WARNING: Self tests can detect equipment faults that might distort ECG waveforms in such a way that they still look like real ECG signals, but could potentially lead to a misdiagnosis. Complications, injury, or death as a result of medication, surgery, or other treatment that is incorrect can often be prevented by detecting these equipment problems and notifying the operator or disabling the equipment.

GET LOW PASSFILTERED ECGO1

MEASURE ECGO1

OFFSET1ENABLED?

ENBL +OFFSET1

ENBL -OFFSET1

OFFSET1NEGATIVE?

OFFSET1POSITIVE?

DISABLEOFFSET1

DISABLEOFFSET1

ARE ALL THE ELECTRODESFOR ECGO1 CONNECTED? (& NOT USED AS A REF)

> +2.45V

< -2.45V -2.45 TO +2.45V

OFFSET1ENABLED?

Y

Y Y

YY

N

N

NN

N

TRACERESTORETHISCHANNELFOR 3 SEC

OVERFLOW?ENBL OFFSETTOGGLE POL

N

Y

GIVE EXCESSOFFSET MESSAGE

NEXTCHAN

~ 0.1 SEC CLK

DISABLEOFFSET1



Copyright © 2001 120.26084 Rev. 2

The ASIC’s ECG self test circuits are included as an aid in the power-up diagnostics of the ECG section of the instrument. While these circuits are not intended to provide a complete test to the published specifications of this ASIC, they do facilitate verification of the proper functionality of most of the ASIC’s basic ECG functions. Making use of these self test capabilities can satisfy many of the needs pointed out by an “FMECA” (Failure Modes Effects and Criticality Analysis)–the analysis of what problems can occur in an ECG system and how those problems may be detected by the instrument. One of the common checks in an FMECA is: “Can the system (or user) tell when an input or output is stuck?” (either signal or control). These and other self tests of the ECG circuits may be accomplished through the use of the EST register’s control bits. The status of the control bits in the EST register and in other ASIC registers that are not specifically mentioned in a test’s description do not affect that test. Since they prevent normal monitoring while they are being done, these tests should be done at power-up. (See also the end of the Self Testing section.)

Self Test DiagramBecause of the lengths of some of the required delays, it may be appropriate to run other system power-up diagnostics in parallel with these. The AD7716 A/D converter must first be set up to run according to its manufacturer’s instructions, and according to the host microprocessor’s needs for sample update rate, etc.

Note that multiple types of faults in the ASIC and supporting circuitry may cause identical failures of some of these self tests. It is beyond the scope of this testing to attempt to differentiate among causes for self test failures. It is considered sufficient to provide an indication that a problem of sufficient severity exists that the instrument should not be trusted, or that a condition must be corrected by the user.

Tests Of The Lead-fail Detection SystemBecause the 7 Hz low pass filters in the lead-fail detectors require time to settle, and the state of electrode connections prior to the start of these tests is unknown, it is necessary to force the tests to begin from a known starting condition. First, set INOPN HI, and set TSTON and RLPUP/ both LO. This allows the internal pullups to pull all five inputs HI. Allow 25 msec before reading the LFS register to verify that LF1-LF5 are all HI. After reading the LFS register, verify that LDCH/ (if used) is HI. To check that all five inputs can show as connected, keep INOPN HI and RLPUP/ LO, but set TSTON HI. Set SIGN LO to prevent any input from being held positive. (Setting the polarity of VTST to be negative is not required to cause status bits LF1-LF5 to show as connected, but it does speed up the settling delay of the filters relative to what that delay would be if some of the inputs were held at +130 mV.)



120.26084 Rev. 2 Copyright © 2001

Allow 60 msec as the worst case settling delay before checking that LDCH/ is LO. Then read the LFS register to verify that LF1-LF5 are all LO. Finally, check that LDCH/ has gone HI again. CLKIN must be running for these tests, or the LFOSC control bit must be set HI. If sleep mode is to be used, do these tests with both CLKIN alone and with LFOSC alone.

By opening the output of the Reference Electrode Driver (LDOPN=HI), tests of the ASIC’s ability to detect open electrode connections could be done so as to include the paths through the ESIS filters and patient cable. While this is a more complete test, it is made more variable in delay by the capacitance to ground of the patient cable. Also, the lead-fail results also become highly dependent on the charge on the patient’s body (if the patient is connected), on electrostatic discharges to and from the patient and ECG system, and on other connections to the patient if other parameters share the same isolation barrier. For these reasons, it is highly recommended that the lead fail tests be done as described in the previous paragraph.

If the designer still desires to do this test while the ESIS filters, etc., are included, the designer should conduct other tests to determine a suitable delay prior to checking for total lead fail.

Tests Of The ECG Channels’ Mode Bits and Ability To Pass SignalsFor all the tests below, unless otherwise specified, set control bits INOPN and TSTON HI, and set ECGOFF, OSON1-OSON4, SIGN, and PDTST LO (on both chips if two are used). On the Primary (or only) chip, while MODE0 and MODE1 are set for each of the ECG mode(s) that the chip uses, test with both states of TSEL. Based on which of the five inputs are fed to which of the four differential amplifiers (as controlled by the ECG mode and LD1OR2), and subject to the ASIC’s input offset voltages, the tolerances of VTST, and the gain tolerance of the sigma delta A/Ds, the four outputs ECGO1-ECGO4 should have nominal outputs as below. Note that proper responses in ECGO1 for the first three listed ECG modes provide a verification that the LD1OR2 control bit is not stuck–an important issue in preventing inaccurate diagnosis, because the ASIC provided Lead II when the system expected to get Lead I. That choice also affects all derived vectors as well. These tests also provide checks that the gains of the ECG signal paths are matched. Channels that are disabled by the ECG mode selection, such as ECGO3 and ECGO4 in “3-lead” mode, will have outputs of zero volts. ECG modes that are never used in a particular ECG design do not need to be tested, but testing of all others ensures that they do provide the expected signals. Allow 3 sample update intervals of the A/D for settling before checking the levels. Only one setting of the SIGN bit needs to be used while testing the first three ECG modes, since changing it would only change the polarities of all results. The operation of both polarities of all the differential amplifiers are already checked by the tests as stated.

For “3-lead” mode:

For “5-lead” mode:

“3-lead” Mode Test

SIGN TSEL ECGO1, LD1OR2=0

ECGO1, LD1OR2=1 ECGO2 ECGO3 ECGO4

0 0 0.0 V 1.04 V 1.04 V 0.0 V 0.0 V

0 1 0.0 V -1.04 V -1.04 V 0.0 V 0.0 V

“5-lead” Mode Test



0 0 0.0 V 1.04 V 1.04 V 0.693 V 0.0 V

0 1 0.0 V -1.04 V -1.04 V -0.693 V 0.0 V



Copyright © 2001 120.26084 Rev. 2

For “12-lead” primary mode:

“12-lead” secondary mode checks require setting up both chips, since the AVG3O of the Primary chip affects the outputs of the Secondary chip. The setting of LD1OR2 does not affect the outputs of interest on either the Primary or Secondary chip for the following tests. In the Primary “12-lead” chip, in addition to the general settings listed above, set MODE0, MODE1, SIGN, and TSEL LO.

For “12-lead” secondary mode, while the Primary chip has the settings listed in the previous paragraph:

Tests Of The Pacer DetectorTo test the Pacer Detector Circuit, control bit PDTST in the EST register may be used to generate a small step (approximately -4.25 mV) in VTST. (The level of PDTST’s signal was selected to be comfortably but not excessively above the detector’s threshold so that PDTST’s tolerance and any possible changes induced by temperature or noise would not result in a test that could be marginal.) While PDTST is HI, this negative step is added to the +130 mV or -130 mV level that already exists in VTST. Setting PDTST LO removes the -4.25 mV signal, causing a +4.25 mV transition in VTST. Both transitions should be used in the testing. (The pacer detector is not affected by the dc content of its input, but only by the transitions of that input.) The occurrence and timing of positive and negative transitions are controllable by the host processor’s writing the PDTST bit. CLKIN must be running to do these tests.

For all the tests below, it is assumed that an ECG design uses the pacer detector in only one ASIC. Until otherwise specified, set control bits MODE0, LD1OR2, LDOPN, INOPN, and TSTON HI, and set ECGOFF, MODE1, OSON1-OSON4, PDOFF, ADPT, SIGN, and PDTST LO. The pacer detector tests are set up in “12-lead” secondary mode for consistency of test signal voltages applied to all channels, though only the outputs actually used by the system need be checked, i.e., (for these detector source mux tests) it is not required to test with ECGO4 as a source in a system that only uses “3-lead” and “5-lead” modes.

The tests start with ECGO1 as the source and proceed from there with ECGO2, etc. Each row in the table below constitutes a separate test setup. If the system uses the AD7716 A/D with the PDETO signal fed into one of the A/D’s data inputs, it is necessary to allow for the variations in delay of PDETO making its way to the A/D’s serial data output. Note that (the serial bit defined for use by) PDETO will appear in the same data bit position for all four of the AD7716’s 32-bit output words, regardless of which vector is used for driving the pacer detector. Before starting the test, verify that PDETO in the serial data is LO. It may be necessary to wait for 5 msec for PDETO to settle if there is a glitch at the start of these tests. After PDETO is seen to be LO, set PDTST HI. Within 1 to 5 msec, PDETO should be seen as HI. Within 5 msec after PDETO was seen to go HI, PDETO should go LO again. After this has occurred, set PDTST LO. Within 1 to 5 msec, PDETO should be seen as HI again. Within 5 msec after PDETO was seen to go HI, PDETO should go LO again. This sequence checks detector operation with both pacer pulse polarities.

Change to the test setup of the next row in the following table and repeat the previous sequence. With each new row, it is still necessary to allow for the effects of a glitch at its startup. TSEL needs to be manipulated according to the following table to cause VTST to be included in all ECG output channels.

“12-lead” Primary Mode Test



0 0 0.0 V 1.04 V 1.04 V 0.693 V -0.347 V

0 1 0.0 V -1.04 V -1.04 V -0.693 V 0.347 V

“12-lead” Secondary Mode Test

SIGN TSEL ECGO1 ECGO2 ECGO3 ECGO4

0 0 -0.347 V 0.693 V -0.347 V 0.693 V

0 1 0.693 V -0.347V 0.693 V -0.347 V



120.26084 Rev. 2 Copyright © 2001

If the AD7716 is not used and PDETO is used to trigger an interrupt to the host processor, the same time intervals may be used. However, the actual delay between the stimulus and PDETO acting is less than 1 msec, and the duration of the PDETO output is 2.9 to 4.0 msec.

After the nonadaptive pacer detector performance is checked while being fed from each output, adaptive performance only needs to be checked while being fed from one output. Do this by setting THMIN and ADPT HI, and use the test setups from the top row of the above table. Cycle PDTST back and forth several times with one transition every 10 msec. After the effects of the setup glitch and the first four (or so) intentional transitions of PDTST, subsequent transitions of PDTST should not cause further outputs from PDETO. The tests of this paragraph may be repeated with THMIN set LO if desired, and the results should be the same as for THMIN set HI.

After the pacer detector source mux and basic adaptation features have been checked as above, more detailed checking of the detector thresholds may be performed. These checks apply to both the non-adaptive and adaptive-with-minimum-threshold modes. The tests must be done in the “12-lead” primary mode in order to take advantage of the lead weighting factors used by Lead V vectors. This facilitates checking of the pacer detector at 2/3 and 1/3 of the amplitude of PDTST.

Be aware that the pacer detector has a trip threshold that is dependent on the width of the pulses that are applied. Therefore, the self test software must control this width (by controlling the difference in time between writing PDTST HI and writing PDTST LO). If this process can be delayed by interrupts to the processor, that timing will not be well controlled and performance will vary, perhaps causing test failure.

For these tests, set LDOPN, INOPN, TMIN, and TSTON all HI, and set ECGOFF, MODE0, MODE1, OSON1-OSON4, PDOFF, ADPT, TSEL, and SIGN all LO. Toggle PDTST to generate 200 µsec pulses. Try it for both “polarities” of pulse. For non-adaptive mode (and for adaptive-with-minimum-threshold mode while pulse separation is greater than 30 msec) the pacer detector should trip on 2/3 amplitude pulses, but not trip on 1/3 amplitude pulses. (To do these tests, ECGO3 and ECGO4 must be used even if those outputs are never used in normal operation of the system. It is the only way to get smaller test pulse amplitudes.)

Pacer Detector Tests - MUX Tests

PDLS1 PDLS0 TSEL Source

0 0 0 ECGO1

0 1 1 ECGO2

1 0 0 ECGO3

1 1 1 ECGO4

Pacer Detector Tests - Threshold Tests

PDLS1 PDLS0 Source Pulse Amplitude(P-P)

1 0 ECGO3 -2/3 PDTST

1 1 ECGO4 1/3 PDTST



Copyright © 2001 120.26084 Rev. 2

Tests Of The ECG Channels’ Offset CapabilityFor tests on the Primary (or only) chip, set control bits MODE0, OSON1-OSON4, INOPN and TSTON HI, and set MODE1, ECGOFF, SIGN, and PDTST LO for that chip. These offset tests are set up in “12-lead” secondary mode, and both states of TSEL must be used in order to avoid including the effects of VTST in the channels under test. Subject to the ASIC’s input offset voltages, the tolerances of the EOS register’s offsets, and the gain tolerance of the sigma delta A/Ds, the four outputs ECGO1-ECGO4 should have nominal outputs as below. Ignore the ECG outputs for which the table entries are blank. Allow three sample update intervals of the A/D for settling before checking the levels. The setting of the SIGN bit does not matter, since VTST is zero in the inputs for which these tests are specified.

For the Primary (or only) chip:

To test a Secondary chip, set its control bits MODE0, INOPN and TSTON HI, and set MODE1, ECGOFF, SIGN, and PDTST LO. Initially, set OSON1-OSON4 LO. Testing the Secondary chip in a two-chip design requires setting up both chips, since the AVG3O of the Primary chip then serves as an input for the Secondary chip. In order to have the Primary chip’s AVG3O be enabled (as opposed to floating), the Primary chip cannot be set for “12-lead” Secondary ECG mode. All other ECG modes develop their AVG3O signal from the average of the RA, LA, and LL inputs. In order to guarantee a fixed level at the Primary chip’s AVG3O, independent of the connection states of the Primary chip’s electrodes, VTST must be present and nonzero in one or two of that group of three inputs. Hence, it is not possible to test the Secondary chip without having some effect from the Primary chip’s AVG3O. That effect must be subtracted out.

For the Primary chip, set control bits INOPN, TSEL, and TSTON HI, and set MODE0, MODE1, ECGOFF, OSON1-OSON4, PDTST, and SIGN LO. This setup puts the Primary chip into “12-lead” primary mode, and injects a non-zero VTST only into LL.

Measure and temporarily save the level at the Secondary chip’s ECGO1. Consider this to be the starting level from which all deltas are to be measured while the Secondary chip’s offsets are enabled. Enable the latter by setting the Secondary chip’s OSON1-OSON4 HI. For the following combinations of the Secondary chip’s OSGN1-OSGN4 and TSEL, measure the Secondary chip’s new outputs, and calculate the deltas to determine if the Secondary chip’s offsets are working correctly. Ignore the ECG outputs for which the table entries are blank.

Primary ECG Channel Offset Test

OSGN1-OSGN4 TSEL ECGO1 ECGO2 ECGO3 ECGO4

0 0 -1.840 V -1.840 V

0 1 -1.840 V -1.840 V

1 0 1.840 V 1.840 V

1 1 1.840 V 1.840 V

Secondary ECG Channel Offset Test

OSGN1-OSGN4 TSEL Delta in ECGO1 Delta in ECGO2 Delta in ECGO3 Delta in ECGO4

0 0 -1.840 V -1.840 V

0 1 -1.840 V -1.840 V

1 0 1.840 V 1.840 V

1 1 1.840 V 1.840 V



120.26084 Rev. 2 Copyright © 2001

Tests of the Reference Electrode DriverThe VTST signal described above is also available as one of the selectable inputs to the Reference Electrode Driver Circuit. Thus, by applying this signal through the common mode select multiplexer (LDIN0, LDIN1, and TSTON all HI), and setting the EIN1-EIN5 multiplexers in a normal (i.e. patient-connected) mode, functional operation the Reference Electrode Driver Circuit can be checked by selecting the reference electrode and checking the lead-fail status register while changing the polarity of the test signal (SIGN).

If the reference electrode is grounded, changing SIGN should not affect the lead fail status of the reference electrode. If the reference electrode is driven, its lead fail status should change with SIGN (lead fail for SIGN=LO).

Tests Of The Chest-Lead-Present DetectorThese tests require the use of hardware outside the ASIC. In the “5-lead” application schematic, this testing is controlled by the GPO2 output pin.

These tests require changing the voltage on the CLPIP input to temporarily force the CLP status bit into each of its states. These tests must be able to achieve this goal not only with no cable connected to the instrument, but also with any type of cable connected, with or without a patient connection. To force CLP LO requires forcing CLPIP below VDDRSP/2, so that the upper peak of the signal injected by CLPCLK into CLPIN will always be able to exceed this, even if the V electrode is grounded. To force CLP HI requires forcing CLPIP to exceed the highest upper peak (roughly 3.3 V) that can occur at CLPIN with no cable connected. For the latter, however, some significant time constraints exist.

Forcing CLPIP below 2.5 V for roughly 50 µsec or so is enough to cause the Chest-Lead-Present detector to switch to a LO state. However, the test to force CLP HI may need to keep CLPIP above 3.3 V for as long as 0.1 seconds before the CLP bit actually goes HI. This timing will vary from chip to chip and with changes in temperature. (For its intended use, CLP’s timing does not need to be at all precise.) Furthermore, a static discharge coupled into the ECG cable (any wire) in a way that forces the V wire up during this interval can restart the timing. This latter test may need to be run more than once to eliminate ambiguities in its results. (Because a patient with an implanted pacemaker may be connected while these tests are being done, the ASIC’s pacer detector cannot be used as a reliable indicator of whether such an interference glitch has occurred during the tests.)

For safety reasons, this test circuit is ac-coupled. This is done so that if GPO2 is left in the “wrong” state for any reason, it cannot prevent CLP from working normally. For an ac-coupled circuit to be able to create the pulse amplitude needed for forcing CLP HI, GPO2 must first be stable in a LO state for at least 0.3 seconds. To force CLP LO, GPO2 needs to first be stable in a HI state for at least 15.8 msec.

Set LDOPN HI, and ECGOFF, CLPOFF, and RSPON all LO. After holding GPO2 LO for at least 0.3 sec, set GPO2 HI. After 0.1 sec, read the CLP bit and verify it is HI. (If CLP is not HI, it is possible that a glitch has restarted the timing. Again, set GPO2 LO for 0.3 sec and repeat this test.) If CLP is HI, set GPO2 LO, and immediately read the LFS register to verify that CLP is now LO.

Running these tests during normal monitoring will likely cause glitches in both ECG and RESP.

Tests of the Respiration HardwareOther than echo checks on the RSP register, virtually the only conclusive tests that can be made on the RESP circuitry involve detecting nonsense conditions during normal operation. The nonsense conditions are:

1. No RESP fault is indicated while one of the electrodes used by RESP is indicated as unhooked by the ECG lead fail detection system.

2. The total impedance voltage is greater than about +0.1 V while RESP is supposed to be off.

Note that a total impedance indication of a level suitable for causing an “Inappropriate Cable” message may result from certain faults in the RESP circuitry, while the ECG cable truly contains proper resistors.



Copyright © 2001 120.26084 Rev. 2

There is a possibility (untried at the time of this writing) that some level of RESP testing may be done by checking for a pacer indication at the instant of enabling RESP in electrodes used for the source of pacer detection. There are many variables that will affect the efficacy of such a test, however, and it may not be conclusive. (Variables include whether or not a patient or even a patient cable is connected, capacitance of the patient cable, which electrode is used as a reference by ECG, etc.)

WARNING: There are many intrinsic problems with using impedance pneumography as a technique for respiration monitoring. There are also certain circuit failures that cannot be easily identified with system self-tests, but that could lead to the inability to detect apnea. Welch Allyn OEM Technologies strongly advises that the use of SpO2 monitoring be required as a safety feature during impedance pneumography respiration monitoring, especially for neonatal patients. For liability reasons, it may be in the best interest of the OEM company to never sell a respiration-equipped monitor that does not also include SpO2 capability.

Indirect TestsIndirect testing can find problems that might occur after power up testing is completed. This issue is of particular interest in ECG machines that may stay on for days or weeks without having their power cycled (e.g., in ICU or neonatal locations). Indirect testing involves looking for nonsense combinations of signals and behavior, and notifying the user when they occur. Indirect tests must be done continuously during normal patient monitoring.

The following are nonsense conditions that indicate failures during normal patient monitoring.

PDETO is stuck HI too long (e.g. >10 msec).

LDCH/ does not go HI again after reading the LFS register.

A respiration-equipped device shows no RESP lead fault while using either of the electrodes that the ECG system shows as disconnected.

Total impedance voltage is greater than about +0.1 V while RESP is supposed to be off.

During the infrequent times when the CLP bit is checked, if the CLP bit is LO, the LF4 lead-fail bit for that V electrode should not also be LO. (This test will need some filtering, etc., because of the lead fail detection delays, fast-attack-slow-decay of the CLP bit, etc.)

The CLP status bit is HI while the chest lead present detector is disabled.

Interrupts from the A/D still happen during sleep mode, yet sleep mode is expected to stop the A/D’s clock.

Miscellaneous Ongoing TestsThese tests can be done periodically without disrupting normal monitoring.

WARNING: It is possible that an ESD event or software problem during a write to the ASIC may corrupt the data stream from the processor. Doing a read-back-and-verify operation (“echo check”) each time an ASIC register is written to will detect such problems. This simple test can prevent mismatches between ASIC actions and what the host processor expects the ASIC is set up for. (It may also be beneficial to verify during any READ from the ASIC that all unused bits read back as LO.) This serves as an additional check on the serial data link. The consequences of mismatches can range anywhere from inconsequential to a false diagnosis and possible treatment for a non-problem. Without comparison with a separate table, the host processor cannot know whether an echo check shows a problem because a corrupted value was loaded into a “correct” register, or whether a “correct” (or corrupted) value was loaded into an incorrect register, leaving the “correct” register not updated. Unless a separate table is kept by the host processor from which all ASIC registers may be reloaded, it may be necessary to reset the entire ECG system and restart if an echo check fails.



120.26084 Rev. 2 Copyright © 2001

The system should perform checks of the supply voltages provided to the ASIC and its ECG processor. It should generate an error message and (typically) shut down if they are outside specifications. Also, the system should do a verification that the 2.5 V reference provided to the ASIC is correct within acceptable tolerance limits. Note that if the same 2.5 V (or a voltage derived from it) is used as the reference for the A/D that performs these tests, a separate reference input must be used to verify that the whole A/D system is truly working correctly.

The system must verify that the timing of CLKIN is correct. The simplest way to do this is to have the host processor’s clock be derived from a different crystal than the crystal used by the ASIC. Then have the host processor time the interval between the interrupts from the sigma delta A/D (assuming the latter is derived from the ASIC’s crystal), or to time CLPCLK or RSPREF directly.

Disable any ECG vectors that would otherwise be derived from a vector that is faulted in any way (faulted because of a lead fault on a required electrode, because of input offset that is too great, because it has failed a direct or indirect self test of any kind, etc.)

WARNING: The ECG self tests that cannot be performed during normal monitoring may still be done periodically during a total lead fail (all electrodes unhooked) situation. Such self tests are brief enough that the delay they may cause in the startup of monitoring after electrodes are connected is negligible. This is highly recommended for applications that are unlikely to have their power cycled at least once per day.

Component InformationThe information below is provided as a courtesy to OEM customers. It includes manufacturers of certain parts, and in some cases the reasons for part choices. Single-source parts are identified. Multiple-sourced parts show one or more manufacturers. Commonly used parts do not include exhaustive manufacturer lists. Supplemental information is also included about passive components.

ICs: The 4053B is made by Motorola, Fairchild, Toshiba, and SGS-Thomson. It was chosen because of its low cost, moderately low capacitance, tolerable ON resistance, and the internal level shifters on the control inputs. It is very advisable to select two vendors that have the same capacitance for this part.

Analog Devices is the only source for the AD7716. This part was evidently developed by Analog Devices specifically for medical equipment customers. Its popularity with more recent customers has caused demand to outstrip production temporarily. Place orders early! Analog Devices recommends contacting the following list of their most active distributors for the AD7716:

Future Electronics 800-388-8731Avnet 800-332-8638Pioneer 800-657-0168Newark 800-463-9275

The LF353 is made by National Semiconductor (now Fairchild) and Motorola (and likely by others), and was chosen for its JFET inputs, BW, slew rate, ±5 V is within its supply range, it still has a sufficient output swing with ±5 V supplies, and its supply current is tolerable for its speed.

The TLC27M2A is made only by Texas Instruments, and was chosen because of its (low input current) MOSFET inputs, sufficiently low input offset voltage, sufficiently large output swing, and ±5 V is within its supply range. It is quite likely that other suitable CMOS op amps are available from other manufacturers.

The 74HCU04 is made by Motorola, and was chosen because its unbuffered output gives lower gain. This makes it much better suited than a 74HC04, etc. for oscillator applications, and having fewer internal stages yields a lower supply current while used in an oscillator.



Copyright © 2001 120.26084 Rev. 2

Discrete semiconductors: The BAV99 is made by Motorola and many others, and was chosen for its low cost and many sources. The BAT54C (and other varieties) are made by Philips and Fairchild (formerly National Semiconductor). It was chosen because it was a small Schottky part, of reasonably low cost for a Schottky, and its low current rating was not a problem. The IRLML2402 and IRLML6302 parts are made by Temic (formerly Siliconix). They were selected because the circuits driving them cannot provide much drive current to turn them on, and because of their low ON resistance at low gate voltage, small size and low cost. The MMBT3904 is made by Motorola and many others. It was selected because of its small size, low cost and ready availability. The MMBZ5232B Zener is made by Motorola and others.

Resistors: Resistors of 1 MΩ and lower should be metal film parts of 1% tolerance and 100 ppm/˚C temperature coefficient. The 10 MΩ parts can be carbon film, 5%, 200-500 ppm/˚C. As mentioned in the Component Voltage and Power Ratings section (page 59), the resistors in the ESIS filter circuits should be 1206 size for voltage breakdown and surge handling reasons. For the same reasons, R1, R4, R6, R10, R12-R15, and R19 in the respiration circuit should also be 1206 size. All other resistors can be as small as desired, subject to achieving the 100 ppm/˚C temperature coefficient. SMD resistor manufacturers include Dale, Koa Speer, Rohm, AVX/Kyocera, Philips Components, etc.

Capacitors: All capacitors shown in the applications schematics either include a tolerance on the schematic, or, if unspecified, may be up to 20%. The 1% and 2% capacitors in these circuits generally need to be NPO dielectric types to obtain the tight tolerance. The 5% and 10% parts are generally available in X7R dielectrics. The 20% parts may have X7R or Z5U dielectrics. The schematics show 0.1uF capacitors with 10% and unspecified tolerances. The user may want to make them all 10% in the interest of reducing the number of line items in the bill of materials. Voltage ratings on all capacitors except the 220 pF 1% parts need only be 16 V or more. When used in any of the respiration circuits, or as the first capacitor in the two-stage ESIS filter shown in the “5-lead” applications schematic, the 220 pF capacitors need to be rated at 200 V. They need to be 805 or larger size because of the voltages they experience during defibrillation. (Note that manufacturers of NPO capacitors claim that such capacitors will tolerate 2.5X their voltage rating.) When used as the only capacitor in the single-stage RF filter shown in the “12-lead” applications schematic, the 220 pF capacitors can be rated as low as 16 V. SMD capacitor manufacturers include Kemet, AVX/Kyocera, Philips Components, Murata/Erie, etc. The 220 pF 1% NPO caps and 100 pF 1% NPO caps are made by AVX/Kyocera and Kemet.

Crystals: From the perspective of circuit operation, the crystal can have the loosest tolerance (0.05-0.1%) and temperature coefficient offered by the manufacturer, though the user’s system constraints may require a tighter tolerance. Crystals are parallel resonant, are for a load capacitance of 15-20 pF (net), have no minimum series resistance requirements, and will not have a power applied to them to exceed any crystal’s limits. Both 5.213 MHz and 7.82 MHz are custom frequencies. Crystal manufacturers include Saronix, ILSI America, Ecliptek, Abracon, Fox, etc.

Neon bulbs: See the Neon Bulb Test Results section (page 58) for specification details. Neon bulbs are made (or at least sold) by Chicago Miniature Lamp, Gilway Technical Lamp, JKL Components Corporation, Lamptronix Company LTD, and others.

RF SusceptibilityBecause the ASIC uses only CMOS technology, it is much more tolerant of RF than devices that use bipolar transistor technology. In typical ECG designs, the components most likely to use bipolar technology include the 2.5 V reference and some switching power supply controllers. Depending on the field strengths and frequencies to be rejected, and on the physical location of these components within the complete system, RF susceptibility solutions may require anywhere from nothing out of the ordinary to combinations of shielding, ferrite beads, additional RF bypassing , and very careful board layout in order to meet design goals. The ASIC and AD7716 do not prevent meeting these goals. The AD680 2.5 V reference proved somewhat challenging, but suitable decoupling and bypassing triumphed over very high levels of RF. Any further discussions about how to design an ECG system to withstand RF are outside the scope of this document.



120.26084 Rev. 2 Copyright © 2001

Layout Considerations

Signal RoutingTo prevent interference due to improper routing of digital signal traces, all ASIC asynchronous digital signals (LDCH/ (and any OR’d combination of two LDCH/s), CS/, DIN, DOUT, and SCLK) as well as any digital signals from, through, or to other parts of the ECG front end, including the A/D, must be kept sufficiently away from all ECG analog circuits. This means such signals should not be on either outer surface metal layer immediately under the ASIC or A/D’s packages (where they could couple interference directly into the dies of these parts), or under any resistor or capacitor used by any of the ECG analog signal paths all the way from the ECG cable connector through inputs to the A/D. An intervening ground or power plane layer must be located between these components and digital traces. Digital signal traces and analog signal traces that are in close proximity to each other must not run parallel to each other, at least without an intervening grounded guard trace while on the same board layer.

Beware having a digital trace on one layer be parallel to and in close proximity to an analog trace on an adjacent board layer without an intervening plane layer. A recommend practice is to use a 6-layer board construction with planes on layers 2 and 5, so that sensitive signal traces may be easily shielded between those two planes. Finally, check that vias on an analog signal net do not pass through the board at locations very near digital signal traces on any layer, and vice versa.

It is important to keep digital signal traces away from all analog components to avoid noise coupling. In particular, keep PDETO out of these areas, or a self-sustaining oscillation of pacer indications may result. The typical way of using the serial interface with infrequent bursts generally allows those signals to interfere with ECG if their traces can couple into the analog circuits. LDCH/ is physically adjacent to CLPIN. While the coupling between these signals inside the ASIC is acceptably small, external additional coupling can briefly disrupt the chest-lead-detector following transitions of LDCH/.

It is also a good practice to keep signals like CLPCLK, RSPREF, and the respiration outputs well separated from analog circuits, even though their steady, higher-repetition rates make them less susceptible to causing interference. ECGON and RSPOFF, though still digital signals, change very infrequently, and it is normal to expect major disturbances when the entire ECG or respiration section is turned on or off.

MiscellaneousSignals GPO1-GPO3 can create a noise coupling problem depending on how they are used. Using one for a respiration lead selection control should not be a significant problem, but other uses may require keeping those signals isolated from analog circuits.

While HWTST has an internal pull-down, it is an exceptionally weak one. To avoid having problems with ESD forcing the ASIC into default conditions, it is a good idea to ground HWTST (either literally, or through a 10 kΩ or lower resistor). Avoid a long circuit board trace.

Be aware that the neon bulbs bring interfering signals inside the shields. To prevent coupling of such interference into other circuits, do not fold the neon bulbs over the top of other circuits, including the ESIS filters.

Keep neon bulbs in a tight cluster away from all other circuitry. Make the ground-side connection of all neon bulbs be grouped together in an “island” of ground plane. Surround that “island” almost completely by a void in the ground plane, so that connection between the island and the rest of the ground plane occurs at only one point. This prevents any high currents during defibrillation from circulating outside the “island”. Locate the connection point to the “island” as far as possible away from all digital circuitry.



Copyright © 2001 120.26084 Rev. 2

Ground PlanesBased on user questions, it is appropriate to discuss how ground plane(s) are to be implemented. In the application schematics, only a single type of ground symbol is shown. This was deliberate. All of these circuits have been implemented on circuit boards that used a single ground plane, shared by analog and digital circuits. From a physical perspective, circuit placement in a production instrument was as follows, starting at one edge of the board and moving to the opposite edge: ECG/RESP input circuits, ASIC(s), ADC(s), processor and its supporting digital circuits, linear supplies, and switching supplies. The only split in this ground plane was for the ground return side of all the neon bulbs, as discussed in the preceeding paragraph.

When the application circuits were incorporated into the complete product with such a ground plane implementation, they successfully passed all required regulatory testing for RF emissions (Level B), RF susceptibility, and ESD. In addition, the noise floors of the ECG and RESP channels easily met regulatory and clinical requirements. This is offered as proof that it is NOT necessary to use split planes to meet regulatory requirements or to achieve sufficiently low channel noise if parts placement and trace routing are done properly.

Despite the popular approach being to use separate ground planes for analog and digital circuits in an attempt to minimize channel noise, the writer has seen many instances where using split planes backfired. In those instances, the magnitudes of problems with RF emissions and RF and ESD susceptibility increased, yet channel noise was not lowered much–if at all. While splitting ground planes is appropriate in some instances, as discussed below, it is not a substitute for careful parts placement and routing!

Creating a separate portion of ground plane in which to confine the switching currents of switching power supplies is sometimes appropriate for higher current supplies. Certainly it would be a disaster to allow such currents to flow into sensitive analog circuit areas. (The ac magnetic fields generated by switchers can induce signals into nearby circuits despite whatever grounding is used, so the analog circuits and switchers must be physically separated anyway.) However, unless the voltage drops they create in the ground plane are large relative to logic levels (and if they are, other problems will exist anyway!), switching supplies and digital circuits can easily coexist on a contiguous ground plane. This is particularly true with low power switching supplies. (Do ensure that no switcher ground plane currents can circulate into areas used by crystals, particularly if a crystal is used in a phase-locked-loop!)

Noise spikes in signals that are to be digitized by a successive approximation A/D converter will affect the digitized result if the spikes occur during the acquisition time of the converter. Digital and switching supply spikes cannot be allowed to enter such circuit areas. Ground plane separation may help this, but so will physical separation of the circuits alone.

Some high frequency circuits must have their ground currents confined in order to meet RF emissions. Such instances are beyond the intended scope of discussion in this manual.

Having stated the above items, it is then appropriate to state why, for the application circuits in this manual, that splitting up ground planes is not appropriate, or is even unnecessary.

• Any digital lines that cross the gap between analog and digital ground planes will add much to the radiated RF emissions from the board, if those lines are switched repetitively. RF currents created by digital signals flowing through these lines must necessarily have a return path. Ideally, such return paths will be induced in the plane layers adjacent in the board sandwich to the digital signals traces. This minimizes the loop area through which such RF currents must flow, and as a result minimizes the amount of RF they will radiate. Splits in the planes force RF return currents from traces that cross them to find another path, and that path will often have a dramatically larger loop area unless extra steps are taken. The result is higher RF radiation levels.

• None of the ICs in the application circuits have large-magnitude spikes in their digital current require-ments. What surge current needs they do have may easily be provided by bypass capacitors located right next to their supply and ground pins. This localizes such spike currents into very small loops, so that the supplies are glitched only minimally, and the RF energy radiated is small.



120.26084 Rev. 2 Copyright © 2001

• If a digital ground plane is used for the ground connection of bypass capacitors whose other ends go to quiet analog supplies, any noise on the digital ground plane will be inherently well-coupled into the analog supplies. This can degrade otherwise quiet analog supplies!

• When transients like ESD couple into a circuit board, they can cause large transient voltage differences between the divided portions of a ground plane. When ICs use supply and ground connections that are split between these divided plane portions, such transients can turn on parasitic structures inside those ICs and give unpredictable (and almost always undesirable) results! Transient differences between ground plane portions can also cause big glitches in digital signals that pass through both ground sections.

• Sigma delta A/D converters are, in a sense, slew-rate-limited tracking converters. The effect of noise glitches in the signals they digitize is also integrated over the entire sample-to-sample interval. Conse-quently, errors caused by glitches in converter inputs are much smaller with this type of converter.

For all these reasons, it is highly recommended that all portions of the application circuits use a common contiguous ground plane.

If the rest of the board on which these parts are located uses split planes, then locate physically next to the applications circuits the linear regulators (for analog “+5V”, “–5V”, and VDDRSP) and the 2.5V reference used by them, and have these linear supplies and reference share the application circuits’ ground plane. Make a single connection between this localized ground plane and the digital ground plane used by the rest of the board. Make that connection be located where the digital lines for connection between the processor and ASIC + ADC cross between the two plane sections, and make the connection be wide enough so that all interconnecting digital lines fit in its “shadow”. Decouple (with a 100 series resistor) the logic supply for the ASIC (VDDIO) from the logic supply used by the processor that interfaces with the ASIC.

As always, it is a good practice to keep supply bypass capacitors close to the chip pins that they bypass. This not only improves circuit stability, but also minimizes coupling of external electrical noise into the ASIC and A/D converter.

Spacings

CAUTION: If the ECG application must tolerate defibrillator discharges, the board spacings around the ECG connector, neon bulbs, and input filter components should be large enough to avoid arcovers. (See ECG ESIS Input Filter and Defibrillator Protection, page 55, for the voltages to expect during defibrillation.)

Two sets of spacings must be considered. Because there is a separate neon bulb clamp for each electrode, it is quite possible for one to clamp at +800 V, e.g., while a physically adjacent bulb is simultaneously clamping at -800 V. Thus the voltage between the non-grounded sides of these two bulbs will be twice as high as the voltage from either of them to ground. The same applies to all the resistors and capacitors to which the neon bulbs connect. Between circuit portions that can have high voltages of opposite polarity on them in this manner, provide creepage distances of 0.050” wherever possible, minimum 0.045" between conductors not covered by solder mask, and minimum 0.035" between conductors where one or more are covered by solder mask. Between high voltage nodes and circuit connections that are at, or very nearly at, ground potential, provide creepage distances of 0.025" wherever possible, minimum 0.023" between conductors not covered by solder mask, and minimum 0.020" between conductors where one or more are covered by solder mask.

Spacings greater than these minimum numbers provide a safety margin. These spacings have been found to work acceptably in practice on boards with solder mask. Be aware that when an arc occurs between circuits on a board, it leaves a board-surface carbon track that is very difficult to remove. When such an arc-over happens during defibrillation of a patient, further ECG monitoring may be impossible at the very time the clinician needs it most–namely, to see if the patient’s ECG has returned to normal. Consider these spacing issues very carefully!



Copyright © 2001 120.26084 Rev. 2

It should be understood that these spacings are based on two assumptions:

1. The series current limiting resistors are physically located in the ECG cable. In this configuration, the peak voltages between pins of the circuit board’s ECG connector are limited solely by the clamping action of the neon bulbs. If any series resistors are configured between the board’s ECG connector and the neon bulbs, the voltages at the board’s ECG connector will be larger than expected. The latter forces a need for larger spacings in and around the board’s ECG connector, and for the added resistors between that connector and the neon bulbs.

2. The ECG monitor will see only occasional discharges from a defibrillator. Insulation breakdown through or across materials other than air is usually a progressive thing, so that often-repeated discharges may break down spacings that a low quantity of discharges may not break down. More to the point, creepage spacing requirements for the ECG front end of a defibrillator are beyond the scope of this document, and the designers of such must make their own determination of spacing needs.

What constitutes an acceptable creepage distance to withstand peak voltages during defibrillator discharges is a function of more than just peak voltage. The shape of board pads affects breakdown voltage between pads or between a pad and a trace. With all other conditions being equal, rounded pads will tolerate higher voltage before breakdown than will square or pointed pads. Consider that spacings from pads for through-hole parts (e.g. neon bulbs) may be affected by which direction their leads are clinched before soldering. Any rework process that leaves added points of solder, particularly sideways points of solder, can also shorten effective creepage distances. When considering creepage distances between a pad and a trace, having solder mask covering the trace will (usually) raise the breakdown voltage between pad and trace. This will not always be true since the solder mask will sometimes have pinholes through it, and the locations of such pinholes are unpredictable. Board surface contamination (particularly from fingerprints, etc.) may lower breakdown voltages. Leftover solder flux, etc. may provide such contamination if it is an aggressive type (which often means it is electrically conductive as well). Moisture condensed on the board is another detrimental factor. For a given spacing, breakdown voltages will be lower while operating at higher altitudes. For reasons of all these variables, it is safest to provide the largest spacings possible.

If a two-stage ESIS filter is used, spacings around the first capacitor of each should be as stated above. Normal board spacings apply to the last capacitor of such filters (or at the only capacitor of single-stage RF filters), because voltages there are clamped to ±5 V by the ASIC. Treat the C33-ends of R29 and R30 (CLP circuits) like they were connected directly to LP4. In monitors with respiration, board creepage distances apply to portions of the respiration circuits as well. The 0.1 µF capacitors C1, C4, and C7, as well as the patient end of the 220 pF capacitors C2, C5, C8, and C12-C14, have virtually the same voltage on them as do the neon bulbs. The ends of these 220 pF capacitors that do not connect to the 0.1 µF capacitors (but connect to resistors instead) have sufficiently fast time constants relative to the time it takes an arc to ionize so that the more relaxed spacings may be used between these nodes of different electrodes, and between each node and ground. Treat the 220 pF capacitor-ends of R1, R4, R6, R10, R12-15, and R19 the same way as the 220 pF capacitors to which they connect.

Software RequirementsThe ECG software must handle the following items: serial communication with the ASIC(s) and A/D converter(s), forcing synchronized operation of all ECG A/D channels, decision-making about which electrode to drive or ground based on cable type and number of electrodes connected, lead-failure reporting, enabling or disabling of additional channel offsets, high-pass filtering to 0.05 Hz (and 0.5 or 0.67 Hz for purely monitoring applications), optional low-pass filtering to 40 Hz when the A/D converter’s upper frequency limit (95 Hz or more) is not desired, trace restoration following large dc changes, drift compensation, deriving of ECG vectors not directly provided, reporting channel offset too great to allow any ECG channel use, selecting a vector for pacer detection and responding properly to ignore pacer pulses, QRS-picking and other desired signal analysis, power mains frequency notch filtering, self-diagnostics (see How to Do Self Testing section on page 63), rate alarm handling, waveform display and transmission, and other tasks.



120.26084 Rev. 2 Copyright © 2001

If this ASIC is to be used in a device that also offers invasive blood pressure (“IBP”) monitoring capability, it is helpful to allow the operator the ability to select IBP as the primary heart rate source. The latter will provide a more stable heart rate indication during electrosurgical interference.

WARNING: It is the responsibility of the designer of the host system to make sure that the pacer detector’s selected source is only allowed to be an ECG channel which is enabled by the ECG mode bits (MODE0 and MODE1), and which does not use electrodes that are not connected.

The respiration software must handle the following items: handling of level of total patient impedance relative to generating messages indicating inappropriate cable, noisy electrodes, respiration fault, high-pass filtering to 0.05 Hz, low-pass filtering to a net -3 dB frequency of 4 Hz, trace restoration following large impedance changes, drift compensation, ignoring the possible effects of pacer pulses on the respiration signal, breath-picking, apnea detection, ignoring of cardiovascular artifact in the respiration signal, rate and apnea alarm handling, waveform display and transmission, and other tasks.

CAUTION: It is important to notify the operator when the total impedance seen by the respiration channel is below the minimum expected impedance. Typically this occurs when there are no current-limiting resistors in the ECG cable. If the patient needs to be defibrillated while connected to such a cable, the ECG front end may likely be destroyed. Providing an “inappropriate cable alert” message can help prevent this.

WARNING: Certain types of implanted pacemakers use narrow spikes of injected current to obtain an indication of respiration rate or minute volume. Such pacemakers may be adversely affected by an instrument’s respiration carrier if the frequencies of each result in a beat note inside the pacemaker. It is most helpful in those circumstances if the instrument’s respiration carrier can be truly shut off when the respiration channel is “turned off” by its user. (Unfortunately, some instruments remove the respiration trace from the display and do not process the signal, yet leave the carrier on. Under these circumstances, clinicians must either use a different type of monitor, or force the pacemaker into its “magnet mode”.) For this reason, it is highly recommended that the circuit use the capability to set the RSPON bit LO to halt the carrier when respiration is not in use, even if the remaining respiration circuitry is implemented without including the power-down feature.

WARNING: The designer should be aware that pacer pulses of high enough amplitude to saturate U1 in the respiration reference circuit will propagate into the RESP channel output. Such pulses will be significantly rounded off and stretched by the RESP channel’s low pass filtering, and may sufficiently resemble breaths that they could be counted as such. (Virtually any impedance pneumography design will exhibit this behavior for the bigger pulses in the AAMI-specified range.) The host system software that deals with rejecting cardiovascular artifact must also be able to deal with this phenomenon. Switching to the RESP vector that has smaller pacer artifact may be helpful in reducing such interference.

Note that for a given pair of electrodes, it is possible to have a respiration lead fault and no ECG lead fault, but the reverse is extremely unlikely. Respiration lead fault occurs when the ac impedance between the pair of electrodes used by respiration exceeds about 1.5 kΩ (electrode plus patient impedance). Respiration cannot isolate a fault to a single electrode, only to a pair of electrodes. ECG lead fault occurs when the voltage of any single electrode rises above the lead-fail detection threshold (0.48 or 0.73 V nominally with respect to circuit common). ECG lead-fail detection can definitely identify individual electrode faults.

Poor electrode contact is the usual cause of high ac electrode impedance and respiration faults. Poor electrode contact also raises the dc electrode impedance, but with a lead-fail detection current of 70 nA, dc impedance can theoretically be so high that a very noisy ECG signal results, without the voltage drop exceeding the lead-fail detection threshold. Fortunately, an electrode’s dc impedance usually falls into one of the ranges of “not too noisy” or totally disconnected.



Copyright © 2001 120.26084 Rev. 2

Only with very high electrode dc offsets simultaneously with good ac contact could a given pair of electrodes cause an ECG lead fault but not a respiration lead fault. (These two conditions might occur simultaneously following patient defibrillation, but only for a short interval.) Therefore, respiration lead faults should be indicated separately from ECG lead faults, but respiration lead faults do not need to be indicated at all if an ECG lead fault is indicated for one of the electrodes used by respiration.

Be aware that when there are no electrodes connected and software is cycling its choice for a reference electrode, that cycling may cause the respiration channel to have a pulse in its output each time a different reference electrode is tried. Software should be configured to ignore this.

NOTE: Be aware that sigma-delta A/D converters generally do not clip gracefully when their input dynamic range is exceeded. Because sigma delta A/Ds resemble tracking A/Ds in this sense, they require multiple samples to recover from overload. The AD7716 sets an overflow indicator bit when clipping occurs, since the conversion data itself is indeterminate during clipping. Software must deal appropriately with such behavior.

REGULATORY AND SAFETY ISSUES

High-Criticality FailuresThrough Failure Mode Effects and Criticality Analysis (FMECA), Welch Allyn OEM Technologies has identified some of the possible high-criticality failures associated with implementation of the ECG ASIC. The warnings about these failures and issues are listed in the manual sections that are more specifically dedicated to the various problem areas. The following table summarizes possible high-criticality failures and provides suggestions for detecting these failures and mitigating the risks.

WARNING: It is the sole responsibility of the host system device manufacturer to complete all hazard and failure analyses (including FMECA) on the device design, including the ECG ASIC component, and to take appropriate action to meet all regulatory, performance, and safety standards relevant to the intended use and market application of the medical device. The information listed in the table below is intended to supplement, but not replace, the host system manufacturer’s own analyses.

High Criticality Failures and Possible Solutions

Item Problem Possible Solution

1 Misdiagnosis because vectors are “distorted”, due to mode select bits or LD1OR2 stuck in unexpected state.

Self tests check whether outputs are correct for each setting of LD1OR2 and for all modes that can be used in system.

2 Cannot detect ECG lead failure during conditions of high humidity or damage inside ASIC. May miss detection of asystole.

Use included self tests of ECG lead fail detection system, and coordinate with RESP lead fail detection system. Properly clean boards.

3 Microshock hazard because ASIC input pins or lead driver output stick at supply rails.

Use input filter total resistance >100 kΩ to limit current to safe level.

4 Misdiagnosis because an ECG output is stuck, has the wrong gain, or two inputs are shorted together, and any waveform derived from it is distorted.

Use self tests to check for this and disable any waveforms that would be derived from that vector.

5 Cannot detect asystole due to noisy, erratic, or intermittent operation of ASIC, ECG cable, or board.

Make use of the multiple ECG channels, use recommended protection circuits, properly clean board.

6 Misdiagnosis because AVG3 doesn’t work, distorting Lead V signals. Do self tests that check out AVG3.

7 Pacer detector cannot work because it is set to a disabled or lead-failed channel, and misses detecting asystole because the QRS picker picks overshoots of “dead man” pacer pulses.

Use all lead fail detection systems as recommended, and structure host’s software so it never selects an inappropriate ECG channel as the source for pacer detection.

8 Pacer detector fails or is intermittent, so it misses detecting asystole because it counts “dead man” pacers.

Use ASIC’s self test circuits and recommended self tests to check pacer detector operation.

9 Pacer detector response is delayed, so it misses detecting asystole because it counts overshoots of “dead man” pacers.

Use ASIC’s self test circuits and recommended self tests to check pacer detector operation, and do system tests to verify frequency and operation of CLKIN.



120.26084 Rev. 2 Copyright © 2001

In order to meet the 50 µA single-fault patient auxiliary current limits of ANSI/AAMI ES1-1993, Section 4.3.2, the designer must include sufficient resistance between the ASIC’s EIN1-EIN5 pins and the patient electrodes so that the current limit is not exceeded, even if the ASIC fails and applies +5 V to one electrode and –5 V to another electrode. Practically speaking, this means the total resistance in each input filter must add up to greater than 100 kΩ. Also, user implementations that include respiration must also include redundant dc-blocking capacitors in series between respiration circuits and the electrodes used by respiration. Safety agency requirements will not be met if these things are not done, and it is the designer’s responsibility to do so.

In order to meet the normal lead-fail detection current limits of ANSI/AAMI EC13:1992, Section 3.2.5, the designer must properly control the lead-fail detection current source for RL. If the RL current source is enabled while using a 3-lead ECG cable that contains an intentional short between its RL and LL electrode pins (or between RL and any other electrode), that (100 nA maximum) current limit will be exceeded. This is caused by summing the lead-fail detection currents for two electrodes (RL and LL) through such a short into one actual electrode (LL). Use the chest-lead-present detector function of the ASIC to determine if the cable contains a wire for a V electrode. If it does not, the cable is almost certainly a 3-wire cable. With this ASIC, RL does not need to be checked for a lead fault condition under these circumstances, so do not enable its current source. Enable the RL pullup only if a V-wire is present.

While presently not a requirement for sale in the United States, clause 51.103 of EN60601-2-25 and EN60601-2-27 require an ECG device to include a means “to indicate that the equipment is inoperable due to an overload or saturation of any part of the amplifier.” In implementations using a sigma delta A/D wired directly to the ASIC outputs, this means that when the average dc level at an A/D input gets close to either limit of the A/D’s input range, such an indication must be given. (This occurs while appropriate ECG electrdoes are connected, but their dc offsets are too large. The system may use the ASICS’s offset capability to deal with such a problem, and report the inoperable condition only if adding the offset does not correct the situation.)

10 Adaptive pacer detector adapts too well, does not detect real pacer pulses, and misses detecting asystole because it counts overshoots of “dead man” pacer pulses as QRSs.

Use ASIC’s self test circuits and recommended self tests to check pacer detector operation. Production tests must verify proper value of cap-to-ground from ASIC pin 37.

11 Device nonoperative due to both VDDA pins open. ASIC uses redundant supply pins. Many self tests will fail.

12 Some patient conditions and circuit failure conditions may prevent detection of apnea.

Self tests are of only limited help, particularly for patient-related issues. Recommend use of SpO2 in parallel as a safety backup.

13 Microshock hazard if a RESP series capacitor shorts out. Use redundant series capacitors in RESP paths.

14 Can’t detect asystole because erratic pacer detector operation (due to intermittent cable contact, etc.) allows counting overshoots of “dead man” pacer pulses as QRSs.

Include in Operator Directions For Use manual the AAMI EC13’s warning statement about not trusting heart rate meters, and not leaving unattended patients with implanted pacemakers.

High Criticality Failures and Possible Solutions (Continued)

Item Problem Possible Solution



Copyright © 2001 120.26084 Rev. 2

ASIC Performance Specific To EC13-1992 And EC11-1991 RequirementsThe versatility and the fidelity of the performance of the ASIC meets the applicable hardware requirements for both EC11-1991 and EC13-1992. Many of the requirements identified in these standards, including all EC13 and EC11 requirements not specifically listed here, are determined and affected by software and external hardware design. Following are the requirements that must be, and are, met by the ASIC alone.

Related DocumentsANSI/AAMI EC11-1991 - American Standard for Diagnostic Electrocardiographic Devices, 1991 ed.

ANSI/AAMI EC13-1992 - American Standard for Cardiac Monitors, Heart Rate Meters, and Alarms, 1992 ed.

ANSI/AAMI EC38-1998 - American Standard for Ambulatory Electrocardiographs, 1998 ed.

ANSI/AAMI EC53-1995 - ECG Cables and Leadwires.

ANSI/AAMI ES1-1993 - Safe Current Limits for Electromedical Apparatus, 1993 ed.

AAMI ECGC-5/83 - Standard for ECG Connectors, 1983 ed.

EN60601-1:1990 (and later amendments) - Medical Electrical Equipment, General Requirements for Safety.

EN60601-2-25:1996 - Medical Electrical Equipment, Particular Requirements for Safety, Specification for Electrocardiographs.

EN60601-2-27:1995 - Medical Electrical Equipment, Particular Requirements for Safety, Specification for Electrocardiographic Monitoring Equipment.

IEC Publication 812 - Analysis Techniques for System Reliability - Procedure for Failure Mode and Effects Analysis (FMEA), 1985 ed.

DEVELOPMENT AIDSFor development purposes, sockets are available that accommodate the ASIC’s 52-pin plastic quad flat-pack package. The following manufacturer makes two styles of sockets for this purpose:

Enplas Tesco, Inc.765 N. Mary Ave.Sunnyvale, CA 94086

www.enplas.comPhone: 408-749-8124Fax: 408-749-8125

Requirements for EC13 and EC11

EC13 Section EC11 Section Requirement Description Performance Comment

3.2.1 3.2.1 Operating temperature range Exceeds 0° to 70°C

3.2.5 3.2.10 Lead-off sensing current magnitude Exceeds ALL are lower than max. allowed

3.2.9.1 3.2.3 Input dynamic range Exceeds Programmable -100 mV to 500 mV, -500 mV to 100 mV, or ±300 mV

3.2.9.2 3.2.9 Input impedance Exceeds ASIC and included filters

3.2.9.3 3.2.12.1 System noise Exceeds Noise < max. allowed

3.2.9.4 3.2.12.2 Multichannel cross-talk Exceeds < max. allowed

3.2.9.5 3.2.4.4 Gain control/stability Exceeds Specific to stability

3.2.9.8 (d) 3.2.7.3 Input signal reproduction accuracy, lead weighting factors

Exceeds For all of the vectors developed by ASIC



120.26084 Rev. 2 Copyright © 2001

Part Numbers:OTQ-52-0.65-01FPQ-52-0.65-01A.

A Development Kit (Part Number 000.91162) including five ASICs and a socket is available from Welch Allyn OEM Technologies. Contact Welch Allyn OEM Technologies for details.

PACKAGE MECHANICAL DRAWING

Package Mechanical Drawing

39 27

40

52

1 13

26

14

PIN 1 INDICATOR

SEATING PLANE

J RADIUS

C D

A B

E

F

H

G

K

L

PACKAGE MARKINGSLine 1 Manufacturer’s name, standard date and

traceability markingLine 2 ©1999 PRYONLine 3 442001600-A (abbreviated version of Part

Number 442-0016-00, Rev. A; Note that the ECG ASIC is purchased in quantities as P/N 000.91163)

Dimensions (mm)a

a. There are several varieties of package styles. Each style varies slightly in features, pin 1 indicator, dimensions, and tolerances. This table includes the full range of dimension variations.

Min Nominal Max

A 13.65 13.90 14.15

B 9.90 10.00 10.10

C 0.65 BSC

D 0.22 - 0.38

E 9.90 10.00 10.10

F 13.65 13.90 14.15

G - 2.26 2.39

H 0.00 - 0.30

J 0.20 - 0.50

K 0.63 - 1.03

L 1.95 REF.



Copyright © 2001 120.26084 Rev. 2

PAGE INDEXFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2SUMMARY OF CHANGES TO THIS MANUAL SINCE REVISION 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3BASIC DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ECG Portion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Respiration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Communication Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11ECG ASIC BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13DETAILED DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ECG Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Reference Electrode Drive Circuit and Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reference Electrode Disconnect, Active Drive, or Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Reducing 60 Hz Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Limitations in 60 Hz Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Electrode Offsets Versus Electrode Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ECG Cable Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Lead-Fail Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Lead Fail Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chest-Lead-Present Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22How the Chest-Lead-Present Detector Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pacer Detector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Three Modes of Operation for the Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Pacer Detector Output PDETO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Pacer Pulse Detection Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Pacer Detector Trip Thresholds for Very Narrow Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Miscellaneous Causes for False Pacer Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ECG Self-Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Respiration Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Voltage Reference Input and Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Clock Divider Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Miscellaneous Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Serial Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Serial Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33ECG Mode Control Register (EMD, Read/Write, Address=0): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34ECG Reference Electrode (Driven-Lead) and Lead-Select Control Register (LDR, Read/Write, Ad-

dress=1): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ECG Offset Voltage Control Register (EOS, Read/Write, Address=2): . . . . . . . . . . . . . . . . . . . . . . . . . 36Pacer Detector Mode, Lead-Fail Control Register (PDL, Read-Write, Address=3): . . . . . . . . . . . . . . . 36Lead-Fail Status Register (LFS, Read Only, Address=4): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37ECG Self-Test Control Register (EST, Read/Write, Address=5): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Respiration Circuit and General Purpose Output Register (RSP, Read-Write, Address=6) . . . . . . . . 38

APPLICATIONS INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Respiration Circuit Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Synchronous Demodulator Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Respiration Signal Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Respiration Artifacts from Non-Patient Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44



120.26084 Rev. 2 Copyright © 2001

ECG Cable Design Versus RESP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Fine Tuning RESP’s Synchronous Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

A/D (and Its Input Filter) Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Other Sigma Delta A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48RC Low Pass Input Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Advantages and Disadvantages of the AD7716 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Other A/D Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Independent Channel Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Sleep Mode Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52ASIC Power Connections and Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Considerations Unique To “12-Lead” Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55ECG ESIS Input Filter and Defibrillator Protection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Possible Causes for Processor Resets, Etc. During Defibrillation Discharge . . . . . . . . . . . . . . . . . . . . 56ECG Front End Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Neon Bulbs and ECG Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Neon Bulb Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Component Voltage and Power Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Defibrillator Issues with ECG Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Derived ECG Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Dealing With ECG Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61How To Do Self Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Tests Of The Lead-fail Detection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Tests Of The ECG Channels’ Mode Bits and Ability To Pass Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 65Tests Of The Pacer Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Tests Of The ECG Channels’ Offset Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Tests of the Reference Electrode Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Tests Of The Chest-Lead-Present Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Tests of the Respiration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Indirect Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Miscellaneous Ongoing Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Spacings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76REGULATORY AND SAFETY ISSUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

High-Criticality Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78ASIC Performance Specific To EC13-1992 And EC11-1991 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 80Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

DEVELOPMENT AIDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80PACKAGE MECHANICAL DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81



Copyright © 2001 120.26084 Rev. 2

TABLE INDEXSpecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Serial Interface Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Read/Write Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33ECG Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Inputs/Outputs for “3-Lead”, “5-Lead”, and “12-Lead” Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34ECG Reference Electrode and Lead-Select Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Selection of Reference Electrode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Reference Electrode and Patient Electrodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Reference Electrode Driver Common-Mode Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36ECG Offset Voltage Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Pacer Detector and Lead-Fail Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Pacer Detector Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Lead-Fail Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37ECG Self-Test Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38VTST Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Resp Circuit and General Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Defibrillator Discharge Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Derived ECG Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61“3-lead” Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65“5-lead” Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65“12-lead” Primary Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66“12-lead” Secondary Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Pacer Detector Tests - MUX Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Pacer Detector Tests - Threshold Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Primary ECG Channel Offset Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Secondary ECG Channel Offset Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68High Criticality Failures and Possible Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Requirements for EC13 and EC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

FIGURE INDEXECG ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Write and Read Operation Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10RESP Circuit Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11ECG ASIC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11ECG ASIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Common Mode Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Sample Schematic for “5-Lead” ECG with RESP and Power Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Sample Schematic for “12-Lead” ECG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Offset Control Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Self Test Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81