ece 456 computer architecture lecture #4 – memory (overview) instructor: dr. honggang wang fall...
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ECE 456 Computer Architecture
Lecture #4 – Memory (Overview)
Instructor: Dr. Honggang Wang
Fall 2013
Dr. Wang
Administrative Issues (10/02/13)• Project team set-up
• Project proposal– due Oct. 21, Monday– Proposal guidelines are available from the class website
Group#1 Group#3
Group#2
Dr. Wang
L#2&3 Review Questions (True/False)1. _____ Computer architecture is concerned with the hardware details that are
transparent to the machine language programmer
2. _____ Different models in the same computer family may have different organizations, but share the same architecture
3. _____ In nested interrupt processing method, the interrupt will be disabled before the CPU transfers the control to the interrupt service routine
4. _____ Consider a system with two I/O devices: a printer and a disk with increasing priorities of 2 and 3, respectively. A user program begins at t=0. At t=5, a disk interrupt occurs; at t=13, a printer interrupt occurs. Each interrupt processing time is 10 time units. Then the printer interrupt handling will be completed at t=25 if using Sequential method; and at t=23 if using Nested method.
5. ______ The octal equivalent of hexadecimal number C2A is 1452
6. ______ Typically the data bus width determines the memory capacity of a computer system
Dr. Wang
Review of Lecture #3
• In the last lecture, we covered the …...– Concept of computer function & structure
– Computer basic functions (4 kinds) and program execution
function (instruction cycle)
– 4-level hierarchical computer structure
– Computer interconnection structures
• bus and its design elements
• single and multiple bus structures
Dr. Wang
Agenda
Memory Input/Output
Central Processing
Unit
Interconnection Bus
Computer history (L#1)Computer architecture = von Neumann architecture + interrupts (L#2)
L#4 ~ 8 L#3
Parallel organizations: SMP, Vector/Array Processors
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Topics
• Characteristics of memory systems
• Memory hierarchy
• Error correction in memory
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Key Characteristics of Memory
• Location• Capacity• Transfer unit• Access methods
• Performance• Physical types• Physical characteristics• Organization
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• Location
– internal• registers
• cache
• main memory
– external• peripheral storage devices
• accessible to CPU via I/O controller
• disk, tape
• Capacity
– internal memory• bytes (8 bits)
• words (x bytes)
– external memory• bytes
Memory Key Characteristics (1)
Dr. Wang
Unit of Transfer
• Addressable unit– smallest location that can
be uniquely addressed
– at word / byte level
– N = 2A
• A: length of an address in bits
• N: number of addressable units
• Internal memory– governed by the data bus
width
– a word length or larger
• External memory– a block / record
Memory Key Characteristics (2)
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Accessing Methods (1)
• Sequential access– access is made in a
specific linear sequence
– example: tape
Memory Key Characteristics (3)
• Direct access– individual blocks have a
unique address– access is by jumping to a
vicinity plus sequential searching
– example: disk
– a shared read/write mechanism is used– accessing time depends on location of data & previous location
…......records / blocks
read/write mechanism
A
Dr. Wang
Accessing Methods (2)
• Random access (RA)– individual addressing
mechanism identifies location exactly
– access time is constant, independent of location & previous access
– example: main memory
Memory Key Characteristics (4)
• Associative access– one type of RA
– a word is retrieved based on a portion of its contents
– example: cache
Dr. Wang
Performance
• Access time (latency)– RAM: time to perform a r/w operation; time from the
instant that an address is presented to memory to the instant that data have been stored or made available for use.
– non-RAM: time to position the r/w mechanism at the desired position
• Memory cycle time– access time plus any additional time
• Transfer rate– rate at which data can be moved
Memory Key Characteristics (5)
Dr. Wang
Exercises
1. A microprocessor has a 32-bit data bus and the minimum duration of a bus cycle is 100ns. What is the maximum data transfer rate (in MBytes/second) that this microprocessor can sustain?
2. For a disk memory, the average time to read/write 1K bits is 30 ms, the average access time is 10 ms, what is the data transfer rate (in bps: bit/second) of the disk?
Dr. Wang
• Physical types– paper
• punch card
– semiconductor• main memory
– magnetic• disk, tape
– optical• CD, DVD
– magneto-optical• MO disk• http://en.wikipedia.org/
wiki/Magneto-optical_disc
• Physical characteristics– volatile vs. non-volatile
– erasable vs non-erasable
– non-erasable means non-volatile (ROM)
• Organization– physical arrangement of bits
to form words
Memory Key Characteristics (6)
Dr. Wang
Agenda
Characteristics of memory systems
– location, capacity, transfer unit, access methods,
performance, physical types, physical characteristics,
and organization
• Memory hierarchy
• Error correction in memory
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Memory Hierarchy (1)
• The Bottom Line– How much?
• capacity
– How fast?• keep up with processor
– How expensive?• reasonable in
relationship to other components
• Dilemma– Trade-off
• fast access time, greater cost/bit
• greater capacity, smaller cost/bit, slower access time
– Users always want UNLIMITED amounts of FAST memory with LOW cost
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Solution to the Dilemma
• Memory hierarchy: – is organized into several
levels
– each smaller, faster, and more expensive/bit than the next, lower level
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Example & Goal
• Goal: to provide a memory system with speed almost as fast as the fastest level and cost almost as low as the cheapest level
CPUCACHE
MEMORYI/O
STORAGE DEVICES
Registers
Register reference
Cache reference
Memory reference
Disk memoryreference
500 bytes0.25ns
SizeSpeed
64KB1ns
512MB100ns
100GB5ms
Dr. Wang
How?
• The key to achieve the goal is – the percentage of access to each successively lower level
is substantially less than that of the level above
• Have to take advantage of locality of reference– Programs tend to reuse data and instructions they have
used recently, 2 types:• Temporal locality: recently accessed items are likely to be
accessed in the near future
• Spatial locality: items whose addresses are near one another tend to be referenced close together in time
Dr. Wang
Example• 2-level memory hierarchy
– Level 1: size (S1), cost/bit (C1), access time (T1)
– Level 2: size (S2), cost/bit (C2), access time (T2)
– H (hit ratio): fraction of accesses involving only faster Level 1
– Assumption:• Processor access Level 1 directly
• Ignoring decision making time
– For system: Ts, Cs
How the goal can be achieved?
?
Dr. Wang
Explanations
• To provide a memory system with speed almost as fast as the fastest Level 1, the hit ratio H should be high
T1
T2
T1+T2
Hit ratio: H0 1
Ts = H*T1+(1-H)*(T1+T2) = T1+(1-H)*T2 = T1+T2-H*T2
Ts T1 as H 1
Ts
Ts ?
S1 is big enough
Dr. Wang
Explanations (Cont’d)
• To provide a memory system with cost almost as low as
the cheapest Level 2, S2/S1 should be large
10
100
1000
Relative size S2/S1
1
Cs/C2 1, i.e., Cs C2 as S2/S1 increases
Cs/C2
21
2211
SS
SCSCCs
10 100 1000
C1/C2 = 1000
100
10
Cs ?
S1 is small enough
Dr. Wang
Explanations (Cont’d)
• S1 should be big enough to assure the needed hit ratio, and thus Ts T1
• S1 should be small enough to hold down system cost/bit, i.e., Cs C2
S1?
Dr. Wang
• Depend on the degree of locality– Spatial: tendency of execution to
involve memory locations that are clustered
– Temporal: tendency for a processor to access memory locations that have been used recently
• S1=S2 H=1: all items in M2 are always stored also in higher level M1
• No locality: references are completely random
• Strong locality: it’s possible to achieve high H even with relatively small upper-level memory size
0.2
0
H
0.5 1.0
Moderatelocality
No locality
Relative size S1/S2
1.0
0.4
0.6
0.8 Stronglocality
Dr. Wang
Administrative Issues (10/07/13, Monday)
•Project proposal (File name: Group#_proposal.doc/docx)– due Oct. 21, Monday– Proposal guidelines are available from the class website
Dr. Wang
Agenda
Characteristics of memory systems
– location, capacity, transfer unit, access methods,
performance, physical types, physical characteristics,
and organization
Memory hierarchy
– dilemma, goal: why ? (locality), how?
• Error correction in memory
Dr. Wang
Review Questions (10 extra points)• Consider a memory system containing a cache and a
main memory. The cache contains 32Kbytes and has an access time of 30ns. The average cost per bit of the cache memory is $10-4. The main memory contains 512Mbytes and has an access time of 0.1s. The average cost per bit of the main memory is $10-5. If a referenced word is in the cache (cache hit), then the CPU can access it directly. If it is in the main memory but not in the cache, the word is first transferred to cache and then accessed by the CPU.
– What is the average cost per bit for the entire memory system?
– If the average access time to the memory system is 20% greater
than the cache access time, what is the cache hit ratio?
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Error Correction
• Memory is subject to errors
– Hard failure
• permanent physical defect
– Soft error
• random, non-destructive
• no permanent damage to memory
• Memory has error detecting & correcting logic
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Error Correction Logic
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Basic Concepts (1)• Code: a means of representing information using a well-
defined set of rules
• Code word: a collection of symbols used to represent a particular piece of information based on a specific code
• Binary code: a code in which all symbols forming each code word are either 0 or 1
• Error detecting code: a code which is capable of detecting errors
• Error correcting code: a code which is capable of correcting errors
Barry W Johnson, Design and Analysis of Fault-Tolerant Digital systems, Addison-Wesley 1989
Dr. Wang
Basic Concepts (2)
• Hamming Distance (HD): the HD between two binary words is the number of bit positions in which the two words differ
– A=(an-1 an-2 … a1 a0 ), B=(bn-1 bn-2 … b1 b0 ),
– Modulo-2 addition : 0+0=0, 0+1=1+0=1, 1+1=0
– |A|=weight of A=number of 1s in A
– HD(A,B)=|A+B|
• HD between 10110100 and 01001010?
HD = |10110100+01001010 | = |11111110| = 7
Barry W Johnson, Design and Analysis of Fault-Tolerant Digital systems, Addison-Wesley 1989
Dr. Wang
Basic Concepts (3)
• Code Distance (CD): the CD for a given code is the minimum HD between any two valid code words– Error detection capability: a code can detect up to d bits
errors iff the CD >= d+1
– Error correction capability: a code can correct up to c bits errors iff the CD >= 2c+1
– Error detection & correction: a code can correct up to c bits errors and detect an additional d bits errors iff the CD >= 2c+d+1
Barry W Johnson, Design and Analysis of Fault-Tolerant Digital systems, Addison-Wesley 1989
Dr. Wang
Basic Concepts (4)Separability
• Separable codes: a code is separable if the code words are formed by appending a collection of check bits to the original information bits
• Non-separable codes: a code is non-separable if the code words are not partitioned directly into information bits and check bits.
Barry W Johnson, Design and Analysis of Fault-Tolerant Digital systems, Addison-Wesley 1989
Dr. Wang
Example Codes
• Parity codes– Single-Bit Parity Codes
– Multiple-Bit Parity Codes: Hamming Single Error Correcting (SEC) codes
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Parity Codes
• The addition of some extra bits to a binary data word such that the resulting code word has either an even number of 1s (even parity) or odd number of 1s (odd parity)
• Single-bit parity and multiple-bit parity
Dr. Wang
Single-Bit Parity Codes (1)
• Odd Parity: the total number of 1s in the code word is odd– 0010
• Even Parity: the total number of 1s in the code word is even– 0010
0010 0
0010 1
Dr. Wang
Single-Bit Parity Codes (2)
• CD = 2 detect single-bit error– Theorem: a code can detect up to d bits errors iff the
CD >= d+1
– Any single-bit error introduced into a code word results in the erroneous word being an invalid code word if a code has a distance of 2
• Detects all errors which involve an odd number of bits
Dr. Wang
Single-Bit Parity Codes (3)
• Even parity generation circuit for 4-bit data
XOR
XOR
XOR
d0
d1
d2
d3
Generated Parity Bit
How about the odd parity generation circuit?
Dr. Wang
Single-Bit Parity Codes (4)
• Example use of single-bit parity codes in a memory of a computer system
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Multiple-Bit Parity Codes• The original information is partitioned into two or more
groups with one parity bit being assigned to each group
• Each bit may appear in more than one parity group – overlapping parity
• Example: Hamming Single Error-Correcting (SEC) Code
Dr. Wang
Venn Diagram Illustration of Hamming Single-Error Correction (SEC) Code
• The use of hamming code on 4-bit data word
• Assign 4 data bits to 4 inner compartments, parity bits to 3 left compartments
• Use even parity for each group (circle)
• Any single bit error can be easily detected by checking the discrepancies in parity bits
1
1
1 0
PA PB
PC
A
C
B
Dr. Wang
KMK 12
SEC Codes (2): How many check bits?
• Example:– M=8, K=?
The comparator receives 2 K-bit values as inputs and generates the K-bit syndrome word by performing a bit-by-bit comparison
The value 0 of the syndrome word indicates no error, leaving 2K-1 values to indicate an error occurring on any of M data bits or K check bits
38123
48124 K=4
Dr. Wang
SEC Codes (4): How to generate check bits?
• Number all bit positions from 1 to (M+K)
• Arrangement of bit positions– Check bits: bit positions whose position numbers are power of 2– Data bits: other positions
Bit pos. 12 11 10 9 8 7 6 5 4 3 2 1
Pos. # 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Data bit D8 D7 D6 D5 D4 D3 D2 D1
Check bit X X X X
Dr. Wang
SEC Codes (4): How to generate check bits?
• Check-bit generating rule:– Each check bit is generated by performing exclusive-or
operation on every data bit whose position number contains a 1 in the same bit as the position number of that check bit
87658
84324
764312
754211
DDDDC
DDDDC
DDDDDC
DDDDDC
Dr. Wang
SEC Codes (5): Error Detection
• No error detected if syndrome contains all 0s
• An error has occurred in check bits if syndrome contains one and only one bit set to 1; no correction needed.
• An error has occurred in data bits if syndrome contains more than one bit set to 1; the numerical value indicates the position of the data bit in error. The data bit is inverted for correction.
Checkbits dRegenerate Checkbits Original WordSyndrome
Dr. Wang
Exercises
• Develop the SEC code for a 6-bit data word D6D5D4D3D2D1=011001
• Assume an error occurs on D4: 10, what happens?
• Assume an error occurs on a check bit, what happens?
Dr. Wang
Summary of Lecture #4
• Characteristics of memory systems
– location, capacity, transfer unit, access methods, performance,
physical types, physical characteristics, and organization
• Memory hierarchy
– dilemma, goal: why ? (locality), how?
• Error correction in memory
– error types, definitions & concepts, parity codes, SEC
Dr. Wang
Schedule for Memory Lectures
CPUCACHE
MAINMEMORY
I/O STORAGE DEVICES
Registers
Internal Memory
ExternalMemory
plus Virtual Memory
Defer to CPU discussion
Dr. Wang
Things To Do
•Project proposal – Due Oct. 21, Monday– Proposal guidelines are available from the class
website
•Check out the class website about– lecture notes– reading assignments