ECE 456 Computer Architecture

Lecture #16 – Exam#2 Review

Instructor: Dr. Honggang Wang

Fall 2013

Dr. Wang

Administrative Issues(Monday, Nov. 20)

• Exam #2 – Monday, Nov. 25

• Project– final report due Dec. 4 (Wed.)

– presentation due Dec. 9 (Mon.)

– Refer to course website about the guidelines (format, page limit, requirements) for report and presentation.

• Today’s topic– Exam #2 Review Session

Dr. Wang

Exam#2

• Time: Monday, November 25, 2:00 ~ 3:15pm• Place: Group II – 212

• Requirements: – Arrive on time! – Random seat will be assigned. – Open-book open-notes in-class exam– No sharing notes during the exam– Individual work

Dr. Wang

Prepare for Exam #2

• Review lecture notes #5,6,7,9,11• Review all the review questions and hands-on

problems discussed in the class

• Ask questions if there are

Dr. Wang

Questions?

• Dr. Wang (Instructor)– Email:   hwang1@umassd.edu – Office:  II-209B (II-214A, temporary office)

Dr. Wang

Review of Lecture #5,6,7,9, 11

I. Overview of Computer Systems (Exam#1)

II. The Memory System (L#5, 6, 7, Exam#2)

III. The I/O System (L#9, Exam#2)

IV. The CPU (L#115, Exam#2)

Dr. Wang 7

Part II Review (Cont’d: L#5)

• Various semiconductor memory types

– Read-write (RAM): static RAM vs. dynamic RAM;

– Read-only: ROM, PROM

– Read-mostly: EPROM, EEPROM, flash memory

• Semiconductor memory organization

– one-bit-per-chip, one-word-per-chip

Dr. Wang 8

Part II Review (Cont’d, L#6)

• Cache memory is the solution to deal with performance imbalance between processor and main memory

• Basic idea and basis of cache memory

• Cache design issues such as– mapping functions: direct, associative, & set associative – cache size, replacement algorithms (4), write policy (2),

cache line size, unified and split caches, single-level and multilevel caches

Dr. Wang 9

Part II Review (Cont’d: L#7)• For knowledge:

– Magnetic surface memory (disk & tape)

– Optical external memory

• Redundant Array of Independent Disks (RAID)– RAID 0 ~ RAID 0

• Total average access time for disks:

Ta= Ts+ Tr+ Tt – Ts: seek time, time to move the disk arm/head to required track– Tr=1/(2r): average rotational delay, time to wait for data to rotate

under head– Tt=b/(rN): time to transfer (read/write) b bytes of data

Dr. Wang

Part III: I/O System

Dr. Wang

Part III Review (Cont’d, L#9)

• Functions and structure of I/O modules

• Parallel & serial external I/O interface between peripheral and I/O module

• Virtual I/O– a file consists of a sequence of bytes or records written to an

I/O device

– file storage allocation: continuous, linked-list, linked-list allocation using an index

– free list & bit map methods to keep track of available blocks

– directory management

Dr. Wang

Review of Lecture #9

I. Overview of Computer Systems (Exam#1)

II. The Memory System (L#5,6,7, Exam#2)

III. The I/O System (L#9, Exam#2)

IV. The CPU (L#11, Exam#2)• CPU registers (L#11)

• Number representation in ALU (L#11)

Dr. Wang

Part IV Review – CPU Registers (L#11)

• CPU organization

• Register organization

– User-visible registers

– Control & status registers

– Examples: MC68000, Intel 8086, 80386 +

Dr. Wang

Part IV Review – ALU (L#11)• Integer representation:

– sign-magnitude

– 2’s complement

• Floating point representation:

– Express the number in binary form

– Normalize the number

– Find the biased exponent

– Sign bit of the significand

– IEEE 754

Dr. Wang

A Computer System (L1)

Memory Input/Output

Central Processing

Unit

Interconnection Bus

Computer architecture = von Neumann architecture + interrupts (L2)

L4 ~ L8 L3 L9, L10

L11 & more (after Exam2)

Good Luck!