ec 2404 esd lab manual

RAJALAKSHMI INSTITUTE OF TECHNOLOGYKuthambakkam - Chennai

ANNA UNIVERSITY2008 REGULATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG.

EC 2404 - ELECTRONICS SYSTEM DESIGNLAB

(IV Year B.E VII Semester 2008 Batch)

Manual prepared by

Ms.A.Valarmathi M.E.,Lecturer,ECE Department.

EC2404 Electronics System Design Lab Manual Dept. Of ECE

SYLLABUS

EC2404 ELECTRONICS SYSTEM DESIGN LAB L T P C0 0 3 2

1. Design of a 4-20mA transmitter for a bridge type transducer.Design the Instrumentation amplifier with the bridge type transducer (Thermistor or any resistance variation transducers) and convert the amplified voltage from the instrumentation amplifier to 4 – 20 mA current using op-amp. Plot the variation of the temperature Vs output current.

2. Design of AC/DC voltage regulator using SCRDesign a phase controlled voltage regulator using full wave rectifier and SCR, vary the conduction angle and plot the output voltage.

3. Design of process control timerDesign a sequential timer to switch on & off at least 3 relays in a particular sequence using timer IC.

4. Design of AM / FM modulator / demodulatori. Design AM signal using multiplier IC for the given carrier frequency and modulation index and demodulate the AM signal using envelope detector.ii. Design FM signal using VCO IC NE566 for the given carrier frequency and demodulate the same using PLL NE 565.

5. Design of Wireless data modem.Design a FSK modulator using 555/XR 2206 and convert it to sine wave using filter and transmit the same using IR LED and demodulate the same PLL NE 565/XR 2212.

6. PCB layout design using CADDrawing the schematic of simple electronic circuit and design of PCB layout using CAD

7. Microcontroller based systems designDesign of microcontroller based system for simple applications like security systems combination lock.

8. DSP based system designDesign a DSP based system for echo cancellation, using TMS/ADSP DSP kit.

9. Psuedo-random Sequence Generator10. Arithmetic Logic Unit Design

Note: Kits should not be used. Instead each experiment may be given as mini project.

TOTAL: 45 PERIODS

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CONTENTS

S.No. List of Experiments Page No

1Design of a 4-20mA transmitter for a bridge type transducer

5

2 Design of AC/DC voltage regulator using SCR 9

3 Design of process control timer 13

4 Design of AM modulator and demodulator 17

5 Design of FM modulator and demodulator 21

6 Design of Wireless data modem 25

7 PCB layout design using CAD 31

8 Microcontroller based systems design 37

9 DSP based system design 41

10 Pseudo-random Sequence Generator 47

11 Arithmetic Logic Unit Design 51

12 Simulation of DC Voltage Regulator using SCR 55

13 Simulation of AC Voltage Controller using SCR 59

14 Simulation of Arithmetic Logic Unit Design 63

15 Simulation of Pseudo-random Sequence Generator 67

16 Viva Questions 71

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CIRCUIT DIAGRAM:

4


DESIGN OF A 4-20MA TRANSMITTER FOR A BRIDGE TYPE TRANSDUCER

EXPT NO: 1

AIM:

To design the instrumentation amplifier with the bridge type transducer and to plot the various temperature corresponding to output current.

COMPONENTS REQUIRED:

S.No. Component Range Quantity1 LM 35 - 12 IC 741 - 33 RPS (0-30)V 14 Resistor 1KΩ 105 Bread Board - 16 Connecting wires - As

required

THEORY:

In a number of industrial and consumer applications physical quantities such as temperature, pressure, light intensity are to be measures and controlled. These physical quantities are measured with the help of transducers has to be amplified so that it can drive the display system. This function is performed by an instrumentation amplifier

The important features of instrumentation amplifier are:1. High Gain Accuracy 2. High CMRR3. High Gain Stability With Low Temperature Coefficient 4. Low Dc Output5. High Output Impedance

PROCEDURE:

1. Connections are given as per the circuit diagram.

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2. The voltage from the bridge type transducer part is amplified by the instrumentation amplifier.

3. The amplified output voltage is noted for different temperature values.4. A graph is plotted between the temperature and the amplified voltage.

MODEL GRAPH :

TABULATION:

VS

(V)TEMP = (100oC * VS) oC

VL

(V)RL = VL / IL

KΩ

6


7


RESULT:

Thus the instrumentation amplifier with the bridge type transducer was designed and the graph is plotted.

CIRCUIT DIAGRAM:

8


DESIGN OF AC/DC VOLTAGE REGULATOR USING SCR

EXPT NO: 2

AIM:

To design a phase controlled voltage regulator using full wave rectifier and SCR and to plot the output voltage by varying conduction angle.


S.No. Component Range Quantity1 Transformer (9-0-9)V 12 Resistor 1KΩ

100KΩ1KΩ POT

521

3 SCR 294N 24 Multimeter 15 CRO 16 Bread Board - 17 Probes &

Connecting wiresAs required

THEORY:

In AC voltage regulator power transform can be done in two ways: On-off control and Phase angle control. In On-off control, the thyristor switches connect the load to the AC source for a few cycle of input voltage. In phase angle control, the thyristor switches connect the load to AC source for the position of each cycle of input voltage.

DC voltage regulator can be implemented by connecting the load in the DC sides. The same fixing circuit designed for AC voltage regulator can be used for DC voltage regulator also. During positive half cycle, the diode current flows through second diode

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loading SCR. During negative half cycle, the DC load current flow through the first diode thus loads SCR.

MODEL GRAPH:

TABULATION:

10


PROCEDURE:

1. Connections are given as per the circuit diagram.2. Note the output voltage VO reading form CRO and plot the VO and time along

Y and X axis.3. The conduction angle is varied and the graph is plotted.

11


RESULT:

Thus the AC/DC voltage regulator was designed using SCR and the graph is plotted.

CIRCUIT DIAGRAM :

Vcc =13 to 14V

RelayVc

12

2.2K

R2

C1

100uf

R11k

C L 100

CL 100


DESIGN OF PROCESS CONTROL TIMER

EXPT NO: 3

AIM:

To design a process control timer using relay.


S.No. Component Range Quantity1 Transistor CL100 22 Relay - 13 Diode IN4001 14 LED - 15 Capacitor 100 F 16 Resistor 1K

2.2 K11

7 Regulated Power supply

(0-30)V 1

8 Bread Board - 19 Connecting wires - As

required

DESIGN:

VC = VCC (1-e-t/RC ) ----------------(1)Where R = 4.7 K. C = 100 F

Let the operation voltage be Vopr . At t = T, voltage across the capacitor is equal to the sum of the relays operating voltage and the two diode drops of Darlington pair.

The calculation of T is given as followsVC = VCC

C1 = e-t/RC

From equation (1) at t = 0, VC = 0 and at t = , VC = VCC

VO = VCC (1-e-t/RC ) , VCC = 13V

13


= 13(1-e-t/RC )R = 4.7 K. C = 100 F

7.97 = 13 (1-e-t/(4.7K*100F) ant t=6sec.Which is the theoretical value of time period for switching from one device to

another.

14


THEORY:

The analog timer circuit shown in the diagram consists of darlington pair and relay circuit connected with proper biasing. The relay circuit is designed to operate at operating voltage Vopr which is given by

Vopr = VCC (1-e-t/RC ) + 2 diode dropsWhere VCC – supply voltage

t – time periodR and C are the values of biasing resistor and capacitor. Also VC = VCC (1-e-t/RC )When the supply voltage VCC (ranging from 13 to 14V) is given to the circuit,

device A is turned ON. The current flowing through the circuit charges the biasing capacitor upto a voltage equal to sum of relay operating voltage and the two diode drop of this voltage is reached. Once this relay lead the switch positions the time taken by the analog timer to switch from one device to another is calculated, whose theoretical value is 6 sec.

PROCEDURE:

1. Connections are given as per the circuit diagram.2. Now supply voltage of 13V is given and time taken by the relay to switch

from one device A to device B (i.e) time taken to switch ON the LED is noted.

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RESULT:

Thus the analog timer was designed using relay.Theoritical value of time taken = -----------Practical value of time taken = -----------

CIRCUIT DIAGRAM:

MODULATOR CIRCUIT:

DEMODULATOR CIRCUIT:

16


DESIGN OF AMPLITUDE MODULATION AND DEMODULATION

EXPT NO: 4

AIM:

To design an AM signal using AM multiplier IC for the given carrier frequency and to demodulate the AM signal using envelope detector.


S.No. Component Range Quantity1 Capacitor 1µF

0.01µF11

2 Resistor 1KΩ5.28KΩ

21

3 Inductor 250mH 14 Diode IN 4007 15 Function

Generator- 1

6 Bread Board - 17 CRO - 18 Probes &

Connecting wires- As

required

17


MODEL GRAPH:

TABULATION:

SIGNAL AMPLITUDE (V) TIME PERIOD (S)

Message

Carrier

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AM modulated

Demodulated

PROCEDURE:

1. Connections are given as per the circuit diagram.2. Sinusoidal wave is given from AFO as input.3. Frequency of carrier signal is varied according to the value.4. Output of AM signal is obtained in CRO.5. The output of the modulated circuit is given as the input to the demodulated

circuit.6. The demodulated signal is obtained in CRO.

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RESULT:

Thus the message signal was modulated and demodulated by amplitude modulation technique using continuous signal as carrier and the graph was plotted.

CIRCUIT DIAGRAM:

MODULATOR CIRCUIT:

DEMODULATOR CIRCUIT:

20


DESIGN OF FREQUENCY MODULATION AND DEMODULATION

EXPT NO: 5

AIM:

To design a FM signal using IC 555 for the given carrier frequency and to demodulate the same using PLL NE 565.


S.No. Component Range Quantity1 Capacitor 1µF

0.01µF10µF

111

2 Resistor 10KΩ2.7KΩ4.7 KΩ

111

3 IC 555565

11

4 Function Generator

- 1

5 Bread Board - 16 CRO - 17 RPS (0-30)V 18 Probes &


required

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MODEL GRAPH:

TABULATION:

SIGNAL AMPLITUDE (V) TIME PERIOD (ms)

Message

Carrier

22


FM modulated

Demodulated

PROCEDURE:

1. Connections are given as per the circuit diagram.2. Set the carrier signal and message signal at pin 5.3. Output of FM signal is obtained at the pin 3 of IC 555.4. The output of the modulated circuit is given as the input to the demodulated

circuit.5. The demodulated signal is obtained at the pin 7 of IC 565.

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RESULT:

Thus the message signal was modulated and demodulated by frequency modulation technique using continuous signal as carrier and the graph was plotted.

CIRCUIT DIAGRAM:

TRANSMITTER CIRCUIT:

24


DESIGN OF WIRELESS DATA MODEM

EXPT NO: 6

AIM:

To design a FSK modulator using timer IC555 and convert it to sine wave using filter and transmit the same using IR LED and demodulated the same using PLL NE 565..


S.No. Component Range Quantity1 Capacitor 0.1µF

0.01µF0.05µF

171

2 Resistor 500Ω47KΩ10 KΩ600 Ω50 KΩ

12421

3 IC 555565741

111

4 RPS (0-30)V 15 Function

Generator- 1

6 Bread Board - 17 CRO - 18 Bread Board - 19 Probes &


required

25


RECEIVER CIRCUIT:

26


PROCEDURE:

1. Connections are given as per the circuit diagram.2. The input is given to the base of the transistor.3. The output is taken at pin3 of IC 555 timer according to the input.4. The IR receives the data and pass it to the FSK decoder. 5. The free running frequency is varied and the lock range and capture range is

noted while 4 and 5 are shorted and output is taken from pin 6 of them.6. The output is taken from pin 6 of the comparator whose input are IC565

output and RC ladder output.

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MODEL GRAPH:

TABULATION:

28


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RESULT:

Thus the circuit for wireless data modem is designed and output was verified. CIRCUIT DIAGRAM:

Vin

30


PCB LAYOUT DESIGN USING CAD

EXPT NO: 7

AIM:

To design a printed circuit board layout for a given circuit using ARCAD.


1. Personal computer.2. PCB layout software such as ARCAD.

THEORY:

General rules for designing PCBs:

The PCB designer follows few rules of thumb that can be used when laying out PCBs. Here they are,

1. PLACING COMPONENTS:

Generally, it is best to place parts only on the topside of the board. Firstly place all the components in specific locations. This includes connectors, switches, LED mounting holes, heat sinks or any other item that mounts to an external location.

Give careful thought when placing components to minimize trace lengths. Doing a good job here will make laying the traces much easier.

Arrange ICs in only one or two orientations (up and down or right and left). Align each IC so that pin 1 is in the same place for each orientation, usually on the top or left sides. Position polarized parts with the positive leads, all having the same orientation. Also use a square pad to mark the positive leads of these components.

Frequently, the beginners run out of room when routing traces. Leave 0.35 to 0.5 between ICs. For large ICs allow even more space.

Parts not found in the component library can be made by placing a series of individual pads and then group them together. Place one pad for each lead of the

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component. It is very important to measure the pin spacing and pin diameters as accurately as possible.

After placing all the components, print out a copy of the layout. Place each component on the top of the layout. Check to insure that you have allowed enough space for every part to rest without touching each other.

2. PLACING POWER AND GROUND TRACES:

After the components are placed, the next step is to lay the power and ground traces. A power rail is run along the front edge of the board and a ground rail along the

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rear edge. From these rails attach traces that run in between the ICs. The ground rail should be very wide, 0.100” and all the supply lines should be 0.50”. When using this configuration the remaining of the bottom layer is then reserved for the vertical signal traces.

3. PLACING SIGNAL TRACES:

When placing traces, it is always a good practice to make them as short and direct as possible. Use vias to move signals from one layer to the other. A via is a pad-through hole. Generally the best strategy is to lay out a board with vertical trace on one side and horizontal traces on the opposite side. A good trace width for low current digital and analog signals is 0.010”.

Traces that carry significant current should be wider than signal traces. The table below gives rough guidelines of how wide should a trace be for a given amount of current.

When routing traces, it is best to have the snap to grid turned on. Setting the snap grid spacing to 0.050” works well. Changing to a value of 0.025” can be helpful when trying to work as densely as possible. Turning off the snap feature may be necessary when connecting to parts that have unusual pin spacing.

It is a commo0n practice to restrict the direction that traces run to horizontal, vertical or at 45 degrees angles.

When placing narrow traces, use 0.015” or less. Avoid sharp right angle turns. The problem here is that , in the board manufacturing process the outside corner can be etched a little more narrow. The solution is to use two 45-degree bends with a short leg in between.

0.010” 0.3 Amps0.015” 0.4 Amps0.020” 0.7 Amps0.025” 1 Amps0.050” 2 Amps0.100” 4 Amps-0.150” 6 Amps

33


It is a good idea to place text on the top layer of the board, such as the product or company name.

4. CHECKING YOUR WORK:

After all the traces are placed, it is best to double-check the routing of every signal to verify that nothing is missing or incorrectly wired. Do this by running through the schematic, one wire at a time. Carefully follow the path of each trace. After each trace is confirmed, mark the signal on the schematic with a yellow highlighter.

34


Inspect the layout, both top and bottom to ensure that the gap between every item is 0.007” or greater. Use the pad information tool to determine the diameters of pads that make up a component.

Check for missing vias. The CAD software will automatically insert a via when changing layers as a series of traces are placed. The user often forget that vias are not automatically inserted otherwise. For example, when beginning a new trace, a via is to first print a top layer , then print the bottom. Visually inspect each side for traces that doesn’t connect to anything. When a missing via is found, insert one. Do this by clicking on the pad in the side tool bar from the down list box and click on the layout.

Check for the traces that cross each other. Inspecting a printout of each layer easily does this.

Metal components such as heat sinks, crystals, switches, batteries and connectors can cause shorts, if they are placed over traces on the top layer. Inspect for these shorts by placing all the metal components on a printout of the top layer. Then look for traces that run below the metal components.

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RESULT:

Thus the PCB layout for the given circuit was designed using ARCAD software.

PROGRAM:

Address Opcode Label Mnemonics Operand Comments

4100 90 41 1F START MOV DPTR # TABLE

Load the start address of switching scheme data TABLE into Data pointer.

4103 78 04 MOV R0, #04 Load the count in R04105 F0 LOOP MOV X A, @ DPTR Load the number in

TABLE into A4106 C0 83 PUSH DPH Push DPTR Value to

stack4108 C0 82 PUSH DPL410A 90 FF C0 MOV DPTR, #

0FFFC0Load the motor port address into DPTR.

410D F0 MOV X @ DPTR, A Send the value in A to stepper motor port address

410F 7C FF MOV R4,#0FFH Delay loop to cause a specific amount of time delay before next data item is sent to the motor

4110 7D FF DELAY MOV R5,#0FFH4112 DD FE DELAY1 DNZ R4, DELAY

1

4114 DC FA DJNZ R4,DELAY4116 D0 82 POP DPL POP back DPTR

value from stack4118 D0 83 POP DPH411A A3 INC DPTR Increment DPTR to

point to next item in the TABLE

411B D8 E8 DJNZ R0, LOOP Decrement R0, if not zero repeat the loop

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411D 80 E1 SJMP START Short jump to start of the program to make the motor rotate continuosly.

411F 09 05 06 0AH

TABLE DB 09 05 06 0AH

Value as per two phase switching scheme.

MICROCONTROLLER BASED SYSTEM DESIGN

EXPT NO: 8

AIM: To interface a stepper motor with 8051 micro controller and control the speed and

direction of the rotation.


S.No. Component Quantity1 8051 Micro

Controller Kit1

2 Stepper motor 13 Interface card 14 Connecting cables few

THEORY:

A motor in which the rotor is able to assume only discrete stationary angular position is a stepper motor. They are used in printer, disk drive process control machine tools etc.

Two-phase stepper motor has two pairs of stator poles. Stepper motor windings A1, A2, B1, B2 are cyclically excited with a DC current to run the motor in clockwise direction and reverse phase sequence A1, B2, A2, B1 in anticlockwise stepping

Two-phase switching scheme:In this scheme, any two adjacent stator windings are energized.

Anticlockwise ClockwiseStep A1 A2 B1 B2 Data Step A1 A2 B1 B2 Data1 1 0 0 1 9 H 1 1 0 1 0 A H2 0 1 0 1 5 H 2 0 1 1 0 6 H3 0 1 1 0 6 H 3 0 1 0 1 5 H4 1 0 1 0 A H 4 1 0 0 1 9 H

37


Address Decoding logic:

The 74138 chip is used for generating the address decoding logic to generate the device select pulses CS1 and CS2 for selecting the IC 74175 in which latches the data bus to stepper motor driving circuitry.

38


PROCEDURE:

1. Enter the above program starting from location 4100.2. Execute the same, stepper motor rotates.3. Varying the count at R4 and R5 can vary the speed.4. Entering the data in the look-up TABLE in the reverse order can vary the

direction of rotation.

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RESULT:

Thus the stepper motor is interfaced with 8051 micro controller and the speed and direction of the rotation is controlled.

FLOWCHART

40

START

Store the counter value in memory

Store Vmax and Vmin in register ay0 &ay1

Set Vmax to DAC port

Apply delay

Send Vmin to DAC port

Read keyboard port

Press any arrow key

If keyboard is UP arrow 0x0076

B

Increase Vmax by 1

A


DSP BASED DIGITAL FUNCTION GENERATOR

EXPT NO: 9

AIM:

To stimulate a simple pulse generator using ADSP2181 DSP processor

APPARATUS REQUIRED:

1. ADSP2181 unit2. ADSP 2181 Universal 3. CRO4. IBM PC keyboard

THEORY:

ADSP 2181 is highly advanced DSP processor, which works of on chip serial port. It is capable of processing 16-bit arithmetic operation, with ALU and Accumulator. This ADSP2181 is suitable for developing applications like adaptive filtering, FET & external precision arithmetic etc.,In this experiment a simple pulse generator is stimulated using ADSP2181.

In order to develop this application IBM PC keyboard is connected to ADSP2181through the IO port of oxo2

The IBM PC keyboard up arrow is used to increase the amplitude of the pulse wave, down arrow is used to decrease the amplitude, left arrow is used to decrease the frequency and right arrow is used to increase the frequency.

PROBLEM STATEMENT:

1. USING ADSP2181 generate the square wave and measure the amplitude of the square wave and frequency

2. Identify scan codes for the up arrow , down arrow, right and left arrow by reading the IO port through which IBM PC keyboard is connected to the IO port of ADSP2181

41


3. Find the suitable logic and wrote a program to increase and decrease the amplitude of square wave using CRO

Yes

42

B

If keyboard is down arrow 0x0072

Decrease Vmax by 1

Decrease memory location value

Increase memory location value

If keyboard is right arrow 0x0074

If keyboard is left arrow 0x006B

A

A

A

A


SAMPLE PROGRAM:

.module /ram main _routine;start:

ay0 =0xfff; [max peak voltage]beg:

cntr =0xfff; [delay counter]do int until ce;axo =0x0000;

int: io(0x14) =ay0;[send max peak to DAC]ax1=io(0x102);[read keyboard port]dm(0x103) =ax1; [store the scan cade for the pressed key]ay1 = 0x0ff; [max upper bytes]ar=ax1 and ay1;ax1=ar;ay1=0x0075;[scan code for up arrow key]ar=ax1-ay1 ; [do camparision]dm(0x105)=ar;if ne jump beg;[if not equal repeat the same square wave]ay =ay0+1;[if equal increase the max peak voltage repeat the square wave]ay0=ar;dm(0x106)=ay0;jump beg;idle;.end mod;

EXERCISE:

In the given program pulse generator is stimulated only using up arrow key so the students instructed to stimulate the same using down arrow , left arrow & right arrow kkeys by identifying the key codes

PROGRAM:.module /ram main_routine;

start:

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ay0 =0xfff;[max peak voltage]ax1 =0xff;dm(0x107)=ax1;

beg: cntr =dm(0x107);[delay counter] do int until ce;

ax0=0x0000;int: io(0x14) =ax0 ; [send minimum peak to DAC]

cntr =dm(0x107);do ict until ce;

ict: io(0x14)=ay0;[send maximum peak to DAC]ax1=io(0x102); [read keyboard port]

TABULATION COLUMN:

AMPLITUDE( V)

TIME PERIOD(MS)

SQUARE WAVE

T ON T OFF

MODEL GRAPH :

VVOLTS

T msec

44


dm(ox103)=ax1;[store scan code for pressed key]ay1=ox0ff;ar=ax1 and ay1;ax1 =ar;ay1=0x0075;[scan code for up arrow key]ar=ax1 –ay1;[do comparision]dm(0x105)=ar;if ne jump aaa;[if not equal check for another key]ar=ay0+1;[ increase amplitude]ay0=ar;dm(0x106)=ay0;jump beg;

aaa:ay1=0x0072;[scan code for down arrow key]ar=ax1-ay1;[do comparision]dm(0x108)=ar;if ne jump bbb;[if not equal check for another key]ar=ay0-1;[ decrease amplitude]ay0=ar;dm(0x106)=ay0;jump beg;

bbb: ay1=0x0072;[scan code for right arrow key]ar=ax1-ay1;[do comparision]dm(0x109)=ar;if ne jump ccc;[if not equal check for another key]ax1=dm(0x107)ar=ax1+5;[ decrease frequency]dm(0x107)=ar;jump beg;

ccc: ay1=0x0074;[scan code for left arrow key]ar=ax1-ay1;[do comparision]dm(0x110)=ar;if ne jump beg;[if not equal check for another key]ax1=dm(0x107)ar=ax1-5;[ increase frequency]

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dm(0x107)=ar;jump beg;

idle;.end mod;

RESULT:

Thus the square wave is generated using ADSP2181 DSP.

LOGIC DIAGRAM:

46


PSEUDO RANDOM SEQUENCE GENERATOR

47


EXPT NO: 10

AIM:

To design the Pseudo random sequence generator using logic gates.


S.No. Component Quantity1 IC 7474 42 IC 7486 23 Connecting wires Few4 Digital Logic

Trainer kit1

THEORY:

A shift register is an n-bit register with provision for shifting its stored data by one position at each clock pulse. The logical configuration of a shift register consists of a chain of flip-flops connected in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive a common clock pulse which causes the shift from one stage to the next.

Most shift registers have provision for shifting only in one direction, but some have a control input that allows either left or right shifting to be specified at each clock. One way to load n bits of data into the flip-flop chain is to load the data one bit each clock cycle using the serial input. Some shift registers also have parallel inputs that can be used to load all n bits in one clock cycle. The output of a shift register can be observed one bit at a time at the serial output, but some shift registers also have parallel outputs for observing all n bits at once.

Shift registers are classified according to three basic considerations: their method of data handling (serial-in serial-out, serial-in parallel-out, and parallel-in serial-out), their direction of data movement (shift right, shift left, and bidirectional), and their bit length. One of the important applications of shift register circuits is in serial computation. Compared to parallel computation, where all bits in a word are processed at the same cycle, serial computation process words in one bit per cycle. Therefore, serial computation is slower, but it has the advantage of requiring less hardware and wiring. The binary sequence generator can be designed using the shift register.

48


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This binary sequence generator will display a random output (repeats every 2n–1 bits, where n is the number of flip-flops used in the shift register). The IC 7486 provides the exclusive-OR needed in the circuit. To start the sequence generator, set the initial state of the shift register to 0001 by setting the switch to logic 1. Then change to logic 0 as this will release the control input.

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Give logical inputs as per the respective truth table.

3. Observe the logical output.

RESULT:

Thus the pseudo random sequence generator was designed using logic gates.

LOGIC DIAGRAM:

50


ARITHMETIC LOGIC UNIT DESIGN

51


EXPT NO: 11

AIM:

To design the Arithmetic Logic Unit using logic gates.


S.No. Component Quantity1 IC 7432 12 IC 7408 23 IC 7486 24 8:1 MUX 25 Connecting wires Few6 Digital Logic

Trainer kit1

THEORY:

The arithmetic logic unit (ALU) is a digital circuit that calculates arithmetic operations (addition, subtraction, etc.) and logic operations (Exclusive OR, AND, OR etc.) between two numbers. The ALU is a fundamental building block of the central processing unit of a computer.

Many types of electronic circuits need to perform some type of arithmetic operation, so even the circuit inside a digital watch will have a tiny ALU that keeps adding 1 to the current time and keeps checking if it should beep timer etc.

ALU units typically need to be able to perform the basic logical operations (AND, OR) including the addition operation. The inclusion of inverters on the inputs enables the same ALU hardware to perform the subtraction operation (adding an inverted operand) and the operations NAND and NOR. A basic ALU design involves a collection of “ALU Slices”, which each can perform the specified operation on a single bit. There is one ALU slice for every bit in the operand.

The basic 2 bit ALU is designed using logic gates. The AND, OR, EX-OR gates are used to perform the various operation such as OR, AND, XOR and addition. The 8:1 Multiplexers are used to select between the various operations: OR, AND, XOR and addition. All the operations are performed in parallel and the select signal (OP) is used to determine which result to pass on to the rest of the data path. The carry signal is only used for addition, is generated and passed out of the ALU for every operation.TRUTH TABLE:

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SELECTION INPUT OUTPUTOP0 OP1 OP2 OUT0 OUT1

0 0 0 A0 XOR B0 A1 XOR B1

0 0 1 A0 AND B0 A1 AND B1

0 1 0 A0 OR B0 A1 OR B1

0 1 1 A0 + B0 A1 + B1

PROCEDURE:

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3. Observe the logical output and verify with their truth table

RESULT:

Thus the 2 bit Arithmetic Logic Unit was designed using logic gates.

CIRCUIT DIAGRAM:

54


SIMULATION OF DC VOLTAGE REGULATOR USING SCR

55


EXPT NO: 12

AIM:

To study the operation of DC voltage regulator with R load and observe the waveform using MATLAB 6.5 software.

APPARATUS REQUIRED:

MATLAB 6.5 software

THEORY:

Rectification is a process of converting an AC to DC. The fully controlled converter uses thyristors as the rectifying elements and the Dc output as function of amplitude of the Ac supply voltage and the point at which the thyristors are triggered. During the positive half cycle of the input voltage SCR 1, SCR 2, are forward biased and are simultaneously triggered at the firing angle . The supply voltage appears across the load resistance R. The load voltage is 0 from to +, until the SCR 3 and SCR 4 is triggered in negative half cycle. The load current now flows from the supply, SCR 3, Load and SCR 4.thus the direction of current through the load is the same in both half cycles. The output voltage is given by the expression.

V0 = Vm / (1+cos) volts

PROCEDURE:

1. Open the SIMULINK library from MATLAB 6.5.2. Select the components from the blockset.3. Give the wiring connection as per the circuit diagram.4. Simulate the circuit and observe the waveform.

WIRING DIAGRAM:

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MODEL GRAPH :

Vo

Time period

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RESULT:

Thus the operation of fully controlled converter with R load has been studied and the waveforms are observed.

CIRCUIT DIAGRAM:

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T1

230V 50 T2

Hz, 1 R Load AC Supply

SIMULATION OF AC VOLTAGE CONTROLLER USING SCR

EXPT NO: 13

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AIM:

To study the operation of single phase AC voltage regulator with R load and observe the waveform using MATLAB 6.5 software.

APPARATUS REQUIRED:

MATLAB 6.5 software

THEORY:

AC voltage controllers are thyristor-based devices, which convert the fixed alternating voltage directly to variable alternating voltage without a change in the frequency. The single phase AC voltage controller uses two thyristors connected in anti parallel. The thyristors T1 and T2 are forward biased during the positive and negative half cycles respectively. During the positive half cycle, T1 is triggered at firing angle. T1 starts conducting and the voltage source is applied to the load from to (+). During the negative half cycle T2 is triggered at (+), hence it conducts from (+) to 2.

PROCEDURE:

1. Open the SIMULINK library from MATLAB 6.5.2. Select the components from the blockset.3. Give the wiring connection as per the circuit diagram.4. Simulate the circuit and observe the waveform.

MODEL GRAPH:

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V0

(V)

time

WIRING DIAGRAM:

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RESULT:

Thus the operation of single phase AC voltage controller with R load has been studied and the waveforms are observed

FLOW CHART:

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ARITHMETIC LOGIC UNIT DESIGN

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EXPT NO: 14

AIM:

To design an Arithmetic and Logic Unit using Xilinx tool and model sim simulator software.


1. PC2. Xilinx Tool Kit3. Model sim software

THEORY:

The arithmetic logic unit (ALU) is a digital circuit that calculates arithmetic operations (addition, subtraction, etc.) and logic operations (Exclusive OR, AND, OR etc.) between two numbers. The ALU is a fundamental building block of the central processing unit of a computer.

Many types of electronic circuits need to perform some type of arithmetic operation, so even the circuit inside a digital watch will have a tiny ALU that keeps adding 1 to the current time and keeps checking if it should beep timer etc.

ALU units typically need to be able to perform the basic logical operations (AND, OR) including the addition operation. The inclusion of inverters on the inputs enables the same ALU hardware to perform the subtraction operation (adding an inverted operand) and the operations NAND and NOR. A basic ALU design involves a collection of “ALU Slices”, which each can perform the specified operation on a single bit. There is one ALU slice for every bit in the operand.

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PROGRAM:

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;

entity ALU is

port( A: in std_logic_vector(1 downto 0);B: in std_logic_vector(1 downto 0);SEL: in std_logic_vector(1 downto 0);R: out std_logic_vector(1 downto 0);

);end ALU;

architecture behv of ALU isbegin

process(A,B,SEL)begin

case SEL iswhen “00” =>

R <= A + B;when “01” =>

R <= A + (not B) + 1;when “10” =>

R <= A and B;when “11” =>

R <= A or+ B;when others =>

R <= “XX”;end case;

end process;

end behv;

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PROCEDURE:

1. Open the Xilinx tool and model sim simulator software.

2. Create a VHDL program and write the entity and the architecture of ALU and

save the file with extension “.vhd”.

3. In the program the output is result (R) and the inputs are A,B and selection input

is SEL.

4. Inside the architecture write the expression of ALU for addition, subtraction,

AND operation and OR operation. These operations are selected by the selection

input.

5. Simulate program using model sim software and then download into a Xilinx

processor and verify the output with different combination of inputs.

RESULT:

Thus the Arithmetic Logic Unit was designed and the output is verified by using simulation.PROGRAM:

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;to use these pseudo-random number sequence generators, memory must be set aside to hold the last random number, which is used to generate the ;next one so that a randomly distributed (but predictable) sequence of ;number is generated.

.equ rand8reg, 0x20 ;one byte

.equ rand16reg, 0x21 ;two bytes

;generates an 8 bit pseudo-random number which is returned in Acc.;one byte of memory must be available for rand8reg

rand8: mov a, rand8regjnz rand8bcpl amov rand8reg, a

rand8b: anl a, #10111000bmov c, pmov a, rand8regrlc amov rand8reg, aret

;generates a 16 bit pseudo-random number which is returned in Acc (lsb) & B (msb);two bytes of memory must be available for rand16reg

rand16: mov a, rand16regjnz rand16bmov a, rand16reg+1jnz rand16bcpl amov rand16reg, amov rand16reg+1, a

rand16b:anl a, #11010000bmov c, pmov a, rand16regjnb acc.3, rand16ccpl c

rand16c:rlc amov rand16reg, amov b, amov a, rand16reg+1rlc amov rand16reg+1, axch a, b

ret

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PSEUDO RANDOM SEQUENCE GENERATOR USING 8051 MICROCONTROLLER

EXPT NO: 15

AIM:

To design the Pseudo random sequence generator using 8051 Microcontroller.


S.No. Component Quantity1 8051 Microcontroller Compiler 12 PC 1

THEORY:

A shift register is an n-bit register with provision for shifting its stored data by one position at each clock pulse. The logical configuration of a shift register consists of a chain of flip-flops connected in cascade, with the output of one flip-flop connected to the input of the next flip-flop. All flip-flops receive a common clock pulse which causes the shift from one stage to the next.

Most shift registers have provision for shifting only in one direction, but some have a control input that allows either left or right shifting to be specified at each clock. One way to load n bits of data into the flip-flop chain is to load the data one bit each clock cycle using the serial input. Some shift registers also have parallel inputs that can be used to load all n bits in one clock cycle. The output of a shift register can be observed one bit at a time at the serial output, but some shift registers also have parallel outputs for observing all n bits at once.

Shift registers are classified according to three basic considerations: their method of data handling (serial-in serial-out, serial-in parallel-out, and parallel-in serial-out), their direction of data movement (shift right, shift left, and bidirectional), and their bit length. One of the important applications of shift register circuits is in serial computation. Compared to parallel computation, where all bits in a word are processed at the same cycle, serial computation process words in one bit per cycle. Therefore, serial computation is slower, but it has the advantage of requiring less hardware and wiring. The binary sequence generator can be designed using the shift register.

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This binary sequence generator will display a random output (repeats every 2n–1 bits, where n is the number of flip-flops used in the shift register). The IC 7486 provides the exclusive-OR needed in the circuit. To start the sequence generator, set the initial state of the shift register to 0001 by setting the switch to logic 1. Then change to logic 0 as this will release the control input.

PROCEDURE:



3. Observe the logical output.

RESULT:

Thus the pseudo random sequence generator was designed using 8051 Microcontroller.

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VIVA QUESTIONS

1. Define buck boost converter.2. Explain the application of using buck boost converter.3. Explain the different modes of buck boost converter4. Define Flyback converter.5. Explain the application of using Flyback converter.6. Explain the different modes of Flyback converter 7. What is AM transceiver.8. What is FM transceiver.9. Applications of AM transceiver.10.Applications of FM transceiver.11.What is the purpose of using data modem.12.Give application of wireless modem.13.Mention the protocols used in data transfer.14.What is PCB?15.List the materials used for manufacturing PCB16.Define Voltage regulator.17.Explain the operating condition in SCR.18.Differentiate between microcontroller and microprocessor.19.State advantage in using microcontroller while designing any system.20.Define Timer.21.Define Various modes of operation of timer.22.How a timer enhances for controlling any process.23.Define Amplifier.24.What is the purpose of using an instrumentation amplifier.25.Define digital function generator?26.What is DSP?27.Define voltage controller?28.State the difference between AC and DC voltage.29.Define signal sampling30.Define Nyquist criteria.

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ec 2404 esd lab manual

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