dual, wideband, voltage-feedback operational amplifier with

0.1 Fm

IN

+5V

10pF

0.1 Fm

10pF

499W

499W

Clock

IN

REFT

REFB

ADS825

10-Bit

40MSPS

1/2OPA2690

+5V

+2.5V

+2.5V

+2.5V

1/2OPA2690

VIN

1kW

1kW

499W

499W

35W

35W

2kW100W

100pF

2kW

2.5VCM

2VPP

HARMONIC DISTORTION vs FREQUENCY

FOR THE SINGLE-SUPPLY ADC DRIVER

Harm

onic

Dis

tort

ion (

dB

c)

Frequency (MHz)

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-1001 10 20

3rd-Harmonic

2nd-Harmonic

2V Differential OutputPP

OPA2690

www.ti.com SBOS238G –JUNE 2002–REVISED MARCH 2010

Dual, Wideband, Voltage-FeedbackOPERATIONAL AMPLIFIER with Disable

Check for Samples: OPA2690

1FEATURES DESCRIPTION2• FLEXIBLE SUPPLY RANGE: The OPA2690 represents a major step forward in

+5V to +12V Single Supply unity-gain stable, voltage-feedback op amps. A new±2.5V to ±6V Dual Supply internal architecture provides slew rate and full-power

bandwidth previously found only in wideband,• WIDEBAND +5V OPERATION: 220MHz (G = 2)current-feedback op amps. A new output stage

• HIGH OUTPUT CURRENT: 190mA architecture delivers high currents with a minimal• OUTPUT VOLTAGE SWING: ±4.0V headroom requirement. These give exceptional

single-supply operation. Using a single +5V supply,• HIGH SLEW RATE: 1800V/msthe OPA2690 can deliver a 1V to 4V output swing• LOW SUPPLY CURRENT: 5.5mA/ch with over 120mA drive current and 150MHz

• LOW DISABLE CURRENT: 100mA/ch bandwidth. This combination of features makes theOPA2690 an ideal RGB line driver or single-supply

APPLICATIONS Analog-to-Digital Converter (ADC) input driver.• VIDEO LINE DRIVING The low 5.5mA/ch supply current of the OPA2690 is• xDSL LINE DRIVER/RECEIVER precisely trimmed at +25°C. This trim, along with low

temperature drift, provides lower maximum supply• HIGH-SPEED IMAGING CHANNELScurrent than competing products. System power may• ADC BUFFERSbe reduced further using the optional disable control• PORTABLE INSTRUMENTS pin. Leaving this disable pin open, or holding it HIGH,

• TRANSIMPEDANCE AMPLIFIERS will operate the OPA2690I-14D normally. If pulled• ACTIVE FILTERS LOW, the OPA2690I-14D supply current drops to less

than 200mA/ch while the output goes to aSingle-Supply Differential ADC Driver high-impedance state.

OPA2690 RELATED PRODUCTSSINGLES DUALS TRIPLES

Voltage-Feedback OPA690 OPA2690 OPA3690

Current-Feedback OPA691 OPA2691 OPA3691

Fixed Gain OPA692 — OPA3692

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2002–2010, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

http://focus.ti.com/docs/prod/folders/print/opa2690.html

https://commerce.ti.com/stores/servlet/SCSAMPLogon?storeId=10001&langId=-1&catalogId=10001&reLogonURL=SCSAMPLogon&URL=SCSAMPSBDResultDisplay&GPN1=opa2690









1

2

3

4

8

7

6

5

+VS

Out B

-In B

+In B

Out A

-In A

+In A

-VS

A

B

1

2

3

4

5

6

7

14

13

12

11

10

9

8

-In A

+In A

DIS A

-VS

DIS B

+In B

-In B

Out A

NC

NC

+VS

NC

NC

Out B

OPA2690

SBOS238G –JUNE 2002–REVISED MARCH 2010 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

OPA2690ID Rails, 100OPA2690 SO-8 D –40°C to +85°C OPA2690

OPA2690IDR Tape and Reel, 2500

OPA2690I-14D Rails, 58OPA2690 SO-14 D –40°C to +85°C OPA2690

OPA2690I-14DR Tape and Reel, 2500

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or seethe TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range, unless otherwise noted.OPA2690 UNIT

Power Supply ±6.5 VDC

Internal Power Dissipation See Thermal Analysis section

Differential Input Voltage ±1.2 V

Input Voltage Range ±VS V

Storage Temperature Range: D –65 to +125 °C

Junction Temperature (TJ) +150 °C

Human Body Model (HBM) 2000 V

ESD Ratings Charge Device Model (CDM) 1500 V

Machine Model (MM) 200 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.

D PACKAGE D PACKAGESO-8 SO-14

(TOP VIEW) (TOP VIEW)

2 Copyright © 2002–2010, Texas Instruments Incorporated

Product Folder Link(s): OPA2690


http://www.ti.com


OPA2690


ELECTRICAL CHARACTERISTICS: VS = ±5VBoldface limits are tested at +25°C.At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 36 for ac performance only), unless otherwise noted.

OPA2690ID, I-14D

MIN/MAX OVERTYP TEMPERATURE

0°C to -40°C to MIN/ TESTPARAMETER TEST CONDITIONS +25°C +25°C(2) +70°C(3) +85°C(3) UNIT MAX LEVELS (1)

AC PERFORMANCE (see Figure 36)

Small-Signal Bandwidth G = +1, VO = 0.5VPP, RF = 25Ω 500 MHz typ C

G = +2, VO = 0.5VPP 220 165 160 150 MHz min B

G = +10, VO = 0.5VPP 30 20 19 18 MHz min B

Gain Bandwidth Product G ≥ 10 300 200 190 180 MHz min B

Bandwidth for 0.1dB Gain Flatness G = +2, VO < 0.5VPP 30 MHz typ C

Peaking at a Gain of +1 VO < 0.5VPP 4 dB typ C

Large-Signal Bandwidth G = +2, VO < 5VPP 200 MHz typ C

Slew Rate G = +2, 4V Step 1800 1400 1200 900 V/ms min B

Rise-and-Fall Time G = +2, VO = 0.5V Step 1.4 ns typ C

G = +2, VO = 5V Step 2.8 ns typ C

Settling Time to 0.02% G = +2, VO = 5V Step 12 ns typ C


Harmonic Distortion G = +2, f = 5MHz, VO = 2VPP

xx x 2nd-Harmonic RL = 100Ω –68 –64 –62 –60 dBc max B

RL ≥ 500Ω –77 –70 –68 –66 dBc max B

xx x 3rd-Harmonic RL = 100Ω –70 –68 –66 –64 dBc max B

RL ≥ 500Ω –81 –78 –76 –75 dBc max B

Input Voltage Noise f > 1MHz 5.5 nV/√Hz typ C

Input Current Noise f > 1MHz 3.1 pA/√Hz typ C

Differential Gain G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.06 % typ C

Differential Phase G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.03 deg typ C

Channel-to-Channel Crosstalk f = 5MHz, Input-Referred –85 dBc typ C

DC PERFORMANCE (4)

Open-Loop Voltage Gain (AOL) VO = 0V, RL = 100Ω 69 58 56 54 dB min A

Input Offset Voltage VCM = 0V ±1.0 ±4.5 ±5.0 ±5.2 mV max A

xxx Average Offset Voltage Drift VCM = 0V ±12 ±12 mV/°C max B

Input Bias Current VCM = 0V +5 ±11 ±12 ±13 mA max A

xxx Average Bias Current Drift (magnitude) VCM = 0V ±20 ±40 nA/°C max B

Input Offset Current VCM = 0V ±0.1 ±1.0 ±1.4 ±1.6 mA max A

xxx Average Offset Current Drift VCM = 0V ±1.0 ±1.5 nA/°C max B

INPUT

Common-Mode Input Range (CMIR) (5) ±3.5 ±3.4 ±3.3 ±3.2 V min A

Common-Mode Rejection Ratio (CMRR) VCM = ±1V 65 60 57 56 dB min A

Input Impedance

xxx Differential Mode VCM = 0V 190 || 0.6 kΩ || pF typ C

xxx Common-Mode VCM = 0V 3.2 || 0.9 MΩ || pF typ C

(1) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value only for information.

(2) Junction temperature = ambient for +25°C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over

temperature specifications.(4) Current is considered positive out of node. VCM is the input common-mode voltage.(5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.

Copyright © 2002–2010, Texas Instruments Incorporated 3




OPA2690


ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)Boldface limits are tested at +25°C.At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 36 for ac performance only), unless otherwise noted.

OPA2690ID, I-14D



OUTPUT

Voltage Output Swing No Load ±4.0 ±3.8 ±3.7 ±3.6 V min A

100Ω Load ±3.9 ±3.7 ±3.6 ±3.3 V min A

Current Output, Sourcing VO = 0V +190 +160 +140 +100 mA min A

Current Output, Sinking VO = 0V –190 –160 –140 –100 mA min A

Short-Circuit Current VO = 0V ±250 mA typ C

Closed-Loop Output Impedance G = +2, f = 100kHz 0.04 Ω typ C

DISABLE (SO-14 Only) Disabled LOW

Power-Down Supply Current (+VS) VDIS = 0V, Both Channels –200 –400 –480 –520 mA max A

Disable Time VIN = 1VDC 200 ns typ C

Enable Time VIN = 1VDC 25 ns typ C

Off Isolation G = +2, RL = 150Ω, VIN = 0V 70 dB typ C

Output Capacitance in Disable G = +2, RL = 150Ω, VIN = 0V 4 pF typ C

Turn-On Glitch ±50 mV typ C

Turn-Off Glitch ±20 mV typ C

Enable Voltage 3.3 3.5 3.6 3.7 V min A

Disable Voltage 1.8 1.7 1.6 1.5 V max A

Control Pin Input BIas Current (VDIS) VDIS = 0V, Each Channel 75 130 150 160 mA max A

POWER SUPPLY

Specified Operating Voltage ±5 V typ C

Maximum Operating Voltage Range ±6.0 ±6.0 ±6.0 V max A

Maximum Quiescent Current (2 Channels) VS = ±5V 11 11.6 12.4 13.2 mA max A

Minimum Quiescent Current (2 Channels) VS = ±5V 11 10.6 9.2 8.6 mA min A

Power-Supply Rejection Ratio (+PSRR) Input-Referred 75 68 66 64 dB min A

THERMAL CHARACTERISTICS

Specified Operating Range: D –40 to +85 °C typ C

Thermal Resistance, qJA Junction-to-Ambient

xx x D xxx SO-8 125 °C/W typ C






OPA2690


ELECTRICAL CHARACTERISTICS: VS = +5VBoldface limits are tested at +25°C.At RF = 402Ω, RL = 100Ω to VS/2, and G = +2 (see Figure 37 for ac performance only), unless otherwise noted.

OPA2690ID, I-14D



AC PERFORMANCE (see Figure 37)

Small-Signal Bandwidth G = +1, VO = 0.5VPP, RF = ±25Ω 400 MHz typ C

G = +2, VO < 0.5VPP 190 150 145 140 MHz min B

G = +10, VO < 0.5VPP 25 18 17 16 MHz min B

Gain Bandwidth Product G ≥ 10 250 180 170 160 MHz min B

Bandwidth for 0.1dB Gain Flatness G = +2, VO < 0.5VPP 20 MHz typ C

Peaking at a Gain of +1 VO < 0.5VPP 5 dB typ C

Large-Signal Bandwidth G = +2, VO = 2VPP 220 MHz typ C

Slew Rate G = +2, 2V Step 1000 700 670 550 V/ms min B

Rise-and-Fall Time G = +2, VO = 0.5V Step 1.6 ns typ C

G = +2, VO = 2V Step 2.0 ns typ C



Harmonic Distortion G = +2, f = 5MHz, VO = 2VPP

xx x 2nd-Harmonic RL = 100Ω to VS/2 –65 –60 –59 –56 dBc max B

RL ≥ 500Ω to VS/2 –75 –70 –68 –66 dBc max B

xx x 3rd-Harmonic RL = 100Ω to VS/2 –68 –64 –62 –60 dBc max B

RL ≥ 500Ω to VS/2 –77 –73 –71 –70 dBc max B

Input Voltage Noise f > 1MHz 5.6 nV/√Hz typ C

Input Current Noise f > 1MHz 3.2 pA/√Hz typ C

G = +2, NTSC, VO = 1.4VP, RL = 150Ω toDifferential Gain 0.06 % typ C

VS/2

G = +2, NTSC, VO = 1.4VP, RL = 150Ω toDifferential Phase 0.02 deg typ C

VS/2

DC PERFORMANCE (4)

Open-Loop Voltage Gain (AOL) VO = 2.5V, RL = 100Ω to VS/2 63 56 54 52 dB min A

Input Offset Voltage VCM = 2.5V ±1.0 ±4.5 ±4.8 ±5.2 mV max A

xxx Average Offset Voltage Drift VCM = 2.5V ±10 ±10 mV/°C max B

Input Bias Current VCM = 2.5V +5 ±11 ±12 ±13 mA max A

xxx Average Bias Current Drift (magnitude) VCM = 2.5V ±20 ±40 nA/°C max B

Input Offset Current VCM = 2.5V ±0.3 ±1.0 ±1.4 ±1.6 mA max A

xxx Average Offset Current Drift VCM = 2.5V ±7 ±9 nA/°C max B

INPUT

Least Positive Input Voltage (5) 1.5 1.6 1.7 1.8 V max A

Most Positive Input Voltage(5) 3.5 3.4 3.3 3.2 V min A

Common-Mode Rejection Ratio (CMRR) VCM = 2.5V ± 0.5V 63 58 56 54 dB min A

Input Impedance

xxx Differential Mode VCM = 2.5V 92 || 1.4 kΩ || pF typ C

xxx Common-Mode VCM = 2.5V 2.2 || 1.5 MΩ || pF typ C

(1) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization andsimulation. (C) Typical value only for information.

(2) Junction temperature = ambient for +25°C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over

temperature specifications.(4) Current is considered positive out of node. VCM is the input common-mode voltage.(5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.





OPA2690


ELECTRICAL CHARACTERISTICS: VS = +5V (continued)Boldface limits are tested at +25°C.At RF = 402Ω, RL = 100Ω to VS/2, and G = +2 (see Figure 37 for ac performance only), unless otherwise noted.

OPA2690ID, I-14D



OUTPUT

Most Positive Output Voltage No Load 4 3.8 3.6 3.5 V min A

RL = 100Ω to 2.5V 3.9 3.7 3.5 3.4 V min A

Least Positive Output Voltage No Load 1 1.2 1.4 1.5 V max A

RL = 100Ω to 2.5V 1.1 1.3 1.5 1.7 V max A

Current Output, Sourcing +160 +120 +100 +80 mA min A

Current Output, Sinking –160 –120 –100 –80 mA min A

Short-Circuit Current ±250 mA typ C

Closed-Loop Output Impedance G = +2, f = 100kHz 0.04 Ω typ C

DISABLE (SO-14 only) Disabled LOW

Power-Down Supply Current (+VS) VDIS = 0V, Both Channels –200 –400 –480 –520 mA max A

Off Isolation G = +2, 5MHz 65 dB typ C

Output Capacitance in Disable 4 pF typ C

Turn-On Glitch G = +2, RL = 150Ω, VIN = VS/2 ±50 mV typ C

Turn-Off Glitch G = +2, RL = 150Ω, VIN = VS/2 ±20 mV typ C

Enable Voltage 3.3 3.5 3.6 3.7 V min A

Disable Voltage 1.8 1.7 1.6 1.5 V max A

Control Pin Input BIas Current (VDIS) VDIS = 0V, Each Channel 75 130 150 160 mA typ B

POWER SUPPLY

Specified Single-Supply Operating Voltage 5 V typ C

Maximum Single-Supply Operating Voltage 12 12 12 V max B

Maximum Quiescent Current (2 Channels) VS = +5V 9.8 10.88 11.44 12.1 mA max A

Minimum Quiescent Current (2 Channels) VS = +5V 9.8 8.96 8.0 7.72 mA min A

Power-Supply Rejection Ratio (+PSRR) Input-Referred 72 dB typ C

THERMAL CHARACTERISTICS

Specification: D –40 to +85 °C typ C

Thermal Resistance, qJA Junction-to-Ambient







100.5 1 100 500

Frequency (MHz)

Gain

(3dB

/div

)

9

6

3

0

-3

-6

V = 4VO PP

V = 7VO PP

V = 2VO PP

V = 1VO PP

Norm

aliz

ed G

ain

(dB

)

Frequency (MHz)

0.7 10 100 700

6

3

0

-3

-6

-9

-12

-15

V = 0.5VO PP G = +1

R = 25WF

G = 2G = 5

G = 10

1

Time (5ns/div)

400

300

200

100

0

-100

-200

-300

-400

G = +2

V = 0.5VO PP

Outp

ut V

oltage (

mV

)

Time (5ns/div)

Outp

ut V

oltage (

V)

4

3

2

1

0

-1

-2

-3

-4

G = +2

V = 5VO PP

dG

/dP

(%

/degre

e)

Number of 150 LoadsW

1 2 3 4

0.200

0.175

0.150

0.125

0.100

0.075

0.050

0.025

0

dG

dG

dP

dP

No Pull- Down

With 1.3k Pull-DownW1/2

OPA2690

402W

-5V

+5V

75W

Video In

402W

Optional1.3kWPull- Down

Cro

ssta

lk (

5dB

/div

)

Frequency (MHz)

1 10 100

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100Input Referred

OPA2690


TYPICAL CHARACTERISTICS: VS = ±5VAt TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.

SMALL−SIGNAL LARGE−SIGNALFREQUENCY RESPONSE FREQUENCY RESPONSE

Figure 1. Figure 2.

SMALL-SIGNAL LARGE-SIGNALPULSE RESPONSE PULSE RESPONSE

Figure 3. Figure 4.

COMPOSITE VIDEO CHANNEL-TO-CHANNELdG/dP CROSSTALK

Figure 5. Figure 6.





Harm

onic

Dis

tort

ion (

dB

c)

Load Resistance (W)

100 1000

-60

-65

-70

-75

-80

-85

-90

V = 2VO PP

f = 5MHz

3rd-Harmonic

2nd-Harmonic

Harm

onic

Dis

tort

ion (

dB

c)

Supply Voltage (±VS)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-60

-65

-70

-75

-80

3rd-Harmonic

2nd-Harmonic

V = 2VO PP

R = 100WL

f = 5MHz

Harm

onic

Dis

tort

ion (

dB

c)

Frequency (MHz)

0.1 1 10 20

-40

-50

-60

-70

-80

-90

-100

V = 2VO PP

R = 100WL

2nd-Harmonic

3rd-Harmonic

Harm

onic

Dis

tort

ion (

dB

c)

Output Voltage Swing (V )PP

0.1 1 5

-60

-65

-70

-75

-80

R WL = 100

f = 5MHz

3rd-Harmonic

2nd-Harmonic

Harm

onic

Dis

tort

ion (

dB

c)

Noninverting Gain (V/V)

1 10 20

-40

-50

-60

-70

-80

-90

3rd-Harmonic

2nd-Harmonic

V = 2VO PP

R = 100WL

f = 5MHz

Harm

onic

Dis

tort

ion (

dB

c)

Inverting Gain (V/V)

1 10 20

-40

-50

-60

-70

-80

3rd-Harmonic

2nd-Harmonic

VO PP= 2V

RL = 100W

f = 5MHz

RF = 1kW

OPA2690


TYPICAL CHARACTERISTICS: VS = ±5V (continued)

At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.

HARMONIC DISTORTION 5MHz HARMONIC DISTORTIONvs LOAD RESISTANCE vs SUPPLY VOLTAGE

Figure 7. Figure 8.

HARMONIC DISTORTION HARMONIC DISTORTIONvs FREQUENCY vs OUTPUT VOLTAGE

Figure 9. Figure 10.

HARMONIC DISTORTION HARMONIC DISTORTIONvs NONINVERTING GAIN vs INVERTING GAIN






Curr

ent N

ois

e (

pA

/)

ÖH

z

Voltage N

ois

e (

nV

/)

ÖH

z

Frequency (Hz)

100 1M100k10k1k 10M

100

10

1

Voltage Noise 5.5nV/ÖHz

Current Noise 3.1pA/ÖHz

3rd

-Ord

er

Spurious L

evel (d

Bc)

Single-Tone Load Power (dBm)

-8 -6 -4 -2 0 2 4 6 8 10

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

20MHz

10MHz

50MHz

Load Power at Matched 50 Load,W

see Figure 36

R(

)W

S

Capacitive Load (pF)

10 100 1000

80

70

60

50

40

30

20

10

0

Gain

-to-C

apacitiv

e L

oad (

dB

)

Frequency (20MHz/div)

0 100 120 140 160 18020 40 60 80 200

9

6

3

0

-3

-6

-9

402W

1kW

402W

RS

CL

VIN

VOUT

1/2

OPA2690

1k is optional.W

C = 22pFL

C = 47pFL

C = 100pFL

C = 10pFLG = +2

Time (50ns/div)

Outp

ut V

oltage (

0.4

V/d

iv)

2.0

1.6

1.2

0.8

0.4

0

V(2

V/d

iv)

DIS

6

4

2

0

G = +2

V = +1VIN

VDIS

Output Voltage

Each Channel

SO-14

Package

Only

Frequency (Hz)

Feedth

rough (

5dB

/div

)

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100Forward

Reverse

VDIS = 0

100k 1M 10M 100M

OPA2690




INPUT VOLTAGE AND CURRENT TWO−TONE, 3RD−ORDERNOISE DENSITY INTERMODULATION SPURIOUS


RECOMMENDED RS FREQUENCY RESPONSEvs CAPACITIVE LOAD vs CAPACITIVE LOAD


LARGE-SIGNAL DISABLE FEEDTHROUGHENABLE/DISABLE RESPONSE vs FREQUENCY






Inp

ut

Off

se

t V

olta

ge

(m

V)

Inp

ut

Bia

s a

nd

Off

se

t C

urr

en

ts (

A)

m

Ambient Temperature ( C)°

-50 -25 0 25 50 75 100 125

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

20

10

0

-10

-20

Input Offset Current (I )OS

Input Offset Voltage (V )OS

Input Bias Current (I )B

V(V

)O

I (mA)O

-300 -200 -100 0 100 200 300

5

4

3

2

1

0

-1

-2

-3

-4

-5

Output Current Limited1W InternalPower Limit

One ChannelOnly

1W InternalPower LimitOutput Current Limit

100 Load LineW

50 Load LineW

25WLoad Line

Pow

er-

Supply

Reje

ction R

atio (

dB

)

Com

mon-M

ode R

eje

ction R

atio (

dB

)

Frequency (MHz)

10k 1M100k 10M 100M

100

90

80

70

60

50

40

30

20

10

0

CMRR

+PSRR

-PSRR

Supply

Curr

ent (2

mA

/div

)

Outp

ut C

urr

ent (5

0m

A/d

iv)

Ambient Temperature ( C)°

-50 -25 0 25 50 75 100 125

14

12

10

8

6

4

250

200

150

100

50

0

Sourcing Output Current

Sinking Output Current

Quiescent Supply Current

Outp

ut Im

pedance (

)W

Frequency (Hz)

10k 1M100k 10M 100M

10

1

0.1

0.01

1/2OPA2690

402W

+5V

-5V

200W

402W

ZO

Open-L

oop G

ain

(dB

)

Frequency (Hz)

1k 1M100k10k 10M 1G100M

70

60

50

40

30

20

10

0

-10

-20

Open-L

oop P

hase (

)°

0

-30

-60

-90

-120

-150

-180

-210

-240

-270

Open-Loop Gain

Open-Loop Phase

OPA2690




OUTPUT VOLTAGE TYPICAL DC DRIFTAND CURRENT LIMITATIONS OVER TEMPERATURE


COMMON−MODE REJECTION RATIO AND SUPPLY AND OUTPUT CURRENTSPOWER−SUPPLY REJECTION RATIO vs FREQUENCY vs TEMPERATURE


CLOSED-LOOP OUTPUT IMPEDANCE OPEN−LOOPvs FREQUENCY GAIN AND PHASE






5

4

3

2

1

0

1

2

3

4

5

-

-

-

-

-

Input V

oltage (

V)

10

8

6

4

2

0

2

4

6

8

10

-

-

-

-

-

Time (10ns/div)

Outp

ut V

oltage (

V)

Input Voltage

Output Voltage

OPA2690



At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted.NONINVERTING

OVERDRIVE RECOVERY

Figure 25.





Norm

aliz

ed G

ain

(dB

)

Frequency (Hz)

0.7 1 10 700100

6

3

0

-3

-6

-9

G = +1

R = 25WF

G = +2

G = +5

G = +10

V = 0.5VO PP

Gain

(dB

)

Frequency (MHz)

0.5 1 10 500100

9

6

3

0

-3

-6

V = 2VO PP

V = 3VO PP

V = 1VO PP

Time (5ns/div)

Outp

ut V

oltage (

mV

)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

G = +2

V = 0.5VO PP

Time (5ns/div)

Outp

ut V

oltage (

mV

)

4.1

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

G = +2

V = 2VO PP

R(

W)

S


1 10 100 1000

50

45

40

35

30

25

20

15

10

5

0

Gain

-to-C

apacitiv

e L

oad (

dB

)

Frequency (20MHz/div)

0 100 120 140 160 18020 40 60 80 200

9

6

3

0

-3

-6

-9

C = 22pFL

C = 47pFL

C = 100pFL

C = 10pFL

402W

58W 714W

0.1 Fm 714W

714W

402W

RS

CL

VIN

+5V

VOUT

+5V

1/2

OPA2690

OPA2690


TYPICAL CHARACTERISTICS: +5VAt TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 37 for ac performance only), unless otherwise noted.

SMALL−SIGNAL LARGE−SIGNALFREQUENCY RESPONSE FREQUENCY RESPONSE


SMALL-SIGNAL LARGE-SIGNALPULSE RESPONSE PULSE RESPONSE


RECOMMENDED RS FREQUENCY RESPONSEvs CAPACITIVE LOAD vs CAPACITIVE LOAD






Harm

onic

Dis

tort

ion (

dB

c)

Resistance ( )W

100 1000

-60

-65

-70

-75

-80

3rd-Harmonic

V = 2VO PP

f = 5MHz

2nd-Harmonic

Harm

onic

Dis

tort

ion (

dB

c)

Frequency (MHz)

0.1 1 10 20

-40

-50

-60

-70

-80

-90

-100

V = 2VO PP

R = 100W to 2.5VL

2nd-Harmonic

3rd-Harmonic

Harm

onic

Dis

tort

ion (

dB

c)

Output Voltage Swing (V )PP

0.1 1 3

-60

-65

-70

-75

-80

3rd-Harmonic

2nd-Harmonic

R = 100W to 2.5VL

f = 5MHz

3rd

-Ord

er

Spurious L

evel (d

Bc)

Single-Tone Load Power (dBm)

-14 -12 -10 -8 -6 -4 -2 0 2

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

20MHz

10MHz

50MHz

Load Power at Matched 50 Load, see Figure 37W

OPA2690


TYPICAL CHARACTERISTICS: +5V (continued)


HARMONIC DISTORTION HARMONIC DISTORTIONvs LOAD RESISTANCE vs FREQUENCY


HARMONIC DISTORTION TWO-TONE, 3RD-ORDERvs OUTPUT VOLTAGE INTERMODULATION SPURIOUS






1/2OPA2690

+5V

+

DIS

-5V

50 LoadW

50W

175W

50W

50 SourceW

402W

402W

+6.8 Fm

0.1 Fm 6.8 Fm

0.1 Fm

0.1 Fm

+VS

-VS

VO

VDVI

RG

RF

1/2OPA2690

+5V

DIS

698W100W

698W

50W

402W

402W

0.1 Fm

0.1 Fm

59W

+6.8 Fm0.1 Fm

+VS

VS/2

VO

VDVI

RG

RF

OPA2690


APPLICATION INFORMATION

WIDEBAND VOLTAGE-FEEDBACK output swing on a single +5V supply with > 150MHzOPERATION bandwidth. The key requirement of broadband

single-supply operation is to maintain input andThe OPA2690 provides an exceptional combination output signal swings within the usable voltage rangesof high output power capability in a wideband, at both the input and the output. The circuit ofunity-gain stable voltage-feedback op amp using a Figure 37 establishes an input midpoint bias using anew high slew rate input stage. Typical differential simple resistive divider from the +5V supply (twoinput stages used for voltage feedback op amps are 698Ω resistors). Separate bias networks would bedesigned to steer a fixed-bias current to the required at each input. The input signal is thencompensation capacitor, setting a limit to the ac-coupled into the midpoint voltage bias. The inputachievable slew rate. The OPA2690 uses a new input voltage can swing to within 1.5V of either supply pin,stage that places the transconductance element giving a 2VPP input signal range centered betweenbetween two input buffers, using their output currents the supply pins. The input impedance matchingas the forward signal. As the error voltage increases resistor (59Ω) used for testing is adjusted to give aacross the two inputs, an increasing current is 50Ω input load when the parallel combination of thedelivered to the compensation capacitor. This biasing divider network is included.provides very high slew rate (1800V/ms) whileconsuming relatively low quiescent current(5.5mA/ch). This exceptional, full-power performancecomes at the price of a slightly higher input noisevoltage than alternative architectures. The 5.5nV/√Hzinput voltage noise for the OPA2690 is exceptionallylow for this type of input stage.

Figure 36 shows the dc-coupled, gain of +2, dualpower supply circuit configuration used as the basisof the ±5V Electrical Characteristics and TypicalCharacteristics. This is for one channel; the otherchannel is connected similarly. For test purposes, theinput impedance is set to 50Ω with a resistor toground and the output impedance is set to 50Ω with aseries output resistor. Voltage swings reported in theElectrical Characteristics are taken directly at theinput and output pins, while output powers (dBm) areat the matched 50Ω load. For the circuit of Figure 36,the total effective load will be 100Ω || 804Ω. Thedisable control line (SO-14 package only) is typically Figure 36. DC-Coupled, G = +2, Bipolar-Supplyleft open for normal amplifier operation. Two optional Specification and Test Circuitcomponents are included in Figure 36. An additionalresistor (175Ω) is included in series with thenoninverting input. Combined with the 25Ω dc sourceresistance looking back towards the signal generator,this gives an input bias current cancelling resistancethat matches the 200Ω source resistance seen at theinverting input (see the DC Accuracy and OffsetControl section). In addition to the usual power-supplydecoupling capacitors to ground, a 0.1mF capacitor isincluded between the two power-supply pins. Inpractical printed circuit board (PCB) layouts, thisoptional-added capacitor will typically improve the2nd-harmonic distortion performance by 3dB to 6dB.

Figure 37 shows the ac-coupled, gain of +2,single-supply circuit configuration used as the basisof the +5V Electrical Characteristics and TypicalCharacteristics. Though not a rail-to-rail design, theOPA2690 requires minimal input and output voltage

Figure 37. AC-Coupled, G = +2, Single-Supplyheadroom compared to other very widebandSpecification and Test Circuitvoltage-feedback op amps. It will deliver a 3VPP





70

68

66

64

62

60

58

56

54

52

50

Output Pull-Down Current (mA)

0 1 2 3 4 5 6 7 8 9 10

SF

DR

(dB

c)

V = 2V , 10MHzO PP

1/2OPA2690

402W

50W

402W

59W

1VPP

698W

698W

VI

+5V

0.1 Fm

RS

30W

IBRB

50pF

0.1 Fm

2.5V DC

±1V AC

ADC Input

Power- supply decoupling not shown.

OPA2690


Again, an additional resistor (50Ω in this case) is The OPA2690 in the circuit of Figure 39 providesincluded directly in series with the noninverting input. > 200MHz bandwidth for a 2VPP output swing.This minimum recommended value provides part of Minimal 3rd-harmonic distortion or two-tone,the dc source resistance matching for the 3rd-order intermodulation distortion will be observednoninverting input bias current. It is also used to form due to the very low crossover distortion in thea simple parasitic pole to roll off the frequency OPA2690 output stage. The limit of outputresponse at very high frequencies ( > 500MHz) using Spurious-Free Dynamic Range (SFDR) will be set bythe input parasitic capacitance. The gain resistor (RG) the 2nd-harmonic distortion. Without RB, the circuit ofis ac-coupled, giving the circuit a dc gain of +1, which Figure 39 measured at 10MHz shows an SFDR ofputs the input dc bias voltage (2.5V) on the output as 57dBc. This can be improved by pulling additional dcwell. The output voltage can swing to within 1V of bias current (IB) out of the output stage through theeither supply pin while delivering > 100mA output optional RB resistor to ground (the output midpoint iscurrent. A demanding 100Ω load to a midpoint bias is at 2.5V for Figure 39). Adjusting IB gives theused in this characterization circuit. The new output improvement in SFDR shown in Figure 38. SFDRstage circuit used in the OPA2690 can deliver large improvement is achieved for IB values up to 5mA,bipolar output currents into this midpoint load with with worse performance for higher values. Using theminimal crossover distortion, as shown in the +5V dual OPA2690 in an I/Q receiver channel will givesupply harmonic distortion plots. matched ac performance through high frequencies.

SINGLE-SUPPLY ADC INTERFACE

Most modern, high-performance ADCs (such as theTI ADS8xx and ADS9xx series) operate on a single+5V (or lower) power supply. It has been aconsiderable challenge for single-supply op amps todeliver a low distortion input signal at the ADC inputfor signal frequencies exceeding 5MHz. The highslew rate, exceptional output swing, and high linearityof the OPA2690 make it an ideal single-supply ADCdriver. The circuit on the front page shows onepossible interface particularly suited to differential I/O,ac-coupled requirements. Figure 39 shows the testcircuit of Figure 37 modified for a capacitive (ADC)load and with an optional output pull-down resistor(RB). This circuit would be suitable to dual-channelADC driving with a single-ended I/O. Figure 38. SFDR vs IB

Figure 39. SFDR versus IB Test Circuit





1/2OPA2690

1/2OPA2690

High- SpeedDAC

V = I RO O F

- -V = IO O FR

RF1

RF2

CF1

CF2

CD1

CD2

IO

-IO

50W

50W

1

2 R Cp F F

=GBP

4 R Cp F D

f =-3dB

GBP

2 R Cp DF

146W

2kW

82.5W

75 CableW

75 LoadW

RG-59

82.5W

75W

402W340W

+5V

+5V

-5V

1/2OPA2690

1/2OPA2690

146W

2kW

75W

402W340W

-5V

+5V

VDIS

DISA

DISB

Video 1

Video 2

OPA2690


HIGH-PERFORMANCE DACTRANSIMPEDANCE AMPLIFIER

High-frequency, direct digital synthesis (DDS)digital-to-analog converters (DACs) require a lowdistortion output amplifier to retain their SFDRperformance into real-world loads. Figure 40 shows asingle-ended output drive implementation. Thediagram shows the signal output current(s) connectedinto the virtual ground summing junction(s) of theOPA2690, which is set up as a transimpedance stageor I-V converter. If the DAC requires that its outputsterminate to a compliance voltage other than groundfor operation, the appropriate voltage level may beapplied to the noninverting input of the OPA2690.The dc gain for this circuit is equal to RF. At highfrequencies, the DAC output capacitance (CD inFigure 40) will produce a zero in the noise gain forthe OPA2690 that may cause peaking in theclosed-loop frequency response. CF is added acrossRF to compensate for this noise gain peaking. Toachieve a flat transimpedance frequency response,

Figure 40. DAC Transimpedance Amplifierthe pole in each feedback network should be set to:

WIDEBAND VIDEO MULTIPLEXING(1)

One common application for video speed amplifierswhich will give a cutoff frequency, f−3dB, of that include a disable pin is to wire multiple amplifierapproximately: outputs together, then select which one of several

possible video inputs to source onto a single line.This simple wired-OR video multiplexer can be easilyimplemented using the OP2690I-14D (SO-14(2)package only), as shown in Figure 6.

Where GBP = gain bandwidth product (Hz) for theOPA2690.

Figure 41. Two-Channel Video Multiplexer (SO-14 package only)





R

RF

402W

RG

402WRF

402W

RG

402W

VIN

VOUT

R

1/2OPA2690

OPA692

C

C

1/2OPA2690

OPA2690


Typically, channel switching is performed either on Each of the two filter stages is a 1st-order filter with async or retrace time in the video signal. The two voltage gain of +1. The delay time through one filterinputs are approximately equal at this time. The is given by Equation 3:make-before-break disable characteristic of the tGR0 = 2RC (3)OPA2690 ensures that there is always one amplifier

For a more accurate analysis of the circuit, considercontrolling the line when using a wired-OR circuit likethe group delay for the amplifiers. For example, in thethat shown in Figure 41. As both inputs may be on forcase of the OPA2690, the group delay in thea short period during the transition between channels,bandwidth from 1MHz to 100MHz is approximatelythe outputs are combined through the output1.0ns. To account for this, modify the transferimpedance matching resistors (82.5Ω in this case).function, which now comes out to be:When one channel is disabled, its feedback network

tGR = 2(2RC + tD) (4)forms part of the output impedance and slightlyattenuates the signal in getting out onto the cable. Where tD = (1/360) × (df/df) = delay of the op ampThe gain and output matching resistor have been itself.slightly increased to get a signal gain of +1 at thematched load and provide a 75Ω output impedance to The values of resistors RF and RG should be equalthe cable. The video multiplexer connection (see and low to avoid parasitic effects. If the all-pass filterFigure 41) also ensures that the maximum differential is designed for very low delay times, include parasiticvoltage across the inputs of the unselected channel board capacitances to calculate the correct delaydoes not exceed the rated ±1.2V maximum for time. Simulating this application using the PSPICEstandard video signal levels. model of the OPA2690 will allow this design to be

tuned to the desired performance.See the Disable Operation section for the turn-on andturn-off switching glitches using a 0V input for a DIFFERENTIAL RECEIVER/DRIVERsingle channel is typically less than ±50mV. Wheretwo outputs are switched (see Figure 41), the output A very versatile application for a dual operationalline is always under the control of one amplifier or the amplifier is the differential amplifier configurationother due to the make-before-break disable timing. In detailed in Figure 43. With both amplifiers of thethis case, the switching glitches for two 0V inputs OPA2690 connected for noninverting operation, thedrops to < 20mV. circuit provides a high input impedance whereas the

gain can easily be set by just one resistor, RG. WhenHIGH-SPEED DELAY CIRCUIT operated in low gains, the output swing may be

limited as a result of the common-mode input swingThe OPA2690 makes an ideal amplifier for a variety limits of the amplifier itself. An interesting modificationof active filter designs. Shown in Figure 42 is a circuit of this circuit is to place a capacitor in series with thethat uses the two amplifiers within the dual OPA2690 RG. Now the dc gain for each side is reduced to +1,to design a two-stage analog delay circuit. For whereas the ac gain still follows the standard transfersimplicity, the circuit uses a dual-supply (±5V) function of G = 1 + 2RF/RG. This might beoperation, but it can also be modified to operate on a advantageous for applications processing only asignal supply. The input to the first filter stage is frequency band that excludes dc or very lowdriven by the OPA692 wideband buffer amplifier to frequencies. An input dc voltage resulting from inputisolate the signal input from the filter network. bias currents is not amplified by the ac gain and can

be kept low. This circuit can be used as a differentialline receiver, driver, or as an interface to a differentialinput ADC.

Figure 42. Two-Stage, All-Pass Network






50W

VI

-VI

RO

RO

RF

402W

RF

402W

50W

RG

1/2OPA2690

1/2OPA2690

V = 1 +DIFF V (- -V )I I

2RF

RG

f =O (cutoff frequency)1

2 R Cp´ ´ ´

R = R = 0.65 R

R = 0.375 R

C = C

C = 2 C

1 ´

´

´

2

3

1

2

6kW

R2A

102W

C1A

100pF

C2

200pF

C1B

100pF

R1A

102W

R1B

102W

R3A

60W

R3B

60W

50W

6kW

+12V

VCM

VCM

VOUTVIN

1000pF

50W

1/2

OPA2690

1/2

OPA2690

R2B

102W

OPA2690


SINGLE-SUPPLY MFB DIFFERENTIALACTIVE FILTER: 10MHz BUTTERWORTHCONFIGURATION

The active filter circuit shown in Figure 44 can beeasily implemented using the OPA2690. In thisconfiguration, each amplifier of the OPA2690operates as an integrator. For this reason, this type ofapplication is also called infinite gain filterimplementation. A Butterworth filter can beimplemented using the following component ratios:

Figure 43. High-Speed Differential Receiver

(5)

Figure 44. Single-Supply, MFB Active Filter, 10MHz LP Butterworth





f =-3dB

12 R Cp F F

Gain

(dB

)

Frequency (MHz)

0.1 1 10 20

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

Diffe

rential G

ain

(dB

)

Frequency (MHz)

9

6

3

0

-3

-6

-9

-12

0.1 101 500100

C = 8.6pFF

OPA2690


The frequency response for a 10MHz Butterworth Single-Supply Differential ADC Driver), thefilter is shown in Figure 45. One advantage for using 2nd-harmonic reacts as expected and drops to athis type of filter is the independent setting of wo and −95dBc at 1MHz and −87dBc at 5MHz—a significantQ. Q can be easily adjusted by changing the R3A, B improvement in going to differential fromresistors without affecting wo. single-ended.

The circuit shown on the front page has a 195MHz,−3dB bandwidth that can be easily bandlimited byusing a capacitor in parallel with the feedbackresistors. Refer to Figure 46 for more details. The−3dB frequency is given by Equation 6.

(6)

Figure 45. Multiple Feedback Filter FrequencyResponse

SINGLE-SUPPLY DIFFERENTIAL ADCDRIVER

The circuit shown on the front page is ideal for drivinghigh-frequency ADCs. As shown in the plot on thefront page (Harmonic Distortion vs Frequency for the Figure 46. Single-Supply Differential ADC Driver

For example, CF = 8.6pF in parallel with RF = 402Ωwill control the –3dB frequency to 18MHz.





OPA2690


DESIGN-IN TOOLS

DEMONSTRATION FIXTURES MACROMODELS

Two printed circuit boards (PCBs) are available to Computer simulation of circuit performance usingassist in the initial evaluation of circuit performance SPICE is often useful when analyzing theusing the OPA2690 in its two package options. Both performance of analog circuits and systems. This isof these are offered free of charge as unpopulated particularly true for video and RF amplifier circuitsPCBs, delivered with a user’s guide. The summary where parasitic capacitance and inductance can haveinformation for these fixtures is shown in Table 1. a major effect on circuit performance. A SPICE model

for the OPA2690 (use two OPA690 SPICE models) isTable 1. Demonstration Fixtures by Package available through the OPA2690 product folder under

Simulation Models. These models do a good job ofORDERING LITERATUREpredicting small-signal ac and transient performancePRODUCT PACKAGE NUMBER NUMBERunder a wide variety of operating conditions. They do

OPA2690ID SO-8 DEM-OPA-SO-2A SBOU003not do as well in predicting the harmonic distortion or

OPA2690I- dG/dP characteristics. These models do not attemptSO-14 DEM-OPA-SO-2D SBOU00214Dto distinguish between the package types in theirsmall-signal ac performance.The demonstration fixtures can be requested at the

Texas Instruments web site (www.ti.com) through theOPA2690 product folder.





http://www.ti.com/lit/pdf/SBOU003

http://www.ti.com/lit/pdf/SBOU002



OPA2690


OPERATING SUGGESTIONS

OPTIMIZING RESISTOR VALUES BANDWIDTH vs GAIN: NONINVERTINGOPERATION

As the the OPA2690 is a unity-gain stable,voltage-feedback op amp, a wide range of resistor Voltage-feedback op amps exhibit decreasingvalues may be used for the feedback and gain setting closed-loop bandwidth as the signal gain isresistors. The primary limits on these values are set increased. In theory, this relationship is described byby dynamic range (noise and distortion) and parasitic the Gain Bandwidth Product (GBP) shown in thecapacitance considerations. For a noninverting Electrical Characteristics. Ideally, dividing GBP by theunity-gain follower application, the feedback noninverting signal gain (also called the Noise Gain,connection should be made with a 25Ω resistor, not a or NG) will predict the closed-loop bandwidth. Indirect short. This will isolate the inverting input practice, this only holds true when the phase margincapacitance from the output pin and improve the approaches 90°, as it does in high gainfrequency response flatness. Usually, the feedback configurations. At low gains (increased feedbackresistor value should be between 200Ω and 1.5kΩ. factors), most amplifiers will exhibit a more complexBelow 200Ω, the feedback network will present response with lower phase margin. The OPA2690 isadditional output loading which can degrade the compensated to give a slightly peaked response in aharmonic distortion performance of the OPA2690. noninverting gain of 2 (see Figure 36). This results inAbove 1.5kΩ, the typical parasitic capacitance a typical gain of +2 bandwidth of 220MHz, far(approximately 0.2pF) across the feedback resistor exceeding that predicted by dividing the 300MHzcan cause unintentional band-limiting in the amplifier GBP by 2. Increasing the gain will cause the phaseresponse. margin to approach 90° and the bandwidth to more

closely approach the predicted value of (GBP/NG). AtA good rule of thumb is to target the parallel a gain of +10, the 30MHz bandwidth shown in thecombination of RF and RG (see Figure 36) to be less Electrical Characteristics agrees with that predictedthan approximately 300Ω. The combined impedance using the simple formula and the typical GBP ofRF || RG interacts with the inverting input capacitance, 300MHz.placing an additional pole in the feedback networkand thus, a zero in the forward response. Assuming a The frequency response in a gain of +2 may be2pF total parasitic on the inverting node, holding RF || modified to achieve exceptional flatness simply byRG < 300Ω will keep this pole above 250MHz. By increasing the noise gain to 2.5. One way to do this,itself, this constraint implies that feedback resistor RF without affecting the +2 signal gain, is to add ancan increase to several kΩ at high gains. This is 804Ω resistor across the two inputs in the circuit ofacceptable as long as the pole formed by RF and any Figure 36. A similar technique may be used to reduceparasitic capacitance appearing in parallel is kept out peaking in unity-gain (voltage follower) applications.of the frequency range of interest. For example, by using a 402Ω feedback resistor

along with a 402Ω resistor across the two op ampinputs, the voltage follower response will be similar tothe gain of +2 response of Figure 37. Reducing thevalue of the resistor across the op amp inputs willfurther limit the frequency response due to increasednoise gain.

The OPA2690 exhibits minimal bandwidth reductiongoing to single-supply (+5V) operation as comparedwith ±5V. This is because the internal bias controlcircuitry retains nearly constant quiescent current asthe total supply voltage between the supply pins ischanged.





1/2OPA2690

50WRF

402W

RG

200W

RB

146W

RM

67W

Source

+5V

-5V

RO

50W

0.1 Fm 6.8 Fm+

0.1 Fm

0.1 Fm

6.8 Fm+

50 LoadW

VO

VI

= 2-

VO

VI

OPA2690


INVERTING AMPLIFIER OPERATION 100Ω feedback resistor. This has the interestingadvantage that the noise gain becomes equal to 2 for

Since the OPA2690 is a general-purpose, wideband a 50Ω source impedance—the same as thevoltage-feedback op amp, all of the familiar op amp noninverting circuits considered in the previousapplication circuits are available to the designer. section. The amplifier output, however, will now seeInverting operation is one of the more common the 100Ω feedback resistor in parallel with therequirements and offers several performance external load. In general, the feedback resistor shouldbenefits. Figure 47 shows a typical inverting be limited to the 200Ω to 1.5kΩ range. In this case, itconfiguration where the I/O impedances and signal is preferable to increase both the RF and RG values,gain from Figure 36 are retained in an inverting circuit as shown in Figure 47, and then achieve the inputconfiguration. matching impedance with a third resistor (RM) to

ground. The total input impedance becomes theparallel combination of RG and RM.

The second major consideration, touched on in theprevious paragraph, is that the signal sourceimpedance becomes part of the noise gain equationand influences the bandwidth. For the example inFigure 47, the RM value combines in parallel with theexternal 50Ω source impedance, yielding an effectivedriving impedance of 50Ω || 67Ω = 28.6Ω. Thisimpedance is added in series with RG for calculatingthe noise gain (NG). The resultant NG is 2.8 forFigure 47, as opposed to only 2 if RM could beeliminated as discussed above. The bandwidth willtherefore be slightly lower for the gain of –2 circuit ofFigure 47 than for the gain of +2 circuit of Figure 36.

The third important consideration in inverting amplifierdesign is setting the bias current cancellation resistoron the noninverting input (RB). If this resistor is setequal to the total dc resistance looking out of theinverting node, the output dc error, due to the inputbias currents, will be reduced to (Input Offset Current)× RF. If the 50Ω source impedance is dc-coupled inFigure 47. Gain of –2 Example CircuitFigure 47, the total resistance to ground on theinverting input will be 228Ω. Combining this in parallel

In the inverting configuration, three key design with the feedback resistor gives the RB = 146Ω usedconsiderations must be noted. The first is that the in this example. To reduce the additionalgain resistor (RG) becomes part of the signal channel high-frequency noise introduced by this resistor, it isinput impedance. If input impedance matching is sometimes bypassed with a capacitor. As long as RBdesired (which is beneficial whenever the signal is < 350Ω, the capacitor is not required because thecoupled through a cable, twisted-pair, long PCB total noise contribution of all other terms will be lesstrace, or other transmission line conductor), RG may than that of the op amp input noise voltage. As abe set equal to the required termination value and RF minimum, the OPA2690 requires an RB value of 50Ωadjusted to give the desired gain. This is the simplest to damp out parasitic-induced peaking—a direct shortapproach and results in optimum bandwidth and to ground on the noninverting input runs the risk of anoise performance. However, at low inverting gains, very high-frequency instability in the input stage.the resultant feedback resistor value can present asignificant load to the amplifier output. For aninverting gain of –2, setting RG to 50Ω for inputmatching eliminates the need for RM but requires a





1/2OPA2690

402W

175W

402W

+5V

50W

50W

CLOAD

RNGVO

R

-5V

Power-supply decoupling

not shown.

OPA2690


OUTPUT CURRENT AND VOLTAGE OPA2690 can be very susceptible to decreasedstability and closed-loop response peaking when a

The OPA2690 provides output voltage and current capacitive load is placed directly on the output pin.capabilities in a low-cost monolithic op amp. Under When the amplifier's open-loop output resistance isno-load conditions at +25°C, the output voltage considered, this capacitive load introduces antypically swings closer than 1V to either supply rail; additional pole in the signal path that can decreasethe specified swing limit is within 1.2V of either rail. the phase margin. Several external solutions to thisInto a 15Ω load (the minimum tested load), it will problem have been suggested. When the primarydeliver more than ±160mA. considerations are frequency response flatness,

pulse response fidelity, and/or distortion, the simplestThe specifications described previously, thoughand most effective solution is to isolate the capacitivefamiliar in the industry, consider voltage and currentload from the feedback loop by inserting alimits separately. In many applications, it is theseries-isolation resistor between the amplifier outputvoltage × current, or V-I product, that is more relevantand the capacitive load. This does not eliminate theto circuit operation. Refer to Figure 19, the Outputpole from the loop response, but rather shifts it andVoltage and Current Limitations plot in the Typicaladds a zero at a higher frequency. The additionalCharacteristics. The X- and Y-axes of this graphzero acts to cancel the phase lag from the capacitiveshow the zero-voltage output current limit and theload pole, thus increasing the phase margin andzero-current output voltage limit, respectively. Theimproving stability.four quadrants give a more detailed view of the

OPA2690 output drive capabilities, noting that the The Typical Characteristics show the recommendedgraph is bounded by a Safe Operating Area of 1W RS versus capacitive load (Figure 15 for ±5V andmaximum internal power dissipation for each channel Figure 30 for +5V) and the resulting frequencyseparately. Superimposing resistor load lines onto the response at the load. Parasitic capacitive loadsplot shows that the OPA2690 can drive ±2.5V into greater than 2pF can begin to degrade the25Ω or ±3.5V into 50Ω without exceeding the output performance of the OPA2690. Long PCB traces,capabilities or the 1W dissipation limit. A 100Ω load unmatched cables, and connections to multipleline (the standard test circuit load) shows the full devices can easily exceed this value. Always±3.9V output swing capability (see the Electrical consider this effect carefully, and add theCharacteristics). recommended series resistor as close as possible to

the OPA2690 output pin (see the Board LayoutThe minimum specified output voltage and currentGuidelines section).specifications over temperature are set by worst-case

simulations at the cold temperature extreme. Only at The criterion for setting this RS resistor is a maximumcold startup will the output current and voltage bandwidth, flat frequency response at the load. Fordecrease to the numbers shown in the Electrical the OPA2690 operating in a gain of +2, the frequencyCharacteristic tables. As the output transistors deliver response at the output pin is already slightly peakedpower, their junction temperatures increase, without the capacitive load requiring relatively highdecreasing their VBEs (increasing the available output values of RS to flatten the response at the load.voltage swing) and increasing their current gains Increasing the noise gain will reduce the peaking as(increasing the available output current). In described previously. The circuit of Figure 48steady-state operation, the available output voltage demonstrates this technique, allowing lower values ofand current is always greater than that shown in the RS to be used for a given capacitive load.over-temperature specifications because the outputstage junction temperatures will be higher than theminimum specified operating ambient.

To protect the output stage from accidental shorts toground and the power supplies, output short-circuitprotection is included in the OPA2690. The circuitacts to limit the maximum source or sink current toapproximately 250mA.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very commonload conditions for an op amp is capacitive loading.Often, the capacitive load is the input of anADC—including additional external capacitance whichmay be recommended to improve ADC linearity. A Figure 48. Capacitive Load Driving with Noisehigh-speed, high open-loop gain amplifier like the Gain Tuning





100

90

80

70

60

50

40

30

20

10

0


1 10 100 1000

RS

(W)

NG = 2

NG = 3

NG = 4

4kT

RG

RG

RF

RS

1/2

OPA2690

IBI

EO

IBN

4kT = 1.6E 20J-

at 290 K°

ERS

ENI

4kTRSÖ

4kTRFÖ

OPA2690


This gain of +2 circuit includes a noise gain tuning In most op amps, increasing the output voltage swingresistor across the two inputs to increase the noise increases harmonic distortion directly. The newgain, increasing the unloaded phase margin for the output stage used in the OPA2690 actually holds theop amp. Although this technique will reduce the difference between fundamental power and the 2nd-required RS resistor for a given capacitive load, it and 3rd-harmonic powers relatively constant withdoes increase the noise at the output. It also will increasing output power until very large output swingsdecrease the loop gain, slightly decreasing the are required ( > 4VPP). This also shows up in thedistortion performance. If, however, the dominant 2-tone, 3rd-order intermodulation spurious (IM3)distortion mechanism arises from a high RS value, response curves. The 3rd-order spurious levels aresignificant dynamic range improvement can be moderately low at low output power levels. Theachieved using this technique. Figure 49 shows the output stage continues to hold them low even as therequired RS versus CLOAD parametric on noise gain fundamental power reaches very high levels. As theusing this technique. This is the circuit of Figure 48 Typical Characteristics show, the spuriouswith RNG adjusted to increase the noise gain intermodulation powers do not increase as predicted(increasing the phase margin) then sweeping CLOAD by a traditional intercept model. As the fundamentaland finding the required RS to get a flat frequency power level increases, the dynamic range does notresponse. This plot also gives the required RS versus decrease significantly. For two tones centered atCLOAD for the OPA2690 operated at higher signal 20MHz, with 10dBm/tone into a matched 50Ω loadgains without RNG. (that is, 2VPP for each tone at the load, which requires

8VPP for the overall two-tone envelope at the outputpin), the Typical Characteristics show 46dBcdifference between the test tone powers and the3rd-order intermodulation spurious powers. Thisexceptional performance improves further whenoperating at lower frequencies or powers.

NOISE PERFORMANCE

High slew rate, unity-gain stable, voltage-feedback opamps usually achieve their slew rate at the expenseof a higher input noise voltage. The 5.5nV/√Hz inputvoltage noise for the OPA2690 is, however, muchlower than comparable amplifiers. The input-referredvoltage noise, and the two input-referred currentnoise terms, combine to give low output noise undera wide variety of operating conditions. Figure 50

Figure 49. Required RS vs Noise Gain shows the op amp noise analysis model with all thenoise terms included. In this model, all noise termsare taken to be noise voltage or current density terms

DISTORTION PERFORMANCE in either nV/√Hz or pA/√Hz.

The OPA2690 provides good distortion performanceinto a 100Ω load on ±5V supplies. Relative toalternative solutions, it provides exceptionalperformance into lighter loads and/or operating on asingle +5V supply. Generally, until the fundamentalsignal reaches very high frequency or power levels,the 2nd-harmonic dominates the distortion with anegligible 3rd-harmonic component. Focusing then onthe 2nd-harmonic, increasing the load impedanceimproves distortion directly. Remember that the totalload includes the feedback network; in thenoninverting configuration (see Figure 36), this is sumof RF + RG, while in the inverting configuration it isjust RF. Also, providing an additionalsupply-decoupling capacitor (0.1mF) between thesupply pins (for bipolar operation) improves the

Figure 50. Op Amp Noise Analysis Model2nd-order distortion slightly (3dB to 6dB). Operatingdifferentially also lowers 2nd-harmonic distortionterms (see the plot on the front page).





E =O ENI2 + (I R ) + 4kTRBN S S

2 NG + (I R ) + 4kTR NG2 2BI F F

E =N

I RBI F

NGE + (I R ) + 4kTR +NI BN S S

22 +4kTRF

NG

2

RF

1kW

±200mV Output Adjustment

= = 2- -

Power-supply

decoupling not shown.

5kW

5kW

328W0.1 Fm

RG

500W

VI

20kW

10kW

0.1 Fm

-5V

+5V

1/2OPA2690

+5V

-5V

VO

VO

VI

RF

RG

OPA2690


The total output spot noise voltage can be computed ±(NG × VOS(MAX)) ± (RF × IOS(MAX))as the square root of the sum of all squared output = ±(2 × 4.5mV) ± (402Ω × 1mA)noise voltage contributors. Equation 7 shows the = ±9.4mV – (NG = noninverting signal gain)general form for the output noise voltage using the

A fine-scale output offset null, or dc operating pointterms shown in Figure 50.adjustment, is often required. Numerous techniquesare available for introducing dc offset control into anop amp circuit. Most of these techniques eventually(7)reduce to adding a dc current through the feedback

Dividing this expression by the noise gain [NG = (1 + resistor. In selecting an offset trim method, one keyRF/RG)] will give the equivalent input-referred spot consideration is the impact on the desired signal pathnoise voltage at the noninverting input, as shown in frequency response. If the signal path is intended toEquation 8. be noninverting, the offset control is best applied as

an inverting summing signal to avoid interaction withthe signal source. If the signal path is intended to beinverting, applying the offset control to the

(8) noninverting input may be considered. However, thedc offset voltage on the summing junction will set upEvaluating these two equations for the OPA2690a dc current back into the source that must becircuit and component values (see Figure 36) gives aconsidered. Applying an offset adjustment to thetotal output spot noise voltage of 12.3nV/√Hz and ainverting op amp input can change the noise gain andtotal equivalent input spot noise voltage of 6.1nV/√Hz.frequency response flatness. For a dc-coupledThis is including the noise added by the bias currentinverting amplifier, Figure 51 shows one example ofcancellation resistor (175Ω) on the noninverting input.an offset adjustment technique that has minimalThis total input-referred spot noise voltage is onlyimpact on the signal frequency response. In thisslightly higher than the 5.5nV/√Hz specification for thecase, the dc offsetting current is brought into theop amp voltage noise alone. This will be the case asinverting input node through resistor values that arelong as the impedances appearing at each op ampmuch larger than the signal path resistors. Thisinput are limited to the previously recommendensures that the adjustment circuit has minimal effectmaximum value of 300Ω. Keeping both (RF || RG) andon the loop gain and hence, the frequency response.the noninverting input source impedance less than

300Ω will satisfy both noise and frequency responseflatness considerations. As the resistor-induced noiseis relatively negligible, additional capacitivedecoupling across the bias current cancellationresistor (RB) for the inverting op amp configuration ofFigure 47 is not required.

DC ACCURACY AND OFFSET CONTROL

The balanced input stage of a widebandvoltage-feedback op amp allows good output dcaccuracy in a wide variety of applications. Thepower-supply current trim for the OPA2690 giveseven tighter control than comparable amplifiers.Although the high-speed input stage does requirerelatively high input bias current (typically 5mA out ofeach input terminal), the close matching betweenthem may be used to reduce the output dc errorcaused by this current. The total output offset voltagemay be considerably reduced by matching the dcsource resistances appearing at the two inputs. Thisreduces the output dc error due to the input bias Figure 51. DC-Coupled, Inverting Gain of -2, withcurrents to the offset current times the feedback Offset Adjustmentresistor. Evaluating the configuration of Figure 36,and using worst-case +25°C input offset voltage andcurrent specifications, gives a worst-case outputoffset voltage equal to:

BLANKSPACEBLANKSPACE





25kW 110kW

15kW

ISControl -VS

+VS

VDIS

Q1

Time (20ns/div)

Outp

ut V

oltage (

10m

V/d

iv)

30

20

10

0

-10

-20

-30

V(2

V/d

iv)

DIS

6

4

2

0

V = 0VI

VDIS

Output Voltage

OPA2690


DISABLE OPERATION (SO-14 Package Only) the output and exceptional signal isolation. Ifoperating at a gain greater than +1, the total

The OPA2690-I-14D provides an optional disable feedback network resistance (RF + RG) will appear asfeature that may be used either to reduce system the impedance looking back into the output, but thepower or to implement a simple channel multiplexing circuit will still show very high forward and reverseoperation. If the DIS control pin is left unconnected, isolation. If configured as an inverting amplifier, thethe OPA2690I-14D will operate normally. To disable, input and output will be connected through thethe control pin must be asserted LOW. Figure 52 feedback network resistance (RF + RG) and theshows a simplified internal circuit for the disable isolation will be very poor as a result.control feature.

One key parameter in disable operation is the outputglitch when switching in and out of the disabledmode. Figure 53 shows these glitches for the circuitof Figure 36 with the input signal at 0V. The glitchwaveform at the output pin is plotted along with theDIS pin voltage.

The transition edge rate (dV/dt) of the DIS control linewill influence this glitch. For the plot of Figure 53, theedge rate was reduced until no further reduction inglitch amplitude was observed. This approximately1V/ns maximum slew rate may be achieved byadding a simple RC filter into the DIS pin from ahigher speed logic line. If extremely fast transitionlogic is used, a 2kΩ series resistor between the logicgate and the DIS input pin provides adequatebandlimiting using just the parasitic input capacitanceon the DIS pin while still ensuring adequate logiclevel swing.

Figure 52. Simplified Disable Control Circuit

In normal operation, base current to Q1 is providedthrough the 110kΩ resistor, while the emitter currentthrough the 15kΩ resistor sets up a voltage drop thatis inadequate to turn on the two diodes in Q1'semitter. As VDIS is pulled LOW, additional current ispulled through the 15kΩ resistor, eventually turningon those two diodes (≈100mA). At this point, anyfurther current pulled out of VDIS goes through thosediodes holding the emitter-base voltage of Q1 atapproximately 0V. This shuts off the collector currentout of Q1, turning the amplifier off. The supply currentin the disable mode are only those required tooperate the circuit of Figure 52. Additional circuitryensures that turn-on time occurs faster than turn-off Figure 53. Disable/Enable Glitchtime (make-before-break).

When disabled, the output and input nodes go to ahigh-impedance state. If the OPA2690 is operating ata gain of +1, this will show a very high impedance at





OPA2690


THERMAL ANALYSIS Note that it is the power in the output stage and notinto the load that determines internal power

Due to the high output power capability of the dissipation.OPA2690, heatsinking or forced airflow may berequired under extreme operating conditions. As a worst-case example, compute the maximum TJMaximum desired junction temperature will set the using an OPA2690ID (SO-8 package) in the circuit ofmaximum allowed internal power dissipation as Figure 36 operating at the maximum specifieddescribed below. In no case should the maximum ambient temperature of +85°C and with both outputsjunction temperature be allowed to exceed 150°C. driving a grounded 20Ω load to +2.5V.

Operating junction temperature (TJ) is given by: PD = 10V × 12.6mA + 2 [52/(4 × (20Ω || 804Ω))TA + PD × qJA PD = 766mW

The total internal power dissipation (PD) is the sum of Maximum TJ = +85°C + (0.766W × 125°C/W)quiescent power (PDQ) and additional power

PD = 180°Cdissipated in the output stage (PDL) to deliver loadpower. Quiescent power is simply the specified This absolute worst-case condition exceeds theno-load supply current times the total supply voltage specified maximum junction temperature. Actual PDLacross the part. PDL depends on the required output is normally less than that considered here. Carefullysignal and load but, for a grounded resistive load, is consider maximum TJ in your application.at a maximum when the output is fixed at a voltageequal to 1/2 of either supply voltage (for equal bipolarsupplies). Under this condition, PDL = VS2/(4 × RL)where RL includes feedback network loading.





OPA2690


BOARD LAYOUT GUIDELINES

0.2pF in shunt with the resistor. For resistorAchieving optimum performance with a values > 1.5kΩ, this parasitic capacitance canhigh-frequency amplifier like the OPA2690 requires add a pole and/or zero below 500MHz that cancareful attention to board layout parasitics and affect circuit operation. Keep resistor values asexternal component types. Recommendations that low as possible consistent with load drivingwill optimize performance include: considerations. The 402Ω feedback used in thea. Minimize parasitic capacitance to any ac Electrical Characteristics is a good starting point

ground for all of the signal I/O pins. Parasitic for design. Note that a 25Ω feedback resistor,capacitance on the output and inverting input pins rather than a direct short, is suggested for thecan cause instability: on the noninverting input, it unity-gain follower application. This effectivelycan react with the source impedance to cause isolates the inverting input capacitance from theunintentional bandlimiting. To reduce unwanted output pin that would otherwise cause ancapacitance, a window around the signal I/O pins additional peaking in the gain of +1 frequencyshould be opened in all of the ground and power response.planes around those pins. Otherwise, ground and d. Connections to other wideband devices on thepower planes should be unbroken elsewhere on board may be made with short, direct traces orthe board. through onboard transmission lines. For short

b. Minimize the distance (< 0.25") from the connections, consider the trace and the input topower-supply pins to high-frequency 0.1mF the next device as a lumped capacitive load.decoupling capacitors. At the device pins, the Relatively wide traces (50mils or 1,27mm toground and power-plane layout should not be in 100mils or 2,54mm) should be used, preferablyclose proximity to the signal I/O pins. Avoid with ground and power planes opened up aroundnarrow power and ground traces to minimize them. Estimate the total capacitive load and setinductance between the pins and the decoupling RS from the plot of Recommended RS vscapacitors. The power-supply connections should Capacitive Load (Figure 15 for ±5V and Figure 30always be decoupled with these capacitors. An for +5V). Low parasitic capacitive loads (< 3pF)optional supply decoupling capacitor (0.1mF) may not need an RS because the OPA2690 isacross the two power supplies (for bipolar nominally compensated to operate with a 2pFoperation) will improve 2nd-harmonic distortion parasitic load. Higher parasitic capacitive loadsperformance. Larger (2.2mF to 6.8mF) decoupling without an RS are allowed as the signal gaincapacitors, effective at lower frequencies, should increases (increasing the unloaded phasealso be used on the main supply pins. These may margin; see Figure 49). If a long trace is required,be placed somewhat farther from the device and and the 6dB signal loss intrinsic to amay be shared among several devices in the doubly-terminated transmission line issame area of the PCB. acceptable, implement a matched impedance

transmission line using microstrip or striplinec. Careful selection and placement of externaltechniques (consult an ECL design handbook forcomponents will preserve the high-frequencymicrostrip and stripline layout techniques). A 50Ωperformance of the OPA2690. Resistors shouldenvironment is normally not necessary on board,be a very low reactance type. Surface-mountand in fact, a higher impedance environment willresistors work best and allow a tighter overallimprove distortion as shown in the distortionlayout. Metal film or carbon compositionversus load plots (Figure 7 for the ±5v andaxially-leaded resistors can also provide goodFigure 32 for the +5V). With a characteristichigh-frequency performance. Again, keep theirboard trace impedance defined (based on boardleads and PCB traces as short as possible. Nevermaterial and trace dimensions), a matching seriesuse wirewound type resistors in a high-frequencyresistor into the trace from the output of theapplication. Since the output pin and invertingOPA2690 is used as well as a terminating shuntinput pin are the most sensitive to parasiticresistor at the input of the destination device.capacitance, always position the feedback andRemember also that the terminating impedanceseries output resistor, if any, as close as possiblewill be the parallel combination of the shuntto the output pin. Other network components,resistor and the input impedance of thesuch as noninverting input termination resistors,destination device; this total effective impedanceshould also be placed close to the package. Evenshould be set to match the trace impedance. Thewith a low parasitic capacitance shunting thehigh output voltage and current capability of theexternal resistors, excessively high resistorOPA2690 allows multiple destination devices tovalues can create significant time constants thatbe handled as separate transmission lines, eachcan degrade performance. Good axial metal filmwith their own series and shunt terminations. Ifor surface-mount resistors have approximately





ExternalPin

+VCC

-VCC

InternalCircuitry

OPA2690


the 6dB attenuation of a doubly-terminated INPUT AND ESD PROTECTIONtransmission line is unacceptable, a long trace

The OPA2690 is built using a very high-speedcan be series-terminated at the source end only.complementary bipolar process. The internal junctionTreat the trace as a capacitive load in this casebreakdown voltages are relatively low for these veryand set the series resistor value as shown in thesmall geometry devices. These breakdowns areplots of Recommended RS vs Capacitive Loadreflected in the Absolute Maximum Ratings table. All(Figure 15 for ±5V and Figure 30 for +5V). Thisdevice pins are protected with internal ESD protectionwill not preserve signal integrity as well as adiodes to the power supplies, as shown in Figure 54.doubly-terminated line. If the input impedance of

the destination device is low, there will be somesignal attenuation due to the voltage dividerformed by the series output into the terminatingimpedance.

e. Socketing a high-speed part like the OPA2690is not recommended. The additional lead lengthand pin-to-pin capacitance introduced by thesocket can create an extremely troublesomeparasitic network which can make it almost

Figure 54. Internal ESD Protectionimpossible to achieve a smooth, stable frequencyresponse. Best results are obtained by solderingthe OPA2690 onto the board. These diodes provide moderate protection to input

overdrive voltages above the supplies as well. Theprotection diodes can typically support 30mAcontinuous current. Where higher currents arepossible (for example, in systems with ±15V supplyparts driving into the OPA2690), current-limitingseries resistors should be added into the two inputs.Keep these resistor values as low as possible sincehigh values degrade both noise performance andfrequency response.





OPA2690


REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (August 2008) to Revision G Page

• Changed data sheet format to current standards ................................................................................................................. 1

• Changed Related Products table .......................................................................................................................................... 1

• Deleted Lead Temperature specification from Absolute Maximum Ratings table ................................................................ 2

• Changed test levels for Slew Rate, 2nd-Harmonic, and Channel-to-Channel Crosstalk parameters .................................. 3

• Changed test level for Control Pin Input Bias Current parameter ........................................................................................ 5

• Changed circuit within Figure 5 ............................................................................................................................................ 7

• Added Figure 25, Noninverting Overdrive Recovery graph ................................................................................................ 11

• Changed VO to VI in Figure 53 ............................................................................................................................................ 26

Changes from Revision E (May 2006) to Revision F Page

• Changed Storage Temperature minimum value from −40°C to −65°C ................................................................................ 2





PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

OPA2690I-14D ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA2690

OPA2690I-14DR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)


OPA2690I-14DRG4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)


OPA2690ID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)


OPA2690IDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)


OPA2690IDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


OPA2690IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

http://www.ti.com/product/OPA2690?CMP=conv-poasamples#samplebuy







http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Addendum-Page 2

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA2690I-14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

OPA2690IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA2690I-14DR SOIC D 14 2500 367.0 367.0 38.0

OPA2690IDR SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

Pack Materials-Page 2

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dual, wideband, voltage-feedback operational amplifier with

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