AABIOS(Advanced Basic I/O System) AbrasivePC BIOS , ABIOS .

PKG . Absorption Constant () . Absorption Dichroism ( ) .

Accel Mode

( 32-200KeV.)

AC Characteristic

Device Timimg .

Acceptable Quality Level

. Sampling, Lot Batch (variant unit) . (variant unit) () .

Acceptance Sampling

. Sampling , Sampling , . Acceptance Tests () .

Acceptor

3 (hole;) 3 Acceptor . Acceptor Level(Acceptor ) Hole P Level Acceptor Level .

ACI (After Cleaning Inspection)

, , , CD(Critical Dimension : ) . Active Matrix Drive ( )

contrastresponse . .

Accumulation

MOSGate Bias silicon surface Gate Majority Carrier(, substrate Carrier) Density .

Accuracy

, . Active Element () . .

ADART (Automatic Distribution Analysis in Real Time) A/D Converter (Analog to Digital Converter)

Program, .

"1" "0" . ADC .

Additive Process ( ; ) .

Address Pre-Decoder

Row/Column Address Decoding Address Buffer internal Address AN, / AN Decoding . Addressing Technology ( ) LCD-Addressing .

Adhesion

WF WF . ( )

ADI(After Development Inspection)

, Pattern , CD . Agitation() WF

AGV

(Automatic Guided Vehicle, ) Intra-bay cassette 6 . LCD lot .

AH (Absolute Humidity)

.

AHU (Air Handling Unit)

, , Particle .

Air Gun

, .

Air Shower

FAB Line , box .

Alignment

WF mask . Ali gner() .

Alignment Mark Alloy

Align Align .

Si AI .

ALPG (Algorithmic Pattern Generator)

Device Data , instruction Coding

Alpha-particle

He() U Th trace contamination IC , sillicon hole-electron pairs Soft error .

Al-Target Ambient

Wafer Al() Al.

Carrier Gas (N2, O2, H2)

.

AMLCD (Active Matrix Liquid Crystal Display)

Amorphous

Silicon .

Amplification Analog

( ) .

.

Analog IC

IC .

Analog Memory

.

Analysis of Variance (ANOVA)

Analyzer Anelva

Wafer .

(Al, Cu, Ti) , .

Angstrom ()

1 =110-8 cm H+ = 0.059210-8

Anicon

LTO(Low Temperature Oxide) deposition

Anisotropic Etching

, () Isotropic Etching ( )

Annealing

, Si N2 Ar gas Oxide quality bulk silicon defect damage cure . Annular Ring ( ) .

Anode

. .

ANSI (American National Standard Institute) .

Antimony

Wafer , N Sb.

Anti Reflect

Polycide silicon 11.0 photo pattern . SiO2 TiN silicide pattern TiN ARC .

Antistatic

AOQ (Average Outgoing Quality)

lot lot . (AOQ)= LOT LOT >

AOQL (Average Outgoing Quality) Application Test

: AOQ

() , .

APCVD

Atmospheric Dressure CVD(Chemical Vapor Deposit-ion). (Vapor) , Gas Chamber .

APD (Avlanche Photo Diode)

PN Photo Diod e.

AQL (Acceptable Quality Level)

Sampling lot , lot .

Ar

Argon Gas

Arc Chamber Arc Current

lon .

Plasma Bean Arc Chamber

ARL (Acceptable Reliability Level) Array

.

Device .

Array Logic

FILP-FLOP, NAND, NOR, Diode Logic Circuit Array () Device.

Artwork Master

Film 1:1

As

(Arsenic)

Ashing

/ (Dry Strip) .

ASIC (Application Specific IC)

(), () IC , IC .

ASIC Memory

Memory. Computer Multi-port Video RAM(VRAM), data cache memory , dark memory . Frame memory Line memory . Dual-port memory FIFO(First In First Out) .

ASIC micon

User 1chip micon. microprocessor microcontroller CPU(CPU core ), CPU, ROM, RAM, Random Logic User system 1 chip . User , , , .

Aspect Ratio

Step Coverage . Assembly .

ASRP (Autoexec Spreading Resistance Probe) Assignable Cause

Silicon Wafer .

.

ASSP (Application Specific Standard Product)

IC. user IC, , IC , Printer controller .

ATE (Automatic Test Equipment) Au-Bond (gold ball Bond) Auto-Doping

Test .

Bonding

.

Auto Loader

(FAB, TEST, ASS'Y) .

Automatic Loading System Auto Transfer

Carrier Wafer .

Wafer Boat Loading Unloading . Auto Transport System ( ) computer system System. Av Voltage Gain,

AV TFT-LCD(AUDIO-VIDEO, TFT-LCD)

, TFT-LCD 1.1 inch 12 .

Avalanche breakdown

Pin Diode (reverse bias) breakdown Zener breakdow n mechanism doping Junction transition region Field electron electron-hole pairs impact ionization mechanism carrier Breakdown .

Avalanche Injection Diode

P+ N+ Diode

Avalanche Transistor

TR TR OFF Avalanche Breakdown ON .

Average Outgoing Quality Level (AOQL)

. sampling , (AOQ) .

A.W.W (Acid Waste Water)

.

Axial Fan Fan Clean Room , .

B

Backward Current

PN .(Reverse Current ) Back Flow Effect ( ) . Back Grind ( ) Wafer , Fab.

.

Back Plane

Back Panel

Fab. Line Bay Room PVC Back Panel . , Particle Room .

Back Seal Oxide

, Wafer Outdoping Wafer .

Back Side Grind

. Wafer Wafer Get tering .

Back Seal Marking

Device Marking lot Fab. Site lot# Device Marking.

Back-Annotation

layout layout ( ) simulation .

Back-Up System

, Gas .

Baffle Bake

Gas control .

Wafer Pre-Bake, Hard-Bake, Soft-Bake . 1) Pre-bake : Wafer Resist Wafer 15010 Oven Wafer 2) Hard-bake : Etch Wafer Resist 3) Soft-bake : Photo-Resist

Base Array

ASIC Process Gate (2 Input Nand gate or 2 Input Nor gate) userable gat e array LSI .

Base Line Spec

process flow . Base Line FAB Base Material () Basic Dimension () .

Batonnet

.

B/B Ratio (Book to Bill Ratio)

3 3 WSTS( ) Da ta . , B/B Ratio .

BC (Buried Contact) BCD Technology

POLY1 N+ Active contact POC 13 doping .

Bipolar, CMOS, DMOS , Bipolar , CMOS digital logic DMOS . (BCD system reliability .)

BCG Approach(Boston Consulting Group Approach) , (SBU) 2 , . .

BCR (Bar Cod Reader) Bean Line

Bar Code .

Source lon Beam .

Beam Mask

Beam , Wafer .

Beam Spectrum

, .

Behavioral Description

System input output computer language . VHDL(very high speed hardware descri-ption language), HDL .

Bench Test

Test Pattern Die DC Probing Electric al Paramet-er Bent Lead () 45 .

Bias Bias

. () System error.

TR 0 0 Bias .

Bidirectional Buffer

signal voltage level , sense AMP data ext-ernal load driv e Buffer.

Bipolar

(electron) (hole) ( Transistor )

Bipolar TR

TR NPN Type PNP Type 2 . Emitter, Base, Collector 3 , Base Emitter Collector . Transistor Bipolar IC .

BI-MOS

MOS Chip .

BiCMOS (Bipolar-CMOS)

Bipolar Transistor CMOS Transistor Chip IC. Bipolar Transistor , CMOS . Binary Number System (2) 0 1 .

B/I (Burn-in)

( 83, 63) .

Bin

. ) Bin 1-, Bin13-, Bin 15-Parameter .

Bin 1 Check

Test .

Bin Grade Down

Test Step Good Device speed power .

Bit Line Bit Map

Memory data data data .

Memory CheckMemory Data Cell ( Cell )

Bit Mapper

, Fail Point Address Fail F/A Tool. Bit Fail Device Test Random Address Cell Fail .

Black & White SPOT

, pinhole seak .

Black Hole

F/A Contact Contact Pattern Poly or Metal Pattern Misalign Over Etch Contact Overap Contact Edge Chemi-cal Contact Defect.

Black Stripe SM

Blade

Wafer . Bleeding () . .

Blister

.

Block Factors

Block. Block Block Block

.

Blow Hole BN Wafer

(Solder).

Boron Wafer Boron Wafer Wafer. BN BN Wafer Tube 375 N2 .

Boat

Wafer SiC Wafer .

Boat Holder Bonding

Boat Poly-Si .

wire bonding Chip PAD .

Bond Diode

Bonding Layor ()

Bonding Pad

Chip wire bonding . Bond Strength () .

Bottom Up Design

Primitive Cell Circuit Level, Logic Level, Architechure L evel IC .

Boulder

FAB Diffusion . Bow () Wafer Wafer film

BPSG

Boron Phosphorus Silicate Glass flow (850Vis-cosity ) . Oxide Film B,P .

BPT (Bond Pull Test)

bondability GRAM weight gauge ball stitch bond .

Bread Board

IC IC IC

Break-Down

PN Breakdown . , avalanche br eakdown zener breakdown .

Breakdown Voltage

P-N Diode Breakd own .

Break-Up Bridging

Half Cutting Wafer Full Cutting .

.

Broken () Wafer Quartzware .

BT Stress (Bias & Temperature Stress)

Bias() Stress .

BT Test (Bias and Temperature Test) Bubbler

TR, Diode Bias .

(D-I Water) Wafer .

Bubbler Memory Buffer

, .

.

Buried Layer

TransistorCollector Collector .

Buried Via Hole

Burr

. Trim Lead .

(85 ~ 125) Device Stress Test , IC (Reliability) , Pa rameter Over Stress Test.

Burn in

Burner Burnt

.

Burn-in Device Stress High Current Device Device .

BVcob (Collector-Base Breakdown Voltage with Emitter Open)

Open - , Collector Base Breakdown .

BVcer (Collector-Base Breakdown Voltage with Specified Resistance)

- .

BVces (Collector-Emitter Breakdown Voltage with Emitter Short-Circuited to base)- Short - .

BVcev (Collector-Emitter Voltage with Specified Reverse Voltage Between Emitter And base)- - .

BVebo (Emitter-Base Breakdown Voltage with Collector Open)Collector open -

CCache DRAMCache ( data buffer ) SRAM Regist DRAM , DRAM SRAM . Main Memory CPU .

CAD(Computer Aided Design)

( ). IC, LSI LSI computer , Simulation, , Device, , , Mask Pattern, Test Pattern Step CAD . .

CAD Software

CAD Program .

CAE(computer aided engineering)

CAD System ( (Simulation) Tools). CAD , CAD Computer CAE simulation , CAE CADCAM En gineering .

CAM(Computer Aided Manufacturing)

, CAD system NC(Numerical Control: ) . Computer LSI LSI , CAM . CAD Master data test data Process data . CAD CAM Computer s ystem CAD/CAM .

Capacitance

.

MOS . , , , MOS , silicon , , .

Capatiance Voltage Characteris

Capacitor Capillary

()

Wire Bonding Chip Lead Frame Load Wire .

Capture Center Carrier Carrier

.

(, )

Wafer 25 . (Blue Carrier), (Black Carrier), (White Carrier), (Metal Carrier) . 1) Blue Carrier : Poly Propylene , 2) White Carrier : Teflon , .

Carrier Generation

carrier .

Valence Electron Conduction Band Electron Hole Carrier Generation.

Carrier Handler Cart

Wafer .

Wafer strage box .

Cascade

3 (DIW) Wafer .

CAT(Category) Cavity

Bin .

PKG PKG .

Cavitation

pump , , .

CBIC (Cell Based IC)

MASK CAD S/W Library .

CBR (CAS Before RAS)

RAS Low CAS Low Refresh .

CC (LIM Central Controller)

STC stocker cassette .

C&C (Computer and Communications) .

CCD (Charge Coupled Device)

(). . ( ) 2 . () .

CCM(Cell Control Manager)

Factory Automation System Host Level program() .

CCST (Constant Current Stress Time)

Dielectric Film Life Time TDDB(Time Dependent Dielectric Breakdown) . CCST 100 Plate Poly Dielectric Film Breakdown

.

CD (Critical Dimension)

. 1) ADI(After Develop Inspection) : Wafer . 2) ACI(After Clean Inspection) : Wafer Strip .

CD-ROM (Compact Disk Read Only Memory) CDI (Collector Diffusion Isolation) Cell

CD() Disk.

IC .

RAM ROM IC Transistor, Capacitor, Resistor 1Bit .

Cell Boundaries

. . data .

Cell Deviations(d)

, , A data . A Xm . . Xm=A d=0. A "+", A "-" .

Cell GAP Cell IMP

LCD , .

Mask ROM Bit Implant . P-Well Boron TR compe nsate .

Cell Interval(i) Cell Library

(). .

function primitive cellNAND, NOR, XOR Cell Logic sy-mbol, Electrical dat a Layout .

Cell Midpoint(Xm)

, . .

Ceramic

.

Cer-DIP(Ceramic Dual In-Line Package)

Ceramic Lead PKG.

Certification

.

Centeral Line

. .

Chance Cause(Random Causes)

, , , .

Chance Variation (Random Variation) .

Channel

MOS Transistor Gate . P-Channel, NChannel .

, . Test Time Data .

Characterization Testing

Charge

Charge Coupled Device(CCD) .

Chip

( 0.5~ 10mm) (Die ). , , .

Chip Select Chip-Set

LSI LSI .

System component(TTL, Contro-ller, PLL) Chip . chipset system solution software .

Chiral

.

. cholestric .

Chiral Nematic Phase

Chiral Pitch

. .

Chokralsky Method

Chokralsky . Chromaticity( ) , , 3 , .

Chrome Mask Chuck

Mask chrome() Mask.

, Wafer Test Wafer Prober .

Chuck Table

Wafer .( )

CIM(Computer Integrated Manufacturing)

, , . , , , Computer .

Clad

(Base Material) .

Clamp Pressure

, . Clean Class () Particle . 1M DRAM 0.1m Particle . 0.5m Particle .

Cleaning

Wafer Carrier (D.I Water) .

Clean Paper

. Clean Room() , Particle .

Hole.

Clearance Hole

Clinched Lead

.

Clock Pulse

1 AND Clock Pulse .

. .

Cluster

C-MOS

(Complementary Metal Oxide Semiconductor) N Channel, P Channel MOS Transistor Noise Margin . CMOS Logic TTL CMOS Logic IC Family, Family NAND NOR Gate, Filp-Flop , Bipolar Logic IC CMOS Logic .

MOS

Clocked CMOS, CMOS. C-MOS LOT .

CMS(Central Monitoring System) .

Coating

, Wafer ().

COB(Chip on Board)

PCB Board Die .

Cob(Collector Capacitance) Bubbler

Collector-Base PN .

Wafer .

Co-Processor

Main processor instruction . Main processor , floating-p oint math-co-processor, graphic graphic coprocessor .

CODEC (Coder and Decodr) COG (Chip On Glass)

ADC DAC one chip IC.

, , .

Cold Solder Joint

.

Cold Test

(-18 )

Collector Collet

Transistor .

Chip Lead Fram Expanding Tape Chip Lead Frame .

Column

, . Column Fail Device Test Y Address, X Address Cell Fail . Combinational Circuit () NAND, NOR Digital

Common

.(Ground)

Comparator

, TTL Logic IC . Complementary Circuit ( ) TR .

.

Compound

Compound Semiconductor . Component () . . Component Density ( ) .

Component Pin ) . Component Side () .

Compound Device. Compressor .

2 .

Computer Network

. 1 . Condenser() 2 .

. Y Y-G-jB G . . Conduction Band () , . Conductivity ( ) . Conductor () ( 10E 6 ~ 4cm ) Conductor Side () . Conductor Spacing () .

Conductance

Contact (TEST)

Continuity Test , tester interface device . Test IC pin protection diode . Contact Potentia () .

Contrast Ratio

. . Concuctor Width () .

Conformal Coating Confounding

.

, block () . Connector Area () .

Console

() .

Contact Resistence

Metal Wafer . Contact Spacing () .

Contact Spiking

AI P/N Alloy Junction Junction Spike Alloy .

Contamination.

.

Control Chart

Control Chart-Standard given

.

Control Gate

2 Polysilicon Stacked Structure Non-Valatile Momory Gate , Electrode Bias Program Erase .

Control Limit

. data

Continuous Sampling Plan

Sampling. , sampling sampling .

Conventional Memory

DOS Memory 640KB Base Memory . Expan ded Memory Extended Memory .

Converter

. .

Cooker Test

TR, Diode, IC .

Coplanar Structure Core

.

Embedded IC Micro-Operation ALU CPU Block (Peripherals) Core .

. Corrosion() AL Etchant Gas Al2O2 Metal Cosmetic Appearance() A Instrum ent panel , E (car-audio), B Game . Convalent Bond() . .

Correlation

Cooling Wafer (CW)

CPO (Customer Product Operation)

Device Test Customer Special Spec .

CPU (Central Processing Unit)

Computer , .

CPU Core

LSI Microprocessmicrocon- troller, standard cell SOG Gate Array library , user system ASIC Micon

1chip

Crack

. , stress Chip, PKG .

Cradle

Chip Mount , .

Crazing

.

Critical Energy

Ion Beam Energy mask Implant Energy . Cross Section() Layer Pattern Layer .

Cross Talk

.

Cross-over Crow Feet

IC .

Wafer .

Crystal Osillator

.

LCD

CTN(Complementary TN)

CUM Graph(Cumulative Graph)

data data data . Water die data Die (element) Data (Wafer) .

Cumulative Frequency Distribution Cure

. .

, PKG .

Custom IC.

IC.

Customer Layer

ASIC process gate array base array process user gate process .

. Cut Stroke .

CUT-OFF Frequency

CV(Cleaning Vacuum) CV(Count Variance).

.

CVD (Chemical Vaper Desposition)

APCVD, LPCVD Nitride, PSG, BPSG, LTO .

Wafer

Poly

C-V Plot (Capacitance Versus Voltage Plot)

Wafer , (, , , ) .

.

CVST (Constant Voltage Stress Time)

Cycle

Function Test Device .

Cycle Time

.

CRT(Cathode-Ray Tube) Cryo-Pump

.

Gas .

CQ(Conditional Qualification) .

CTE(Coefficient of Thermal Expansion) .

Hepa Filter Clean Room A Class . 0.3m/s 700/h. Granting Down Flow Clean , Hepa Box

CTM(Clean Tunnel Module)

.

, .

CTS(Computerized Typesetting System)

CU(Control Unit) Culvert

Timing. .

, .

DD(Demerit)Quality score . D-A (Digital to Analog Converter) Analog .

DA(Die Attach)

Die Lead Frame

DAC(Digitaaal to Analog Converter)

Digital Analog . Hi-Fi CD player 16bit D/A convertor .

D.C Characteristic

DeviceStatus Current , Device Status .

DAD(Digital Audio Disk)

Disk .

DAE(Dynamics Asian Economies)

, , , .

Daisy Chain Dambar

LSI

PKG Lead Bar. Dark Current() .

D.A.T.A

Derivation And Tabulation Associates Inc. .

Data Line

on-off .

Data Retention Mode

(DRAM/SRAM) power-off battery back-up circuit

DC(direct Current) DC Characteristic

.

Device Status current , DeviceStatus .

DC Parametic Testing

Steady state test OHM . / / . DC test (ICC), (leakage test), (VIL,VIH), (VOL,VOH) .

DC PDP (Direct Current Plasma Display Panel)

(lonized Neon-Argon Gas , .

DCW (Dry Cooling Water) DD (Double Die) Die.

FAB Cooling Coal .

Debug

, . Debugging, Screening, BURN-IN .

Debugging

Test Plan .

Decay Time

100% 10% .

Decel Mode Decoder

lon ( 0-33kev)

2 (Decode) (10 ) 2-10 Decoder . Encoder Defect () product service

. defect . 1) Class 1 : . 2) Class 2 : . 3) Class 3 : . 4) Class 4 : .

Deflash

Compound . Defocus ( ) (P/R) . Delamiantion () .

Delay Time

TR Switching () 10% .

Demo

Wafer .

data () control .

Demutiplexer

Dent

.

Depletion Device

MOS FET Gate Channel . Depletion Layer() PN P HoleN . .

Depletion Mode Depletion Type

TR Bias .

Channeldeplete . channel .

Deposition

CVD , Si Film() (Oxide, Nitride) .

strip back defect site .

Deprocess

Descum

(scum) .

Design Kit

Electrical/Physical ASIC modeling layout database Electricla Design Kit . (: Mentor Design Kit, Verilog Design Kit)

.

Design Rule

Develop

Mask Align expose Pattern .

Development

. Pattern .

Device

()() Dextrotatory ( ) .

Dewetting

.

DF (Die Fabrication)

Wafer mount dicing saw .

Dichronmated Gelatin

Dichomated gelatin .

Dicing

Wafer ( )

Dicing Saw Die Attach

Wafer Die (Chip) diamond wheel.

Die Lead Frame .

Die Business

Probe Test package Good Die wafer wafer Good Die .

Die Bonder

(chip) , IC .

Die Bonding

IC Chip . , .

Die Coating Die Collet

Die .

Die Die . .

Die Pocket

Die . .

Die Sawing

Wafer chip . Dielectric Constant() .

Dieletric Isolation

IC Electrical . (), Poly-Si, Ce-ramic .

Diffused Resistor Diffusion

diffusion .

(Wafer) B (boron;) P(Phosporous;) .

Diffusion Capacitance Diffusion Current

Diffusion Junction Capacitor .

E-filed/ Current Carrier .

Diffusion Furnace

Diffusion Length

Carrier Carrier Carrier . Life Time Carrier diffusion length .

Diffusion Pump Diffusivity

gas .

.

Digital(DIC) Digital IC

Analog "1" "0" (Digital IC)

"1" "0" digital IC, MOS IC Bipolar digital I C , logic IC Memory IC . ,, .

Digitizing

Mask . Dimenrization() .

Dimension

DIMM(Dual In-Line Memory Module)

PC Memory module PCB pin .

Dimple

Wafer . Dimentional Stability( ) , , , . Dimentioned Hole () .

DIN

Deionized Water .

Diode

di-electrode 2 . 2 , , .

Diode Array

.

Diode Ring Structure

.

DIP(Dual Inline Package)

IC , (Chip) .

Discolor Discrete

Wafer FAB Pad .

(IC) . TR, Diode, , Discrete .

Discretional Array Method

LSI 10 100 (Cell Unit Cell ) Cell .

Discrete Device

, Transistor , Diode .

Discrete Product

Diode, Transistor, (Rectifier), (Thyristor) , .

Discretion Wiring-Approach

Wafer , Wafer Patt ern LSI .

Display Device

, .

DIW (Deionized Wafer)

, Wet . D-I Water (De Ionized Water Semiconductor grede Water) , Wafer .

DLM

2 Metal Layer . 1 power routing line 2 rounting line .

D-MOS(Double DiffusionMetal Oxide Semiconductor) channel length , MO S .

DMA (Direct Memory Access)

CPU data DMAC(8237A) DM A data .

Domain

cell .

Donor

N-type P, As, Sb .

N donor . (Forebidden band) level Donor Level .

Donor level

Dope

(, ION IMP-LANTATION ) .

Dopant Doping

Dope .

(Wafer) P-type N-type .

Dope Oxide Dosage Dose

Doping layer Oxide.

.

lon lmplantation dose , .

Dot-Clock Signal

.

DPLL(Dull Phase Locked Loop)

PLL 2 PLL PLL DPLL , Digital PLL .

DRAM(Dynamic Random Access Memory)

Capacitor Cell device CAP Charge Refresh Cycl e . Refresh RAM (capacitor) , Memory leak , Refresh . DRAM SRAM memory cell memory .

Drain

TR(FET) , . TR, TR .

DRC/ERC/LVS

DVP-Circuit Layout Design Rule, . 1) DRC(Design Rule Check) ; Layout Data (Metal , ) Check 2) ERC(Electrical Rule Check) ; Check. 3) LVS(Layout vs Schematic) ; Layout Data Circuit .

Dressing Drift

Wafer (Blade) Dressing .

"0" .

Drift Current

Extrinsic Semiconductor E-Filed Current Carrier Drift Velocity v=E (:M oblity, E:Electric Filed) .

Drive-In

Deposition B() P()DMF wafer (Furnace) .

Driver

Device , .

Driving Fregurncy Driving Voitage

.

.

DRO(Destructive Read-Out)

. . Dross() .

DRT(Device Reliability Test) Dry Etch

" " (Quality Approval Test) .

, Gas(Plasma) .

Dry Process

TR, IC beam .

DST(Die Share Test)

Die Die Attach Die Frame pad .

DT(Down Time) Dummy Wafer

.

Tube Uniformity Wafer Wafer Wafer Wafer

Dumping-ZIG

Carrier wafer carrier .

DUT(Device Under Test) Duty Cycle

. test , DUT Board .

refresh rate 60Hz .

Duty Ratio

. Dyed Polyimides (polyimide) .

Dynamic Shift Register Dynamic RAM

MOS Shif Register .

(Dynamic Random Access Memory; DRAM) "1" "0" . Dynamic Scatting Mode ( ) . . .

Dynascope

Wafer 0.1mm . ( ) , , .

DW(Diffused Wafer)

EE/Post SimulationSimulation layout esti-mated wire capacitance Pre Simulation la yout actual wire capacitance Post Simu-lation .

EA (Exhaust Air)

GAS , , , , , .

EAROM (Electrically Alterable ROM) EBE (Electron-Beam Evaporation) EBR (Edge Bead Removal)

EPROM .

Beam Wafer() .

Wafer particle .

ECC (Error Check & Correction)

ROM device repair column row program RAM Redency . logic column row fail column row . MASK ROM DRAM Module .

ECC

(Error Correction Code)(Error Checking Code) , .

ECC Mode (Error Catch & Correction Mode)

Memory Module Parity Bit 2Bit Error Memory Module .

ECL (Emitter Coupled Logic)

CML(Current Moded Logic) . Bipolar Transistor () . Transistor Emitter Emitter Coupled Logic .

Edge Board Connector Edge Board Connector

.

.

Edge Definition ()

film .

E/D MOS (Enhancement-Depletion MOS) ED (Electronic Data Interchange) Editing

Enhancement MOS Depletion MOS .

CAD System CRT Layout .

EDO (Extened Data Output)

DRAM data access fast page mode /CAS signal inactive high valid data /CAS signal low active data . fast PAGE MODE TPC(fast page mode cycle) speed . .

EDS

Wafer .

EDS Test

Wafer (chip) .

EDS Yield

EDS test : (Good Die / Net Die)100

EECA

(European Electronic Component Manufactures Association) .

E-E PROM(Electrically-Erasable PROM)

off data . Parallel data Intel Type Seria l data NEC Type . Tunneling Erase Programming In-System 2 Transistor 1 cell EPROM .

Elght Nines

9 8 . 99.999999% .

MOS Source Drain cha-nnel Gate length . EL ()(ELECTRO-LUMINECENCE) . 1936 DESTRIAU 2 .

Effective Channel Length

ELD (Electro Luminescent Display)

PDP COLOR .

ELD

.

Electroless Deposition ( ) .

Electrical Test

Process Wafer Passivation Test Pattern Test Test (, wafer mapping)

Electron Beam Exposure System

Beam mask pattern system, mask pattern pattern pattern generator , , . LSI pattern data algorithm , EBMT( tape) Beam on/off, aperture pattern . ASIC sample needs . mask wafer Beam . Element () .

Ellipsometer

Thin Film (Polarization) . Electron Beam Exposure ( ) () photolithography .

EM (Electromigration) Emitter EMM

Metal Quality .

NPN,PNP Transistor .

(Emission Microscope Multilayer Inspection) Electron Hole recombination photon leakage current FA .

Emulsion Mask Encoder

Mask , Emulsion() Mask.

Decoder . (10 2 )

End Point Detection

Etch Wafer plasma Etch stop reference .

End Seal

LCD

End Station Endurance

lon wafer .

data program erase .

Energy Band

Energy .

Energy Gap

energy gapdlfkrh .

. . .

Energy Level

Enhancement Device Enhancement Mode

Gate Channel MOSFET.

TR (FET) Gate bias . Entity () .

EOH (Ending on Hand) EOP (End Of Point) EOTC

( ).

plasma .

(European Organization on Testing and Certification)

EPD (Etch Pit Density)

Etch Pit . End Point Detect Etch Etch Etch .

Epi (Epitaxial Layer)

. Bipolar Transistor

Epitaxial Layer .

Epitaxial

EPI-TAXIAL " " . Substrate Substrate . Epitaxial-Growth () Substrate .

EPM (Electric Parameter Monitor)

test pattern , .

EPM Standard Sub Program Epoxy

EPM .

Chip lead frame .

Epoxy Dispenser EPROM

Epoxy

(Erasable Programmable Read Only Memory) ROM . programm- able ROM, Program IC Package glass . bit .

EPS(Experimental Plan Sheet) Equip(Equipment).

S/N RUN SPLIT

Erase

EPROM EEPRO Floating Gate Tunneling Bit . EPROM Floating Gata discharge EEPROM Floating Gate .

Erase Gate

Erase Gate 3Polysilicon Split Gate Flash E(E)PROM Erase Gate Electrode.

ERC(Electrical Rule Check) ERC(Electrical Rule Check)

check .

Layout , .

ESD(Electro Static Discharge)

ET Part(Extended Temperature Part)

Memory Device 0 ~ 70 Device 40 ~ 85 .

Etch Back

, .

Etch Bias Etching

Photo etch pattern .

. Silicon wafer chemical gas . Etching Selectivity( ) SX (plasma) .

Etch Factor Etch Rate

.

. A/min .

E-Test (Electrical Test)

Process Wafer Passivation Test Pattern Test Test.

Evaporation Evaporator Event

Wafer AI, Au() .

beam wafer .

Evtity Start, End, Maintenance .

Evolutionary Operation(EVOP)

. .

EWS(Engineering Work Station)

CAD Design Tool system system. Excess Electron ()

. Excite () . pumping .

Exclusive Effect

2 . . , .

Exclusive or Circuit

"1"', "0" "1" .

Exoending Tape

Wafer 360 tape. Expose() P/R wafer pattern aligner .

External Visual Inspection Exposure

.

, WF mask . mask p attern .

Extraction Voltage

Lon Source lon Beam .

Extrinsic Semiconductor

(lntrinsic Semiconductor) (3, 5 )

Eylet

.

FFAB (Fablication) FAB ProcessWafer .

Wafer diffusion, thin film, photo, etch .

Factor

, .

Fail Memory

Device Function Test Device Device

Falg

. . tag . Fail Time() TR off collector on 90% 10% .

Fan coil unit

coil .

Fan Out Capability Fan-In

Device data current drive .

.

Fan-Out Farad

.

. 1F 1 volt/sec 1A .

Simulation simulation vector % access output simulation vector .

Fault Coverage

FCU (Fan Coil Unit)

, .

FDM (function data module) Fermi Energy

(function data) module.

energy energy . energy - . 1/2 F . FET ( Transistor:Field Effect Transistor)

carrier () Transistor. carrier Bipolar Unipola() Transistor . FFU () Fan Filter Unit . fanfilter filter fan clean

Field oxide

active active .

FIL (Filament) Fill Factor

.

Filter () Final test (/Class Test) .

Finder Coat

Wafer .

Fire Damper (F.D)

Duct damper 70 fuse damper.

Film Ware

software ROM . First Acticle () .

First Minimum Fixture

Gooch & Terry 0 .

.

Fixed Oxide Charge (Qf) Flat Pack

Oxidation , , Cooling silicon Oxide charge.

IC .

Flat-Zone Aligner

carrier loading wafer(flat-zone) .

EPROM EEPROM EPROM EEPROM , EPROM, EPROM . Memory Device block . flash memory NOR, NAND NOR EEPROM Hot Electron , NAND . . Memory har d disk . Flat Zone ( ) Wafer cut .

Flash EEPROM

FLC

. . .

Flexible Strength,

Flip-Flop

2 (on off) .

.

Flicker

Floating Gata

MOS TR Floating Gate .

Floor plan

chip layout block layout layout block .

Flux

.

Forbidden Band () . .

Forming Die

Forming I.C. ead frame lead frame .

Forming Gas

1) Die Attach wire bonding H2 N2

Gas. 2) FAB(, ) Gas. Forward () PN P +, N . Forward Current ( ) PN . Forward Voltage ( ) PN PN . Four Layer Diode (4 Diode) PNPN 4 Diode.

Four-Point Probe

sheet .

FOX (Fast Oxidation)

(0~25) Hipox . (High Pressure oxida tion)

FPGA (Filed Programmable Gate Array)

program chip CAD .

FPO (Finish Process Order)

lot lot 1 lot flow , lot FPO lot . .

FQ (Full Qualification) FR (Failure Rate)

Customer .

" " .

FRAM (Ferroelectric RAM)

. , memory cell RAM SRAM DRAM data . EEPROM data .

Reticle/mask Alignment PatternProcess item Sawing Scribe line Alig nment . Scibe li ne Align key Process inspection Pattern .

Frame

Frame Ring

Wafer tape . Free Election ()

Freon

.

Freedericks () . Hc .

From/To chat

Inter-bay intra-bay simulation chart.

FSTN(Film Super Twist Nematic)

DSTN . FSTN DSTN .

FTA (Fixed To Attempt Ratio)

Wafer repairable fuse cutting .

Full-Auto

host AGV CST LOAD/UNLOAD . Full Custom Tool Chip IC. MOS tran-sistor level . Simulation, opti-mization Chip Area layout .

Full Cutting

, (tape cutting) Wafer (95~100%) .

Function Test.

Device Formater Device .

F.W.W(Flouric Waste Water)

.

GGaAs(Gallium Arsenide)

, silicon . III-V Si 5~6 , device . UHF SHF GaAs FET, micro anlog IC, Diode, laser, .

Gas Scrubber Gate

gas .

transistor , 2 MOS transistor bipolar transistor base .

Gate Array

NOT-Gate, AND-Gate, OR-Gate, NOR-Gate, NAND-Gate Transistor logic . semi-custom digital IC. cell master wafer user Timing Chart Data CAD . Gate Type Chip Gate Gate SOG(Sea o f Gate) G/A .

Gate oxide Gel

TR 2 , insulator , MOS TRGate

.

Gettering

, , Si-SiO2 .

GIDL (Gate Induced Drain Leakage)

Gate oxide breakdown voltage drain substrate leakage current gate drain field drain deep depletion band , ba nd tunneling drain junction inpact ionization EHP drain hole substra te leakage current .

Glass Substrate

. .

Gm (Transconduction)

Gate Source Drain . = Bipolar TR ()

GN2 (General N2)

N2. Purge .

GO/NO GO TEST

(pass) (fail) (GO), (NO-GO) . Wafer Die Package Device / Test . Test Program Program.

GOI (Gate Oxide Integrity)

Gate Oxide . (BV,) . GOI System In-Line Diffusion Oxidation Tube, Recipe, W/S Electrical Stress Test .

Grade Junction

PN P N . P N P N .

Grating

Clean Down Flow Lamimar Unit floor . Ac cess Floor . . Aluminum . . Grain () . Ground Gate ( ) TR(FET) 3 Gate (Common Gate) . .

PNPTR P N , P . P . BAND GUARD .

Guard Ring

Guard Rings

CMOS Latch-up Pattern Ring .

Guest-Host Effect

. . , .

H

H.A.L(Host Solder Air Leveling)P.C.B .

Handler

Package Ttest Test system(Tester) .

Half Cutting Halide

Wafer 70 ~ 80 % .

2 . .

Hard Fail

defect .

HCT (High Speed C-MOS TTL)

C-MOS TTL LSTTL ( ) Computer computer CPU, Menory, IC . Heat Sink Plane () .

HEMT (High Electron Mobility Transistor)

Transistor , GaAs , FET GaAs undoped GaAs, N AIGaAs , AIGaAs Channel .

Hepa Box

Clean Room Hepa Filter Box.

HEPA Filter (High Efficiency Particulate Air Filter)

Clean Room Filter . (0.1m - 99.9995 %)

Hetero Junction

P N PN Junction . P N . 2 HETERO Juction .

High Power Inspection Hfe(DC Current Gain)

Wafer Die

Emitter .

Hierarchy

LSI Design Design .

High Pressure Cleaner Hillock

Wafer CO2 D-I Water .

. HMDS(Hexa Methyl Di Silazane ) Wafer Wafer Primer() .

H-MOS(High-performance MOS)

MOS IC N-NOS MOS.

Hold Time

data tCAH(Column Address Hold Time) tRAH(Row Addres s Hold Time), tDH (Data Hold Tome) .

Hole

. .

HOPL(High Temperature Operating Life Test)

" " 125 Oven 7.5(V) Bias, 1000 " " .

Hot DI water Hot Run

DI water(85), Wafer .

RUN(lot) RUN . Normal RUN RUN.

Hot Test

Test .

Hot Electron

. ( ) . . Hot Electron .

HP4145

Wafer level DC Graphic Bench Test T ool.

H/S (Heat Sink)

. PKG .

HTO (High Temperature Oxidation)

. . (900) Si Wafer , Si Wafer SIO2 .

HTRB (High Temperature Reverse Biase) HTS (High Temperature Storage)

" Bias" Device Bias Oven .

" " (125) Oven Device .

HVAC (Heating Ventilation and Air Conditioning) Hybrid-Circuit Hybrid I.C

, () .

, , . (THIN FILM) (THICK FILM) I.C , I.C . IC ,, , .

II-line stepper 365 nm

IC (Integrated Circuit)

2 , , .

IC Memory

TR MOS F-F Memory(cell) IC. IC Tester ( ) IC . ATE (Automatic Test Equipment) .

Ids

MOS TR Source Drain .

Ie (Emitter Current)

IEC (Integrated Equipment Computer)

.

(Integrated Injection Logic) Bipolar Transistor PNP Tr-ansistor NPN Transistor . Bipolar Logic IC . PNP Transistor NPN Transistor N P . Gate . Analog. Digital Bipolar IC Digital . (Isoplanar Integrated Injection Logic) .

ILT (Infant Life Test)

() 48. Burn-In . Image Sticking() ghost .

Impact Ionization

Electric Field Electron Atom Electronhole Pair . Implanter( ) wafer , , 3 . Implanting () wafer B() P() Implanter .

Impurity

, P N . P: B, AI, Ga, In N: P, As, Sb

Index Feeding

Lead Frame .

Index Register

Address Register.

Induced Cholesteric Phase

. .

, .

Induced Smectic Phase

Indum arsenide Initial Oxide

InAs, III-V .

Si Nitride Tensite Stress(1109 Dyne/cm2) , Buffered Oxide . , Oxide Bird's Beak . Injection() PN .

Ink

.

Inker

Wafer Ink .

Inking

Package Package Wafer Inking .

Inorganic Filter

.

Input Buffer Input Level Insulator

Signal voltage level .

Device De-vice (High, Low) .

.

Inter-bay Interface

Bay Bay Clean Way (AGV, Track) .

Amp Computer . Inter Metallic Compound( ) .

Intra-bay Intrinsic

Bay AGV Track .

P N , P N .

Inversion

MOS FET Gate PN Type NP Type . Inversion Wall() . , . Inverted Staggered() source .

Inverter

Digital Circuit 10 01 .

Optic, X-ray, electron beam Lithography . Ion Implantation .

Ion Beam Lithography

Ion Injection

Silicon lon . Ion Shell () .

IPA (Iso Propy Alcohol) IPO (Inter Poly Oxide) ISO-Planar Isolation

.

Poly Si Poly Si Oxide.

Planar .

Chip TR, Diode Isolation .

Isolation Diffusion

N Epi P Sub-strate . Epi .

Isotropic Etching

. () . Isotrophic Phase ()

. ..

Isolation in IC Isotropic

.

ITO(Indium Tin Oxide)

. (In2O3, SnO2) .

JJ-FET(Junction FET)Depletion Mode Source-Drain lon Gate Gate Drain FET(Filed Effect Transistor) .

Jig

.

Junction

. Junction Depth (Xj) Silicon Diffused layer background .

Junction Diode

PN Diode Junction Transistor ( TR) 3 ( PNP NPN) TR.

Junction Spiking Jungle-Box

Metal-Silicon contact Metal Silicon

Gas Gas Flow Meter(MFC) GAS .

K

Kerf

(). Blade .

Keying Slot

.

LLabelling() Wafer RUN Tube Diamond pen .

Laminar Flow Station Laser Diode

Filter .

PN . PN .

Laser Interference Method

Etch Wafer Laser .

Laser Repair

Data ( ) laser data( ) .

Laser Scriber Laser Test Lasera Latch

Wafer Die .

Yield Fuse Laser

.

Latch Up

CMOS , ionizing redation Turn on .

Layer

IC Si-Wafer (Insulator, Conductor) Photo/Etch Pattern .

Layout Plot

Layout Hard Copy CMOS LSI THYRISTOR TRANSISTOR IC .

L/B (Loadboard)

Test System Jig.

LC (Liquid Crystal)

. . " ".

LCD(Liquid Crystal Display)

.

LDD(Lightly Doped Drain)

Doping , Device .

LDMOS(Lateral Diffused MOS)

MOSFET Source Drain .

Lead Finshing

Lead (Tin), .

Lead Frame

TR, Diode, IC Sawing Die Attach . Alloy42 , Copper, Kovar, Steel IDF TTT .

Leak

Pin Pin .

Leak Current Leakage

.

Input tristated output open circuit high impedence . leakage voltage input triasted output current input leakage triasted leakage .

LED(Light Emission Diode)

Diode. (PN )

Legend() .

LF(Lead Frame) Library

Chip .

Gate array Standard cell .

1 , 2 Motor.

LIM(Linear Induction Motor)

Linear IC

IC , , .

LIPAS(Line Item Performance Against Schedule) . Liquid Crystal () . Liquid Phase Epitaxy () . Ga, Sn .

LN2(Liquified N2) Loader

N2 GAS, .

Stocker Station Cassette Unit.

Load Circuit

Test Device Application , Cpacitance Circui t.

Loading

Wafer Boat Tweezer . Loading Effect() Pattern Pattern .

Loading fixture

Lead Frame .

Local Oxidization of Silicon

.

silicon silicon silicon silicon . Logic Circuit() 2 , , , .

Logic Simulation

IC Functionality Logic Value .

Logic Synthesis

HDL Netlist Logic Level Schemetic . VHDL Logic .

Lot Lot

Sampling .

Wafer .

Low Power Part LP(Lens Paper)

Power Device Portable .

Lens .

LPCVD(Low Pressure CVD)

Wafer Deposition Gas .

LRR (Lot Reject Rate)

Gate Lot Reject.

LSB (Least Significant Bit) .

LSI (Large Scale Integration)

Transistor100 . LTO (Low Temperature Deposition of Oxide, ) LPCVD 400~450 .

LTS(Low Temperature Storage)

" " (-40) Oven Device . Luminerous Effciency .

.

Luminescence

LVS (Layout Versus Schematic) Lyotropic Nematic

Layout .

, .

MMacro Cell Library Core Macrocell Interface Input/Output Macrocell .

Macro Function

Macrocell Macrocell Library CAD software Library Library.

Macro Loading Effect Magazine

Wafer etch .

Lead Frame Strip Carrier . Magneto Diode ( Diode) Diode.

Main Frame

. . , , . Magnetic Ink (, ) Ink, TRIC Wafer . Majority Carrier ( ) . .

Manual Station Mask

Handler Tester .

. Mask Epitaxial Method

Mask .

Mask Layout

Mask , , , ,, , , mask .

Mask Tooling Information

Reticle/Mask Information PG Data, FramePIE Scrbe Line Align Key Information Vendor .

Master Drawing

, , , .

MBE(Molecular Beam Epitaxy) MCC(Motor Channel Center) Mcdonnell Switch

.

Motor , Panel.

. Boiler , Gas Boiler .

MCM (Multi Chip Module)

. MCM , , .

MDS (Microcontroller Development System) Measling

MICOM Program Tool.

.

Gas .

Mechanical Pump

Mega Cell

RAM,ROM Memory PC 82 Series Logic Macrocell Library.

Mega function

Megacell Library Macrofuntion CAD Library Megafunction Library Disk .

Memory IC Data . RAM SRAM, DRAM, SRAM Cell Latch , DRAM Condenser . SRAM , Access . DRAM Condenser Bit ,. . Leak Data Rewrite (Refresh) . Memory Effect .

Memory Cell

Memory module Mesogen

Memory Memory .

.

Metal Gate

(AI ) TR MOS FET MOS FET IC .

Metallization

.

MFC(Mass Flow Controller) .

Micro Bridge

Pattern Pattern Bridge Scope Current leve l Scope .

Micro IC

.

Micromulsion Mil

() .

1/1,000 Inch. 25.4m. Minority Carrier( ) .

Mis-Align

(mask) Wafer .

IC Metal 1 Layer . 2, 3 .

MLM(Multi-Layer Metal)

MMIC(Monolithic Microwave Integrated circuit)

Wafer IC Inductor, Capacitor,, Transistor .

MO Tape(MASK ORIGINAL TAPE) Mobility

Mask Data .

, , , , 10/m . .

(Metal-Organic Chemical Vaper Deposition) MOVPE Epi . Source 5 .

MOCVD

Mode

. . , , Operation .

Model Parameter

Simulation .

Module

. Module .

Molding

() . Wire Bonding () package .

Molding Compound

Wire Bonding .

Molding Die

.

Monitoring

.

Monolithic IC

1 .

MOP(Metal Oxide Passivation) .

MOS(Metal Orcide Semiconductor)

Silicon Device.

MOS FET(MOS Field Effect Transistor)

Source, Drain Gate3 Gate Source Drain Channel .

MOS IC

MOS FET IC.

Movement

Run .

MPR(Micro Peripheral)

LSI Micro Computer Microprocessor LSI .

M-Pyrol

, , .

MRB(Material Review Board)

Criteria , Stock Shut-down 24 Corrective action .

MSI(Medium Scale Integration)

100 10 Transistor .

MTO(Medium Temperature Deposition of Oxide) Multi-Processing

LPCVD 800 .

.

Multiple Diode Multiplexer

2 Diode .

() Control .

Myelin Figure Nail Heading

A 2 .N

.

Intensity .

Nano Line

Nano Spec

Wafer .

National Reference Standard Navigation TFT-LCD

2 .

LCD , .

N-Channel

P FET , .

, , lame lla .

Neat Phase

Necking

Interconnect line .

Negative LCD

Normally black .

Negative Resistance Nematic IC Net Die Netlist

.

.

Wafer Total Die.

Simulation Layout , , , Signal Name File.

Neural Processing Chip N-CH Filed Implant

Neuron Neuron IC.

Filed Region VT Cell Cell Filed Oxide ICON .

N MOS(N-channel MOS) Nodule

P Source Drain N MOS device.

, Si Si . Noise Margin( ) 1 0 level "1" "0 " . Non-Volatile( ) Memory.

Notch/Void

() . Notch , Hole Void .

Notching

Photo line .

Notebook TFT-LCD

3.5Kg PC 10 Laptop Pitch 0.21, 0. 33mm.

NPN TR

N ,P, N , , TR.

N-Type Silicon(Negative Type Silicon) NVD(Non Visual Defect)

Major Carrier Electron .

Deprocess Fail Defect Non Visual Defect .

OOA(Outside Air)AHU .

OAHU(Out Air Handing Unit) Oalemce Election

.

, .

OCD(Optically Coupled Device) .

Octal Test

Probe Test touch 8Die Probeinng 8 Die test .

OEIC(Organized design for line & Crew System)

System Layout Method Line .

One Chip CPU

1 Chip LSI . ONO Capacitor Dielectric Material Oxide/ Nitride/ Oxide 3 Pinhole Breakdown , Nitride Dielectric Constant Oxide Capacitance .

Open

.

Open Repair

TFT Arrey Panel Data Lline Gate Line line short .

Optic Emission Method

Plasma etch Optic signal .

Optical Axis

(No:ordinary) (Ne:extra ordinary) . Orientation- Film() . Oscilator() .

O/S(Open Short) .

OTP(One Time Programmable)

EPROM Device Plastic Package Erase Package Device .

Output Buffer

Sence AMP Data External Load Device Buffer.

Output Level Outgassing

Device Data (High, Low) .

Source Gas Gas Lon Beam .

Oven

Wafer .

Over Coat

(ITO) Alksli Barrir Coa t .

, .

Over Coating(Polyimide Coating)

Over Etching

End Ppint Detection Etch .

Oerlay Vernier

Wafer Wafer Pattern .

Over- flow Oxidation Oxide

.

, (650 ~ 1200 ) Wafer .

(SiO2)

Oxide Breakdown

Oxide voltage . Oxide Film() .

PP-ChannelN P FET ,

.

P & R(Placement & Rounting)

Design Automation Chip Layout Macro-Block Standard-Cell .

P/A(Process Area)

Wafer Area.

P-Type Silicon(Positive Type Silicon)Major Carrier Hole Si .

PA(Process Air) Package

Air Comp Dryer Filter Air .

TR, Diode, IC Package Mold() Type, Ceranic type, Cam() type . Type Pin Type .

Package Density

. Panel Plating() . Parasitic Effect() IC .

Passivation

, , Damage Plas ma CVD Oxide Nitride , PN , .

Pattern

.

PBH (Planer Buried Heterostructure)

(LD) , epi . PCB (Printed Circuit Board: ) , , , , TR, IC, LSI, .

PCD (Plasma Coupled Device) PCM Data

CCD Device.

RUN Data Test pattern Data.

PCM Test

Process control monitor , .

PCT(Pressure Cooker Test)

" " 15PSI, =100%, =1212 Pressure Cooker .

PCW(Process Cooling Wafer) PD(Photo Detector)

.

PIN-PD, APD .

PDP(Percent Defect Panel)

.

Plastic Package Type Package Lead Socker .

PDIP (Plastic Dual In-Line Package)

PECVD(Plasma Enhanced Chemical Vapor Deposition) Plasma . TFT-LCD Insulato r a-Si .

Pellet

Wafer .

Pelletize

compound .

Performance Board

Test System Test System Probe PCB Coaxial Cable Wiring Interface board.

Peripheral LSI

Test system CPU LSI.

PG(Pattern Generator)

CAD System Digitizing Mask Pattern Reticle .

PG(Pattern Generation)

Pattern Layout Reticle/Mask Data .

PG Tape

Layout Data Reticle/Mask E-Beam Machine Format

Data PG data Tape .

PGA(Pin Grid Array)

LeadPackage . Phase() 1 . Photo Conductive Effect() .

Photo Diode

PN PN . Photo Etching( ) .

Photo-Resist

Positive Negativ e 2 .

Photo-Resist or Resist

Positive Negative . Photo Volatic Effect( ) PN PN .

PI(Process Integration)

Photo, Etch, Diffusion, Thin Film, Ion Implantation Process Flow . Piezo Electric Effect() .

Pin Hole

Mask WF Pattern . .

Pit

. Pixel() "Picture Element" R,G,B 3 1 .

Pixel Defect

LCD .

PLA(Programmable Logic Array)

Program . Planner. FAB Silicon .

Planar Transistor Plasma

FAB Silicon Chip .

.

Plasma Display

.

Plasma Etching

Gas Energy , , , , , .

Plating.

PLCC(Plastic Leaded Chip Carrier) Plenum

Package lead 4 .

.

.

PLL(Phase Locked Loop)

P-MOS

Channel MOS Transistor.

P-N Junction

P-N Junction P N . Junction (rectifier) Diode .

PNPN Diode

PNPN 4 Diode.

PNP Type Transistor

PNP P, N, P , , TR .

, 2 PVA TAC(Tri Acetyl Cellul ose) . Poly-Crystal() . Poly-Crystal Silicon( ) . .

Polarizer

, . .

Poly-Si

Polyimide Polymer

Rubbing .

. (Monomer) .

Positive LCD Post Burn-in

LCD Normally White .

Burn-in .

Post Laser Repair Test

Laser Repair Wafer Chip Pass/Fail Laser Repair .

Pot

.

Power Regulator

Bipolar IC IC Linear IC .

Pattern . Pattern . Pre Burn-in Burn-in .

PR(Photo Resist)

Predipitate

( ), FAB .

Preform Feeder

Preform Lead Frame .

Pretilt Angle Probe Card

.

Wafer Chip Probe Tip .

Prober

Test Wafer X, Y, Z ROOM/HOT Wafer Point Test .

Probing

PAD Probe Tip Contact .

Process Minispec.

base line FAB SPEC ,, .

Profile

.

Proximity Effect

Pattern Etch .

PRT(Production Realiability Test) PSG(Phospho-Silicate-Glass)

.

. Phosphorous Reflow .

P/S(Prober Station)

Wafer

PSRAM(pseudo SRAM)

DRAM SRAM Refresh DRAM SRAM .

P-Type

N-Type 3 .

.

P type semiconductor

Punch-Through Breakdown

Source/Drain Junction depletion region Breakdown Substrate , Short Channel Junction Depletion Source-Dain .

PV(Process Vacuum)

Pump . .

PVD(Physical Vapour Deposition) PW(Polished Wafer) .

CVD , .

PWL(Pulsed Word Line)

ICC Reading Word Line Signal Pulse Control Circuit .

QQDR(Quick Drain Rinse)DI Rinse Cycle Sho-wer Drain Cleaning .

QFP(Quad Flat Package) Quartz Boat

Lead Package Lead .

Wafer , . Quartzware() Furnace N/C Chamber .

Q-tip

. Cleaning .

QTL(Q8K Test Language) Qual(qualification)

Q8K Test System PGM language.

Test .

Elec tronics .

Quantum Electrnics

QV (Quality Validation)

Test QA , ,Test .

RR/A(Return Air) Rack .

. .

Ram Height

.

Rambus DRAM

Rambus DRAM. Data 500MHz data bus .

RAMDAC

Pixel Address RAM DAC R.G.B Analog Chip.

Raster

CRT .

Recipe

Material Process Rule Control data .

Rectifier

Diode .

, . . Rectifying Action() .

Recombination

Redundancy

Cell Chip .

Redundancy

Chip Cell Defect Cell Cell .

Reference Check

Device System Check . Reflectance() Film .

Reflective Display Refresh

Backlight Display.

DRAM MOS FET WRITE-IN REFRESH .

Reject

Wafer Mask .

Reliability

.

Repairable

Memory Chip Fall Bit Redundancy Fail Cell Spare Cell Repairable . Wafer Test Row Column Cell Row Column . Repeating Defect() Wafer .

.

Resin Recession

Resisstor Retilcle

Mask Chip 10 Mask Master Mask .

Resistration

.

Response time Retest

.

System Align Test Wafer Test .

Reticle

Mask .(Stepper Mask) Wafer Pattern () () Wafer .

Reverse Tilt

.

Reverse Twist

, .

RF(Radio Frequency)

, Gas , .

RIE(Reactive lon Etching)

. Plasma etching Ion .

Ring Oscillator Rinse

Library .

(DI Water) Wafer . Rise Time() TR Collector () 10% 90% .

Room Temperature Test .

ROR(Ras Only Refresh) Round Cut Routing

RAS Low Refresh .

Wafer Wafer .

PCB . PCB Drill PCB . Row Fail Device Test X address, Y address cell fail .

R.S(Resistivity)

.

RTI(read time inspection)

FQA Sampling .

RTV(Room Temperature Vulanizing)

. 25, 60% .

Rubbing

.

Run Split

Run , Run Wafer , .

RZ(Return to Zero)

Pattern Data "1" "0" Palse .

SS/A(Service Area) Mainternance Area 1M-DRAM CALSS 100. Salt Spray " " =35, 5% Device Lead Frame Check .

Sawing

Wafer 1/1000 Wafer X,Y .

S/C(Solder Coating)

I.C lead lead .

Scanner

Beam line lon Beam Beam .

Scanning Trigger Circuit

Feedbac k .

Schematic

. Simulator Text Netlist .

Schottky Barrier Schottky Diode

.

, P-N Diode.

Schottky gate fet SCP

FET Gate , Schottky FET.

Gate PNPN .

Scramble Scratch

Device Pin Test .

, .

Screening

DEBUG, BURN-IN LOT .

Scibe

Wafer Chip .

Die Sawing .

Scibe line

Scribing

, Wafer ( , )

Scrubber Scum

Wafer .

Wafer .

SDA(Statistical Dafect Analysis)

Process Wafer Fail(Row, Column, Bit fail) Feedback Data.

SDRAM(Synchronous DRAM)

System Clock Data 10ns Access Time DRAM.

Bonding Wire .

Seal

Seal Print

LCD Seal .

Search Level

Die Lead .

Second Bond SECSDEV

Lead Frame Bond.

Loopback Test Simulator .

SECSIM(SECS Simulator) SECSTEST SECCPEC Segment

SECS Test PC Simulator.

Loopback Test Simulator HOST .

SECS Protocol Specification Vendor .

NIXIE TUBE , , , . , .

Segment ON/OFF

"8" .

SEG(Selective Epitaxial Growing)

Epi Silicon Oxide . Selective Diffusion() . Selective Oxidation Process() .

Self Align

Mask . Self bias( ) .

Self Refresh

DRAM Refresh Refresh Mode DRAM , Self Refresh DRAM Refresh T ime Refresh .

Self-Alignment

MOD Gate AL Melting Poing AL DEP. Themal Caycle . AL DEP Source Drain Drive-in . S/D Drive-In Gate Define Alignment Tolerrance Overlap Regio n S/D Parasitic Overlap Capac-itance Minimum size .

SEM(Semiconductor Equipment and Material Institute) , .

Semi-Auto

Host CST LOAD/UNLOAD Opertor . Semi-Custom Masker Cell Mask User IC/LSI IC.

Semiconductor.

( ) ( ) .

.

Sensor

Sense AMP

Cell Data Data line voltage swing Data line Signal Am plifier. Sequential Circuit() GateNAND, NOR , Flip-Flop, Shift Register, Counter, Memory .

SER(Soft Error Rate)

Memory Particle FIT .

SET(Summary of Electrical Test) Set-up

TEST Information Sheet.

() . Set-up Mode Arc Energy lon Beam .

SF(Stacking Fault) .

SF(Spiral Flow) .

Sheath() . Shelf() Stocker Cassett .

Shift Register

Register (Shift ) .

Shoe Box Shoom

Carrier 2 , carrier .

Device graphic , 2 , Device pass/fail dotting Device .

.

Short Circuiting Short Repair Shrink

.

Chip .

SiC(Silicon Carbide)

, Wafer Tube , .

Side Ball Bonding

Wire .

Side Etch Silicon

() .

4 .

Silicon Compiler

System master pattern IC .

Silicon Gate

Gate , MOS .

Si Gate MOS

MOS FET Gate (Poly) silicon MOS Device.

Silicon Nitride

.

SIMM(Single In Line Memory Module)Edge connector .

Simulation Vector

simulation input pin input netillist cycle .

Single Crystal Single end

.

lead .

Single In Line.

Lead .

SIP(Single Inline Pkg)

Memory Module Memory Modual, Pin Type Memory Module . Inserting .

Site

Wafer .

Skew Slice

Pin Timing.

Wafer . Silicon .

level , limitter level slicer . Slot() Carrier boat Wafer .

Slicer

Sludge

.

Smart Power IC

Control IC . Smock()

Line .

SN(Spit Notice)

RUN Spit Split .

SOA(Safe Operating Areas) .

Socket Board

Jig (TEST PKG )

SOG(Sea of Gate)

ASIC Unit Gate Array Channel . Metal D ie Unit Gate .

SOG(Spin On Glass)

VLSI , , . SOG SOG 400 ~500 .

SOIC(Silicon outline Integrated Circuit) IC.

SOJ(Small Outline J-form Package)

Device "J" LEAD PKG PCB .

Solder Ball

.

Solder Coating

, Frame Coating . Soldering () PCB I.C , .

Soldering Oil

Wafer Soldering Machine .

Soler Preform Solder Resist

Die Lead Frame .

PCB , Solder . Soler Side() .

Sorting

Wafer .

SOT(Small Outline Transistor) Transistor.

Space Charge Spacer

.

LCD , .

SPARC(Scalable Processor Architecture) Speed-Up Capacitor Spider bonding

SUN MICRO 32 Bit RISC Processor.

TR Inverter Speed-Up .

Wireless Pattern Wafer .

Spike

Silicon Contact .

Spindle Motor

Blade Wafer , . Air Bearing 30, 000RPM .

SPLC(Stocker PLC) Split

Stocker Stocker Program .

Normal RUN .

Split Word line

SRAM Cell Layout Design Asymmetry Word Line .

Argon Gas Target Wafer .

Sputtering

Square Out

Wafer , Wafer .

S-RAM(Static RAM)

Dynamic RAM . .

SSI(Small Scale Integration)

10 Gate . Stack . FAB Silicon .

Standard Cell

Standard Cell Cell , Chip semi-custom LSI Gate Array custom .

Standby

.

.

Standby Current Drain Static Hold

2V Data Data Retention .

Static memory

MOS FET .

STC(Stocker Controller)

Bay Cassette , Bay Cassette Bay Cassette Bay .

STD(Standard)

Stem

TR , Header .

WF 1 Chip Chip . WF 1 . STN(Super-Twisted Nematic) WF PC .

Stepper

Storage Time () TR ON .

Stress

Wafer .

Stringer Strip

Film Etch Residue .

Wafer P.R , .

Strobe

Device Device Latch Timing.

Sub-Mask

Mask Master Mask Mask mask.

Substrate

() , Wafer .

Substrate-Concentration Subtrative Process

Wafer , Bulk .

, , etching . Supported Hole() .

Surface Agent

.

Surface Concentration

. Wafer . Surface Passivation( ) PN . (ACTIVE) PN (PASSIVE) .

Surface Potential Surge Current

. Wafer .

.

Synchronization() Timing .

SWMI(Side Wall Masked Isolation)

LOCOS Isolation Oxide En-croachment , bird's Beak .

TTAB(Tape Automated Bonding)Tap Die .

TAB

TR IC 1mm TAB .

Taping

Wafer Tape ( ).

TCA Oxidation

TCA .

TCP(Tape Carrier Package)

IC Chip Tape Film TAB(Tape automated bonding) Package.

TEG(Test Element Group) Tenting

Bread Board TR, Diode, .

Resist .

TEOS(Tetra Ethyl Ortho Silicate) Terminal

Si Source .

lon Source Cover .

Test Head

Tester Handler Prober Station .

Test Mode

Device Test Test Access Device , Test Test Time Test multi-bit test .

Test Pattern Tester

/ Wafer Pattern.

Computer .

Test Option Test Plan

Computer .

, , , Limit .

Test Program

Wafer Program SPEC Program Software.

Test Schematic(Test Circuit)Jig .

.

Test System

Test Vector

Test Simulation Test Signal Set.

Test vehicle

Mask.

Test Test Program Pass/Fail .

Testability

Chip Level Block Sub Block Test .

TF-EL Display (Thin-Film Electrolumines- cent Displays)

, .

TFIC(Thin Film Integrated Circuit)

5 . .

TFT(Thin Film Transistor) TFT Array

FET.

Matrix TFT .

Thermal Addressing

. Thermo-Optic Effect( ) . .

Thermotropic LC

.

Thermal Relief() . Thermal Shock Test() TR, Diode, IC . Thermo Electric Effect() , , . Thick Film IC( ) 5 .

Thin Film

Thick Film ( 5 micro) .

3D Circuit Device

LSI , DEVICE LSI Silicon LSI . 3 .

Threshold Level

Input Device . Thyristor () PN 3 ON/OFF 2 OFF ON .

Tie bar Tilt

PKG Lead Bar.

, . .

Tilt Angle

.

Timing

Device Comtrol Clock, Address, Data .

Tin Plating Tip

Sn Frame .

Chip .

TiSiX (Titanium Silicide)

Titanium silicon contact .

Tj(junction Temperature).

TN LCD (Twisted Nematic Liquid Crystal Display)90 LCD.

TN-FE LCD (Twisted Nematic Filed Effect LCD)

90 Twist LCD.

TNI. Clearing Point Tooling Hole

.

. Topology () Wafer .

TQFP(Thin Quad Flat Package) TR(Transformer) Transfer

1.0 mm 1.4mm QFP.

.

LCD , Carrier Boat Wafer Carrier Boat .

Transfer Collect Transfer Print

Tape Die .

Ni-beads .

Transfer System

. RUN SHOE BOX Wafer

.

Transition time

Device level level A.C .

Transistor

Emiter Collector base base carrier .

Transition Trap

.

carrier . Trench . FAB , Silicon .

Triangular Voltage Sweep Method

Gate mobile ion oxide current gattte bias oxide check .

.

Triger

Trim/Form

Package lead 90 I.C .

Tristate output

Level High Low High Impedance .

TSOP(Thin Small Outline Package)

Package 1.0mm SOP(SOIC) P-DIP PACKAGE SYSTEM .

TS(Tensile Strength)

.

TTL(Transistor Transistor Logic) TTV(Total Thickness Variation) (wafer)

. .

Tunneling

Bisas PN, Oxide Energy Band Gap

Electron Hole .

TV RUN

Test Vehicle Wafer.

Tweezer

Wafer ( Vacumn Tweezer )

Twist angle

Cell .

UUART(Universal Asynchrnous Receiver & Transmiter) LSI Interface .

UJT(Unjunction TR) Ultra Filter

Junction 1 Base 2 TR.

2 Particle Filter.

Ultrasonic Cleaner

() .

Under Coating

LCD SiO2 . SiO2 . MASK LAYER .

Undershoot Noise

0V NOISE, 0V NS Pulse Negative Latch-up .

Uni-Biopolar IC Unipolar

- TR .

Transistor FET .

Unloader

Frame Magazine Frame .

Unloading

Loading Wafer Tweezer Transfer Arm CARRIER BOAT .

UPS(Uninteruptable Power Supply) . UV(Ultra Violet,) Energy .

VVacumn TubeTransistor , , , , Transistor IC .

Vacuumn Tweezer

Chip Carrier . Valence Band () . Valence Electron() .

Vane Damper Varistor

Fan .

.

Vcc (Supply Voltage)

. Device Device Device .

Vector

Simulation Input Pin Input Netilist Cycle .

Vector Address

Pattern Memory Pattern Address. Verical TR( ) () . .

VFD(Vacumn Fluorescent Display)

. .

VIA

Metal lnsulating filed Contact.

VIA not OPEN

METAL LAYER PROCESS VIA CONTACT UNDER ETCH Metal Layer Contact SPEC .

Via hole

PCB .

Viewing Angle

. LCD. Virtual Cieaing Point( ) .

Viscosity

, . .

Visual inspection Void

Chip Device .

RTN (). FAB SPACE .

Vss

Device Device Vcc Clock Device Signal . VTD Depletion TR VTH.

VTH(Threshold Voltage).

VTN

Natural TR VTH.

VTPC(Vertical Probe Card)

Wafer Test Device PAD Needle Probe Card Probe Card Needle .

WWafer (Si) .

Wafer Carrier Wafer ID

Wafer , .

RUN Wafer Wafer .

Wafer Sort

Wafer Level GO/NO-GO Test , Test Wafer Probe Prober Card Test . Wafer Storage Box (Wafer) Wafer Carrier Box.

Wave Form

Wafer lon Beam .

Wave Soldering

.

Wedge Bonding Well

.

CMOS Technology N-Channel Transistor P-Channel Transistor Si-Substrate N P-Channel Transistor substrate.

Wet Etch Wet Sink Wetting

. .

Wafer .

.

WI(Wire Inspection)Bond .

Wide Bit

8bit I/O Byte Word Dar Device .

WIP(Work In Process)()

Wire Bonder

TR IC Wire Bonding Wire Bonder .

Wireless Bonding Work Function

.

.

Work Holder

Lead Frame Loader Magazine Die Unloading Magazine .

Work station Worm

WF .

(1 : Write once Read many) .

Write

EPROM EEPROM Floating Gate Bit .

WSI(Wafer Scale Integration)

Wafer Chip Wafer .

WSTS(World Semicondiuctor Trade Statistics)

. .

XXylne or Way Coat (resist) .

Y

Yield

Wafer Wafer 1 Wafer Chip Wafer Test Chip .

ZZenor breakdownPN Diode 0 . . Zenor . PN Diode , . . , . .

Zero ohm resistor

SIMM PD Pin Chip Connector ZERO OHM RESISTOR .

ZIP(Zigzag In-line Package)

Package Type Package Lead Zigzag Device .

Zone AHU(Zone Air Handing Unit)

FAB Return FAB Air .