dll designoverall presentation •the dll will allow us to have a controlled sampling rate....

DLL design

Herve Grabas

4/28/2010 13rd Chip Review

Overall presentation

• The DLL will allow us to have a controlled sampling rate.

• Provide us a cleaner sampling window

• No dead zone of sampling ( if the effective delay free running delay line is less than the period of the input clock -> dead time)

4/28/20103rd Chip Review

2

CMOS design

• Cell design

Phase detector

Charge pump

Delay line

Some control logic

• Simulation

Complicated: long locking time, small time steps.

The use of VerilogA language and mixed signal simulation saves you.


3

DLL simulation

• Difficult because: DLL function with 40ps delays.Locking take up to 100us.

• Therefore, there is more than 7 orders of magnitude of difference between the smallest time step and the biggest one.

• Solution : not simulating the internal function of the delay line.


4

Delay line simulation model (1)

• Delay line structure: chain of small delays.


5

Generates a sampling frequency equals to Delay

1

Delay line simulation model (2)• From its input and output the delay line is however nothing

else than a big delay adjustable by to voltages : VCN and VCP.


6

Delay line simulation (3)

• VerilogAMS description of the VCDL:

Allow us to describe

a variable delay.

Description uses post

layout results from Eric


7

DLL simulation success


8

Delay Locked Loop principle

1. VCN and VCP are set to their max value (1.2 & 0 resp.). The propagation delay in the DLL is then the smallest -> 11ns.

2. The delay is increased until it reaches the delay of one clock cycle.

3. The phase comparator locks then the delay of the delay line at one clock cycle


9

Delay locked loop control logic• In a delay locked loop the generated delay of the delay line cannot

reach 0. It is always minored by the smallest delay of the line. Here 11ns.

• Therefore, the DLL can never lock on the first edge of the clock. (See Fig.)

• However the phase comparator work at ±180° around a clock edge. And in some case this can result in the DLL trying to lock on the first edge of the clock (See Fig.)

• This has to be taken care of. Some simple logic is sufficient.


10

DLL control logic (2)

• The control logic outputs 1 if VDLL is in the wrong pull-in range.

• After having being active the pull-out logic is inactivated. (The DLL can only be in the wrong pull-in range once).

• The control logic operates directly on the phase comparator to preserve its speed.


11

Dynamic phase comparator


12

• It is a dynamic phase comparator so it is extremely fast. Therefore it gives us very accurate jitter correction.

• Adjusted to give us directly the right control signal for the charge pump. (No extra inverted needed).

• Shift logic integrated.

Charge pump


13

• High performance charge pump.

• 1uA external current source.

• Cascode current mirror to increase output resistance, so that charging and discharging current are not disturbed by the state of the output. (Better current matching).

Delay locked loop4/28/20103rd Chip Review

14

• Whole schematic circuit with the control logic.

Layout: Charge pump & Phase detector


15

• Layout of the charge pump and phase detector done together for better matching and smallest wiring capacitances.

• 16um x 18um

Layout Control logic


16

Results

• Successful simulation and locking pre and post layout.

• Lock time ~ 10 us.

• Simulation time ~10 min.

• Measured jitter in schematic simulation : 8as (not legitimate!)

• 300fs in post-layout simulation with the behavioral model of the DLL.

• DLL system is stable and precise.


17

Results (2): The pull-out


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Pull-out control signal

Decrease in VCN -> Increase in delay.

Results (3) : The locking


19

Small UP and DOWN control signal. Locking almost complete.

Results (4) : The jitter


20

Very low delay variations at the output of the delay line

dll designoverall presentation •the dll will allow us to have a controlled sampling rate....

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