divided word line architecture

7/13/2019 Divided word line architecture

1/28

1

EE 587

SoC Design & Test

Partha Pande

School of EECS

Washington State University

[email protected]


2/28

2

System Design Issues


3/28

3

Low Energy FPGA Architecture

Architectural level optimization

Level 0 Nearest Neighbor

Level 1 Mesh

Level 2 - Hierarchical


4/28

4

Different Architectures


5/28

5

Paths in Interconnect

Connection may be long, complex:

LE LE LE LE LE

LE LE LE LE LE

LE LE LE LE LE

Wiring channel

Wiringchannel


6/28

6

Interconnect Architecture

Connections from wiring channels to LEs.

Connections between wires in the wiring channels.

LE LE

Wiring channel


7/28

7

Switchbox

channel channel

channel

channel


8/28

8

Mesh-based Interconnect Network

Switch BoxRouting of the data

Connect Box

Connects cell I/Os

To the globalinterconnect

Interconnect

Point

Courtesy Dehon and Wawrzyniek


9/28

9

Circuit Level Optimization

The connecting path from one CLB to

another is an RCchain


10/28

10

Low Swing Interconnect

Mode E (pj) D (ns) ED

Full Swing 72.3 1.9 137

Low Swing 31.4 2.3 72


11/28

11

Low Power SRAM Design


12/28

12

Memory Organization

Sense amplifiers/drivers

Column decoder

AKAK-1

AL-1

Storage cell

Word line

Bit line

Input-Output (M bits)

A0

AK-1

2L-K

M.2K


13/28

13

SRAM Cell

bit bit

VDD

Sense

amplifier

PC

EQ

Output

BL BL

WL

Precharge

circuit


14/28

14

Cell Array Power Management

Smaller transistors Low supply voltage

Lower voltage swing (0.1V 0.3V for SRAM)

Sense amplifier restores the full voltage swing for outside

use.


15/28

15

SRAM Cell Design

6 transistor SRAM cell reduces static current

(leakage) but take more area

Vthreduction in very low VddSRAMs suffer from

large leakage current

Use multiple threshold devices:

Memory cell with high Vth(reduce leakage)

Peripheral circuits with low Vth(improve speed)


16/28

16

Banked Organization

Banking targets total switched capacitance to achieve reducedpower and improved speed


17/28

17

Divided Word Line

Main idea: Divide each row of RAM cells into segments (blocks), use a

decoder to access only one segment

Only the memory cells in the activated block have their bit line pair

driven


18/28

18

Divided Word Line

Pros:

Improves speed (by decreasing word line delay)

Lower power dissipation (by decreasing the number of bitline pair activated)

However, local decoders add delay

Less cells/block reduces power, but increases area (more localdecoders)

Chang, 1997:

49.8% power reduction, 14.8% area penalty

82.9% power reduction, 24.8% area penalty


19/28

19

Reduced Bit Line Swing

Limit voltage swing on bit lines to improve both speed andpower:

1. Pulsed word line

2. Bit line isolation

Need sense amplifiers for each column to sense/restoresignal


20/28

20

Pulsed Word Line

Main idea: Isolate memory cellsfrom the bit lines after sensing,

to prevent the cells from

changing the bit line voltage

further


21/28

21

Pulsed Word Line

Q

R S

Reset from dummy sense-amp Word enable

SA Sense Amplifiers

Memory Core

Accessed Row

DummyColumn

WordD

river

WordDecoder


22/28

22

Pulsed Word Line

Dummy bit lines reach full swing, but trigger pulse shut off when regularbit lines reach 10% swing

Generation of word line pulses very critical

Too long: power efficiency degraded

Too short: Sense amplifiers operation may fail

Generation of word line using delay lines is susceptible to process andtemperature


23/28

23

Bit Line Isolation

Main idea: Isolate sense amplifiers from bit line after sensing, toprevent from having large voltage swings


24/28

24

Row Decoders

Collection of 2M

complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder


25/28

25

Hierarchical Decoders

A2A2

A2A3

WL0

A2A3A2A3A2A3

A3 A3A0A0

A0A1A0A1A0A1A0A1

A1 A1

WL1

Mult i -s tage imp lementat ion imp roves performance

NAND decoder using

2-input pre-decoders


26/28

26

Data Retention in SRAM

(A)

1.30u

1.10u

900n

700n

500n

300n

100n

0.00 .600 1.20 1.80

Factor 7

0.13 m CMOSm

0.18 m CMOSm

VDD

Ileaka

ge

SRAM leakage inc reases with technology scaling


27/28

27

Reducing Retention Current

Turning off unused memory blocks Increasing the thresholds by using body biasing

Inserting extra resistance in the leakage path

Lowering the supply voltage


28/28

28

Suppressing Leakage in SRAM

SRAMcell

SRAMcell

SRAMcell

VDD,int

VDD

VDD VDDL

VSS,int

sleep

sleep

SRAMcell

SRAMcell

SRAMcell

VDD,int

sleep

low-threshold transistor

Reducing the supp ly vol tageInsert ing Extra Resistance

divided word line architecture

Documents