IEEE CAS, Dallas Chapter: Seminar Feb 15, 2005

Direct RF Sampling for Digital Radio Processing:

Principles and Methods

Khurram MuhammadWireless Terminal Business Unit

Texas Instruments, Dallas, TX

Outline• Motivation• Deep-submicron low-complexity design

– Direct rf sampling– Discrete-time signal processing receiver architecture– Digital Backend

• Analog impairments• Bluetooth Receiver example (sens: -83dBm)• GSM/GPRS Receiver example (sens: -110dBm)• Conclusion

2

Motivation• Low-cost

– Base digital deep-submicron CMOS process– Low-power– Amenable to migration to newer processes– Excellent performance; marketing reasons!– Fully integrated

• Transceiver + Digital BB + Memory + Power Management + RFBIST

• Analog/RF functions like important “guests” on application centric solutions

– very large RAM– Analog/rf typically occupy < 5% area

– Built-in calibration mechanisms3

I. Direct RF Sampling

Receiver Architecture ExampleContinuous

Time

5

LNA

ADPLL DCU PCU

TA SAMPLER SINCFILTER 8 4FILTER

IIR/SINCSINC

FILTERIFA

32 ADC

MTDSM

TA SAMPLER SINCFILTER 8 4FILTER

IIR/SINCSINC

FILTERIFA3

2 ADC

MTDSM

DIGITALRECEIVE

CHAIN

2400 MS/s 300 MS/s 75 MS/s 37.5 MS/s

AGC ADCAGC

AGC ADC

CLKBITS

LNTA

Discrete Time

Source: K. Muhammad et. al., “A Discrete-Time Bluetooth Receiver in a 0.13µm Digital CMOS Process,” paper 15.1, ISSCC 2004.

Discrete Time Receiver

LNA

ADPLL DCU PCU

TA SAMPLER SINCFILTER 8 4FILTER

IIR/SINCSINC

FILTERIFA

32 ADC

MTDSM

TA SAMPLER SINCFILTER 8 4FILTER

IIR/SINCSINC

FILTERIFA3

2 ADC

MTDSM

DIGITALRECEIVE

CHAIN

2400 MS/s 300 MS/s 75 MS/s 37.5 MS/s

AGC ADCAGC

AGC ADC

CLKBITS

LNTA

MTDSM

6

MTDSM: Multi-tap Direct Sampling Mixer

Cb

DAC

CrPA

PB

RES

DUMP

FAFB

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

7

MTDSM Sub-Blocks

Cb4 Cr

Cf

DIN_CMDIN_DM

CrCh

LNTA

I_FBCK_P

AVSS

IFOUT_PRFINLO

Readout ChargeMix &Sample

DAC

2400 MHz

Ch+Cr

VSSVSSVSSVSSVSSVSSVSSVSS

gmvrf

Cf

VSS

I_FBCK_P

TEMPORAL AVERAGINGSINC FILTER

PREPARINGFOR

PRECHARGE

Voltage gain over single RF half cycle:

8

IIR Filtering

9

Combined Response

Ref: K.Muhammad et. al, “Direct RF sampling mixer with recursive filtering incharge domain,” ISCAS 2004 10

Offset and CM ControlDIN_CM

DIN_DMLNTA

I_FBCK_P

AVSS

IFOUT_PRFINLO

Cb

VSS

Cr

VSS

Cr

VSS

Cr

VSS

Cr

VSS

Cf

VSS

PRECHARGE

• No dc current• charge packets diverted from plus to minus or vice versa under digital control

11

II. Digital Controls

Offsets, Common Mode• LO leakage and dc offset• 1/f noise

– No continuous current flow

LNARFIN MTDSMgm

LO

13

Programmable filtering• Corner frequency• Order• Rotation rate

Cb1Cr1Cr1Ch

LNTA

AVSS

RFINLO

2400 MHz

Cb2Cr2Cr2

IFOUT2IFOUT1

14

III. Operation

Phase 1

Cb

DAC

Cr

DUMP

FB

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1LNTA

S(0) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

0 0 0 0 0 0 01

LO

Readout

ChargeSample

16

Phase 2

Cb

DAC

Cr

DUMP

FB

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

1

0 0 0 00 1 0 0

LO

17

Phase 3

Cb

DAC

Cr RES

FA

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

1

0 0 0 00 0 1 0

LO

18

Phase 4

Cb

DAC

Cr

PB FA

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

0 0 0 00 0 0 1

LO

19

Phase 5

Cb

DAC

Cr

DUMP

FA

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

1 0 0 00 0 0 0

LO

ChargeSample

Readout

20

Phase 6

Cb

DAC

Cr

DUMP

FA

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

0 1 0 00 0 0 0

LO

21

Phase 7

Cb

DAC

Cr RES

FB

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

0 0 1 00 0 0 0

LO

22

Phase 8

Cb

DAC

CrPA

FB

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNTA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

0 0 0 10 0 0 0

LO

23

24

MTDSM Sinc Response

Digital Receiver Backend

25

Calibration

ejωt

26

Higher Rate Sampling: 2-pole system

Cb

DAC

CrPA

PB

RES

DUMP

FAFB

Cf CfCr

DIN_CMDIN_DM

CrCrCrCrCrCrCh

SAZSBZLO/8

1

LNA

S(0) S(1) S(2) S(3) S(4) S(5) S(6) S(7)

I_FBCK_PI_FBCK_M

To NegativeSide

AVSS

DCU

BANK A BANK B

IFOUT_P

RFIN

Dump/Precharge

600 Mspsreadout

rate

Bank A

Bank B Dump/Precharge

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MTDSM Advantages• Mixer embedding a filter

– Anti-aliasing– Adjacent channel interferer rejection

• Reduces linearity requirements of ABE• Reduces dynamic range requirements of ABE

– No further filtering required

– Modular and scalable– Programmable

• Filtering performance• Noise performance• Feedback configuration

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IV. Results

Implementation• Digital deep-submicron 0.13µm CMOS process

with no analog extensions• RF and analog integrated with digital

Interconnect material copperMinimum metal pitch 0.35 um

Transistor nom. voltage 1.5 VL drawn 0.11 um

L effective 0.08 umGate oxide 29 A

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Measurement Results• Passed the official Bluetooth qualification• C/I = 10.5 dB, Max. Input = -5dBm, DBB = 4 mA

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Work TechnologyTX

Current(mA)

RX Current

(mA)

SensitivitydBm

This one 0.13u,1.575V 25 37 -83

[1] 0.18u2.5-3.0V

35.5 30.5 -78

[2] 0.18u2.7V

37 39 -83

[3] 0.25u?V

36 45 ≤ -70

[4] 0.25u2.5V

<70 <50 -80

Chip Micrograph - Bluetooth

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• Single-chip Bluetooth radio

• RX path– Direct RF Sampling– Discrete time RX

path with Σ∆ ADC• 1.575V / 37mA

current consumption in continuous RX mode

130nm Digital CMOS Process

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Chip Micrograph – GSM/GPRS

FREF

ABE

MTDSM

LNA

DCO

PM BGAP

PM

90nm Digital CMOS Process

RX path• Direct RF Sampling• Discrete time RX, Σ∆ADC@500Msps• 1.4V design• Scalable architecture

Conclusions• The first commercial discrete time wireless RX at par

with continuous time architectures– Bluetooth– GSM/GPRS– …

• Direct rf sampling followed by discrete-time signal processing

• Performance demonstrated in single-chip fully-compliant radios

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References

[1] P. T. M. van Zeijl et al., “A Buetooth Radio in 0.18um CMOS,” ISSCCDig. Tech. Papers, pp. 86–87, Feb. 2002.[2] G. Chang et al., “A Direct-Conversion Single-Chip Radio-Modem forBluetooth,” ISSCC Dig.Tech. Papers, pp. 88–89, Feb. 2002.[3] J. Cheah et al., “Design of a Low-Cost Integrated 0.25um CMOSBluetooth SOC in 16.5mm2 Silicon Area,” ISSCC Dig. Tech. Papers, pp.90–91, Feb. 2001.[4] Eynde et al., “A Fully-Integrated Single-Chip SoC for Bluetooth,”ISSCC Dig. Tech. Papers, pp. 196–197, Feb. 2001.

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