LETTER

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDACboosting common-mode voltage and controlling input voltage range

Jisu Son1 and Young-Chan Jang2a)

Abstract A capacitor digital-to-analog converter (CDAC), which booststhe common-mode voltage and controls the input voltage rang, is proposedto improve the dynamic range and linearity of a single-ended successiveapproximation register (SAR) analog-to-digital converter (ADC). The 10-bit 10-MS/s single-ended asynchronous SAR ADC using the proposedCDAC is implemented by using a 180-nm CMOS process with a supplyvoltage of 1.8V. Its active area and power consumption are 0.207mm2 and2.29mW, respectively. The measured DNL and INL are +0.93/−0.51LSBs and +0.61/−0.81 LSBs, respectively. The measured ENOB is 9.04bits for the analog input signal with Nyquist frequency.Keywords: successive approximation register, analog-to-digital convert-er, capacitor digital-to-analog converterClassification: Integrated circuits

1. Introduction

Natural analog signals and signals from various electronicdevices are still measured with respect to the ground inthe form of single-edged signals. Despite this form ofsignal measurement, differential analog-to-digital convert-ers (ADCs) are mainly used for high-resolution sensorinterfaces. Therefore, a signal-to-differential converter isadditionally used in sensor interfaces for differential ADCs.However, as the demand for low-power sensor interfaceshas increased, single-ended successive approximatelyregister (SAR) ADCs with capacitor digital-to-analog con-verters (CDACs) are being used for data conversionof signals with dynamic ranges of approximately 60 dB[1, 2, 3, 4]. Although the input signal of the SAR ADCis generally a single-ended analog signal, a differentialSAR ADC with a middle reference (VREFM ) for one ofthe two input signals is commonly used to increase thenoise immunity of the ADC circuit [5, 6, 7, 8, 9, 10, 11,12]. In this case, the dynamic range of the single-endedSAR ADC can be reduced to half of that of a differentialSAR ADC. To achieve the full dynamic range of thesingle-ended SAR ADC with a rail-to-rail input signalrange, additional references with different voltage levelscompared to VDD and VSS are required for the top andbottom references (VREFT and VREFB). In addition, the

supply of a single-ended signal to the differential CDACof the single-ended SAR ADC deteriorates the performanceof the comparator following the differential CDAC dueto changes in the common-mode voltage of the differentialoutput of the CDAC. This can degrade the linearity per-formance of the single-ended SAR ADC [13, 14, 15].

In this letter, a 10-bit 10-MS/s single-ended asynchro-nous SAR ADC is proposed for low-power sensor inter-faces. The dynamic range and linearity of the single-endedSAR ADC are improved using the proposed CDAC thatboosts the common-mode voltage while controlling theinput voltage range. The additional capacitor in the pro-posed CDAC enables implementation of the single-endedSAR ADC with a full dynamic range of 10-bit resolutionwithout further reference requirement by controlling theinput voltage range in the half rail-to-rail mode operation.Furthermore, it improves the linearity of the single-endedSAR ADC by boosting the common-mode voltage of theCDAC to a value higher than the middle-reference voltage.

2. Proposed single-ended asynchronous SAR withCDAC boosting common-mode voltage and controll-ing input voltage range

The proposed 10-bit 10-MS/s single-ended asynchronousSAR ADC consists of a CDAC boosting a common-modevoltage, a comparator, an internal reference driver, and aSAR logic, as shown in Fig. 1(a). The proposed single-ended SAR ADC uses an asynchronous architecture toincrease the sampling rate without increasing the frequencyof the external clock, compared with a typical SAR ADC[16, 17, 18, 19, 20, 21, 22]. The binary search operation ofthe SAR logic, shown in Fig. 1(b), is sequentially per-formed by using a valid signal of the comparator, whichinforms the completion of the comparison operation in thecomparator. At the rising edge of EX_CLK, which is thesynchronous clock signal of the SAR ADC, the samplingprocess in the single-ended SAR ADC is completed andthe data conversion process for a 10-bit resolution starts.The operation of the CDAC and comparator is performedasynchronously ten times by controlling the SAR logic fordata conversion of the sampled analog signal. After thisconversion, the single-ended SAR ADC samples the newanalog signal until the next rising edge of EX_CLK. Theoperation sequence of the proposed single-ended SARADC is independent of the duty cycle ratio of EX_CLKbecause the proposed single-ended SAR ADC only usesthe rising edge of EX_CLK.

DOI: 10.1587/elex.16.20190597Received September 20, 2019Accepted October 15, 2019Publicized November 1, 2019Copyedited November 25, 2019

1Silicon Works Inc., Daejeon 34027, Korea2School of Electronic Engineering, Kumoh National Instituteof Technology, Gumi 39177, Koreaa) ycjang@kumoh.ac.kr

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Copyright © 2019 The Institute of Electronics, Information and Communication Engineers

In this work, the proposed single-ended SAR ADCuses a half rail-to-rail mode operation [23, 24] to imple-ment the full dynamic range without additional referenceswith different voltage levels. The half rail-to-rail modeoperation in a single-ended SAR ADC effectively reducesthe input voltage range in half compared with the inputvoltage range of a differential SAR ADC. In addition, theCDAC boosts the common-mode voltage of its differentialoutput signal to improve the linearity deteriorated by thechanges in the common-mode voltage in the single-endedSAR ADC. These two functions are implemented by add-ing capacitors in the CDAC. To reduce the total capaci-tance of the CDAC that is increasing because of theboosting of the common-mode voltage and the control ofthe input voltage range, the proposed CDAC uses a VCM-based switching architecture [25, 26, 27]. To implement thesingle-ended SAR ADC with no dynamic range degrada-tion although VREFT and VREFB have voltage levels corre-sponding to VDD and VSS , the CDAC controls the connec-tion of the added capacitor CBOOST , as shown in Fig. 1(a),according to the half rail-to-rail mode operation. The valueof CBOOST is twice that of C8. The capacitors from C8 toC0A in the CDAC are switched for a 10-bit resolution, asshown in Fig. 1(b). To reduce the effect of the referencevoltage in half for the half rail-to-rail mode operation,CBOOST and C0B are operated only for the sampling andVCM-based CDAC operation.

When the differential signal with the input voltagerange from VREFB to VREFT is supplied to the CDAC, thecommon-mode voltage of the CDAC is generally deter-mined to be 1=2 � ðVREFT þ VREFBÞ, the common-modevoltage of the differential signal. However, because VREFM

is supplied as the negative input of the CDAC for theoperation of the single-ended SAR ADC, the common-

mode voltage of the CDAC is changed according to thevoltage level of the input signal of the single-ended SARADC. Fig. 2 shows the differential output waveform of theCDAC according to the progress of data conversion whenthe node VCM of the CDAC is set to the middle voltage ofthe single-ended input signal. When the input signal of thesingle-ended SAR ADC is VREFB and VREFT , the common-mode voltages of the CDAC converge to 3=4 � VREFT þ1=4 � VREFB and 1=4 � VREFT þ 3=4 � VREFB, respectively,as shown in Fig. 2(a). In this case, a comparator with awide input voltage range connected in parallel with theNMOS and the PMOS input stages is required to comparethis differential signal with a change in the common-modevoltage [28, 29, 30, 31]. However, the input offset voltagedifference between the two input stages generated owing toprocess mismatch that degrades the linearity performanceof the single-ended SAR ADC. The proposed CDACboosts the common-mode voltage of its differential outputsignal by connecting to VREFT the capacitor CBOOST usedfor the half rail-to-rail mode operation when the common-mode voltage of the CDAC converges to a voltage levellower than 1=2 � ðVREFT þ VREFBÞ. Fig. 2(b) shows thatthe common-mode voltage of the CDAC converge to1=2 � ðVREFT þ VREFBÞ finally through this process whenVIP and VIN are VREFT and VREFM , respectively. Therefore,the proposed SAR ADC reduces the linearity error causedby the input voltage dependent offset voltage of the com-parator by using the letter with only NMOS input stage[23, 32, 33]. Fig. 3 shows the operation of the proposed

(a)

(b)

Fig. 1. Proposed single-ended asynchronous SAR ADC (a) blockdiagram (b) timing diagram.

(a)

(b)

Fig. 2. Differential output of CDAC for single-ended SAR ADC(@ VIP ¼ VREFB or VREFT ; VIM ¼ VREFM ) (a) case of conventionalCDAC (b) case of proposed CDAC.

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CDAC according to the input voltage level of the single-ended SAR ADC. The single-ended SAR ADC samples avoltage level of VREFB in all capacitors of the CDAC shownin Fig. 3(a). During the sampling phase, the two outputnodes of the CDAC, VDACP and VDACM , are not driven to aspecific reference to reduce additional power consumptionin the reference driver. The voltage at these two nodes isdetermined by charge sharing of the CDAC as the centervoltage between the two analog input signals. The capaci-tor CBOOST in the CDAC is first switched to the node VCM

for the VCM-based CDAC and half rail-to-rail mode oper-ation, as shown in Fig. 3(b). Subsequently, the most sig-nificant bit (MSB) B[9] is determined to be low by per-forming the first comparison in the comparator. Owing tothe result of the MSB B[9], the connection of the capacitorCBOOST is maintained at VCM for the remaining data con-version process, as shown Fig. 3(c). When the voltagelevel of VREFT is sampled by the single-ended SARADC, the MSB B[9] is determined to be high after thefirst conversion of the CDAC, as shown in Fig. 3(b). Fromthis result, the common-mode voltage of the CDAC isexpected to converge to a voltage level lower than 1=2 �ðVREFT þ VREFBÞ. In this case, the two capacitors CBOOST

are all switched to VREFT whereas the two capacitors C8 areswitched by the result of the MSB B[9] in the secondconversion of the CDAC, as shown in Fig. 3(d). Owing tothis CDAC operation, the two outputs of the CDAC aredetermined using Eqs. (1) and (2). The last term is the

voltage boosted by the proposed CDAC. The common-mode voltage of the CDAC is determined using Eq. (3).The connection of the two capacitors CBOOST to VREFT ismaintained for the remainder of the switching process ofthe CDAC. The final common-mode voltage of the CDACis also expressed using Eq. (3) when the single input signalVIP is VREFT .

VDACP ¼ �VIP þ 7

4� VCM þ 1

4� VREFT þ 1

4� ðVREFT � VREFTBÞ ð1Þ

VDACM ¼ �VIN þ 7

4� VCM þ 1

4� VREFB þ 1

4� ðVREFT � VREFTBÞ ð2Þ

ðVDACP þ VDACM Þ2

¼ 1

2� VREFT þ 1

2� VREFTB ð3Þ

Fig. 4 shows the simulated static performances of thesingle-ended SAR ADC depending on the boosting of thecommon-mode voltage of the CDAC. When the analoginput voltage supplied to the conventional single-endedSAR ADC increases to a value higher than VREFM , theoutput common-mode voltage of the conventional CDACbecomes lower than VREFM . In this case, the comparatorconsisting only of the NMOS input stage cannot accuratelycompare the two output signals of the CDAC. Therefore, asthe digital output code of the SAR ADC increases, thelinearity of the conventional single-ended SAR ADC de-grades, as shown in Fig. 4(a). The proposed CDAC, whichcan boost the common-mode voltage, improves the integralnonlinearity (INL) of the single-ended SAR ADC from+0.37/−1.31 least significant bits (LSBs) to +0.16/−0.16LSBs, as shown in Fig. 4(b). As the performance of thecomparator is affected by the input common-mode voltage,it has a greater effect on the performance improvement ofthe single-ended SAR ADC as the supply voltage is lower.

(a)

(b)

(c)

(d)

Fig. 3. Operation waveform of proposed CDAC for single-ended ADC(a) sample for input signal of single-ended SAR ADC (b) first CDACconversion for VCM-based CDAC operation (c) second CDAC conversionfor proposed CDAC operation (@ VIP < VREFM ) (d) second CDACconversion for proposed CDAC operation (@VIP > VREFM ).

(a)

(b)

Fig. 4. Simulated static performances of single-ended SAR ADCaccording to boost of common-mode voltage of CDAC (a) withoutboosting common-mode voltage of conventional CDAC (b) with boostingcommon-mode voltage of proposed CDAC.

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3. Chip implementation and measurement results ofproposed single-ended SAR

The proposed 10-bit 10-MS/s single-ended asynchronousSAR ADC was implemented by using a 180-nm CMOSprocess with a supply voltage of 1.8V. Its active area andpower consumption including the reference driver are530 �m � 390 �m and 2.29mW, respectively, as shown inFig. 5.

The measured differential nonlinearity (DNL) and INLshown in Fig. 6 are +0.93/−0.51 LSBs and +0.61/−0.81LSBs, respectively. In the center code, the DNL has arelatively large value of +0.93 LSBs, which is not relatedto the common-mode boost of the proposed CDAC, and itis due to the capacitor mismatches of the CDAC. Thejumping points in the measured INL were also generatedbecause of the mismatches of the binary-weighted capaci-tors for MSBs above C7 in the CDAC. However, theproposed CDAC, which can boost the output common-mode voltage, eliminated the degradation of INL in thedigital output codes above “800”, as shown in Fig. 4(a) dueto the increase in the input common-mode voltage of thesingle-ended SAR ADC. The measured effective number ofbits (ENOBs) are 9.22 bits and 9.04 bits for the analoginput signals with low and Nyquist frequencies, respec-tively, as shown in Fig. 7.

4. Conclusion

The proposed 10-bit 10-MS/s single-ended asynchronousSAR ADC was designed using a 180-nm CMOS processwith a supply voltage of 1.8V. The proposed CDAC,which boosts the common-mode voltage and controls theinput voltage range, was proposed to eliminate the degra-dation of dynamic range and linearity caused in the single-

ended SAR ADC. The proposed CDAC improved the INLof the simulated static performances of the single-endedSAR ADC from +0.37/−1.31 LSBs to +0.16/−0.16LSBs. The measured ENOBs was 9.04 bits for the analoginput signals with Nyquist frequencies. The power con-sumption, including the reference driver, was 2.29mW.

Acknowledgments

This work was supported by the Priority Research CentersProgram (No. 2018R1A6A1A03024003) through the NRFand the HRD Program for Intelligent semiconductorIndustry (No. N0001883) through the KIAT funded bythe Korea Government. The EDA tools were supportedby IDEC.

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