IEICE TRANS. FUNDAMENTALS, VOL.E96A, NO.2 FEBRUARY 2013443

PAPER Special Section on Analog Circuit Techniques and Related TopicsA 410 bit, 0.41 V Power Supply, Power Scalable AsynchronousSAR-ADC in 40 nm-CMOS with Wide Supply Voltage RangeSAR Controller

Akira SHIKATAa), Student Member, Ryota SEKIMOTO, Kentaro YOSHIOKA, Nonmembers,Tadahiro KURODA, and Hiroki ISHIKURO, Members

SUMMARY This paper presents a wide range in supply voltage, reso-lution, and sampling rate asynchronous successive approximation register(SAR) analog-to-digital converter (ADC). The proposed dierential flip-flop in SAR logic and high eciency wide range delay element extendthe flexibility of speed and resolution tradeo. The ADC fabricated in40 nm CMOS process covers 410 bit resolution and 0.41 V power supplyrange. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv.with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keepingENOB of 8.7 bit.key words: analog-to-digital converter, successive approximation, asyn-chronous, dierential flip-flop

1. Introduction

Power ecient, performance scalable circuit is essential forfuture applications like a wireless sensor network and med-ical implantable devices. Such applications require variouskinds of specifications. For example, the required specifica-tion ranges from low frequency, high resolution signal suchas temperature monitoring to high frequency and low reso-lution signal such as image capturing. Furthermore, to usefor energy harvesting devices, ultra-low-voltage operation isalso important. This trend is also applied to ADCs. How-ever, designing power ecient, performance scalable ADCsis dicult because of those complex and large structure.

Among various types of ADC architectures, SAR-ADC is suited for low-voltage and low-power operation be-cause of its relatively simple structure and resource reuseoperation. Low power SAR-ADCs are intensively stud-ied and several fJ/conv. ADCs have been reported [1][4].Especially, [2][4] operate at enough low voltage and lowpower for energy harvesting powered systems. As a result,low cost wireless sensor network system becomes feasible.However, these previous reported works were designed forfixed specification and cannot be used for wide variety ofapplications.

Recently, wide operational range in power supply volt-age and resolution SAR-ADCs have been reported [5], [6].However, the power of ADC in [5] is still far away from best

Manuscript received June 5, 2012.Manuscript revised September 20, 2012.The authors are with Keio University, Yokohama-shi, 223-

8522 Japan.a) E-mail: shikata@iskr.elec.keio.ac.jp

DOI: 10.1587/transfun.E96.A.443

Fig. 1 Eciency (FoM) of past published resolution reconfigurable SARADCs against eective number of bits (ENOB).

Fig. 2 Sampling Speed (Fs) against ENOB of past published resolutionreconfigurable SAR ADCs and the target of this work. The data is takenfrom their performance summary tables. Reference [5] operates up to3 MHz with 5 bit mode and 2 MHz with 8 bit mode and 10 bit mode at 1 V.

ecient ADCs in both of normal supply voltage [1] and lowvoltage [3], [4]. Reference [6] achieved high eciency butthe power supply voltage is fixed at 1.1 V (Fig. 1). Theirsampling rate limitations are from 2 (5 bit mode) to 3 MS/s(810 bit mode) at 1 V [5] and 4 MS/s (for all resolution)at 1.1 V [6], respectively (Fig. 2). This indicates these widerange ADCs still have lots to improve speed and resolutiontrade-o.

In the previous works [1][10], the power eciencywas improved mainly by developed internal DAC and com-parator. As a result, relative power consumption of the SARlogic compared with DAC and comparator increases [11].To reduce the power consumption, asynchronous SAR logic

Copyright c 2013 The Institute of Electronics, Information and Communication Engineers

444IEICE TRANS. FUNDAMENTALS, VOL.E96A, NO.2 FEBRUARY 2013

with dierential dynamic flip-flop was reported [11]. How-ever, it has potential problems of data retention error anddata write error at ultra low voltage operation.

In this study, we proposed an asynchronous SAR con-troller which can be used in wide frequency range with widepower supply voltage range. By using the proposed SARcontroller, power ecient and performance scalable ADCwas developed.

In the following sections, Sect. 2 describes the pro-posed resolution configurable architecture, Sect. 3 explainsSAR controller problems, Sect. 4 describes the circuit im-plementations, Sect. 5 shows the measurement results, andfinally, in Sect. 6, we conclude this paper.

2. Resolution Configurable Architecture

The proposed SAR ADC adopts the asynchronous top platesampling architecture for wide voltage range operation. Thetop plate sampling substitutes CMOS switches in DACwhich are hard to drive at low voltage to simple logical gatessuch as an inverter buer.

As shown in Fig. 3(a), the proposed resolution config-urable SAR-ADC consists of a bootstrapped switch [12] asthe track and hold (T/H), an internal 9-bit reconfigurableDAC and its foreground calibration unit (DAC CAL UNIT)[3], [4], a clocked comparator [13], 410 bit resolution con-figurable SAR logic, and an asynchronous clock generationcircuit. For the simplicity, T/H circuit and DAC is expressedin single-ended circuit in Fig. 3(a). In the actual implemen-tation, T/H circuit and charge redistribution DAC are com-bined together and have dierential circuits. ADC resolu-tion, the comparator capacitive load, and the delay time in

Fig. 3 (a) Block diagram of the proposed SAR-ADC single-endedexample, (b) the operation of the N-bit mode SAR-ADC.

clock generator circuit are digitally controlled to further op-timize the speed and resolution tradeo. Thanks to the dig-ital calibration technique developed in our previous work[3], [4], a small size unit capacitor of 0.5 fF can be used forDACs, therefore power of the other components is also im-portant. Thus DAC capacitance does not scale with reso-lution like Refs. [5], [6]. For the LSB comparison in 10-bitmode, DACs operate asymmetrically. One of the comple-mentary DAC outputs is set 1LSB larger value to the otheroutput to generate a half LSB (see Fig. 3(a)) for LSB deci-sion at 10 bit mode.

Figure 3(b) shows the basic operation of the proposedresolution configurable ADC. Where samp is input sam-pling clock and CLK is internally generated comparatorclock. When CLK is high, the comparator is activated tocompare the polarity of the input signals and when CLK islow, the comparator is reset and it waits DAC settling bythe next bit decision. After the internal clock signal goeshigh the number of times equal to the number of operatingresolution, finish signal (FIN) goes high to keep CLKlow until next conversion phase. The digital selector (MUX)chooses one of d [4:10] as FIN (Fig. 3(b)). In the con-ventional approach, the internal clock period does not de-pend on the operating resolution. However, as the operatingresolution becomes low, the required DAC settling time isrelaxed. In our ADC, the internal clock period can be re-duced by controlling a delay to further increase the speed atlow resolution mode.

Tunable capacitors are connected at the output nodesof comparator to control the oset and the capacitive load.The oset control is used for DAC calibration [3], [4]. Forthe additional power saving, the capacitive load scales ac-cording to the operating resolution of ADC [6].

3. Consideration of SAR Logic

Asynchronous SAR is suited to both of fast and slow oper-ations. Because it eliminates fast external clock and signaldegradation by leakage. However internal looped circuit be-comes unstable easily and it requires carefully estimationduring circuit designs.

In the asynchronous operation, both of conventionalstatic and dynamic logic gates can be employed. The per-formance characteristic of conventional static logic gates,dynamic logic gates, and our work is summarized in Ta-ble 1. The conventional static logic gates are stable and easyto design but consume much power because of its relativecomplex structure.

On the other hand, dynamic logic gates are simple andcan be used to reduce power consumption and increase the

Table 1 Comparison of SAR controller.

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operating speed. Especially, asynchronous SAR ADC suitswith dynamic logic gates because each successive approxi-mation (SA) step automatically proceeds internally and theconversion finishes in certain time which is independent ofexternal sampling period. This avoids the problem of the failoperation of dynamic logic gates by charge leakage at lowfrequency. Additionally recent progresses of designing highecient analog building blocks increase the power ratio ofthe digital block in SAR ADC.

However, dynamic circuits are weak to noise, leakage,and timing error and it is dicult to operate properly at ultralow voltage condition because the low supply voltage en-hances those issues. Then we targeted to design circuits aslow power, fast speed as dynamic circuits and as stable asconventional static circuits.

3.1 Conventional Synchronous Static SAR Logic

Figure 4 shows the conventional static logic gate based SARcontroller. The upper D-FF line consists of a ring counterwhich controls the phase of the SAR operation. The lowerD-FF line latches the comparator signal at each phase to de-termine the internal DAC setting code and the ADC finaloutput code.

In this kind of circuit, the SAR logic uses two D-FFsfor each conversion bit. D-FF gates are relatively complexand it increases the power and area of SAR logic.

Fig. 4 Conventional synchronous SAR logic with static D-FFs.

3.2 Conventional Asynchronous Dynamic SAR Logic

As shown in Fig. 5, the dynamic logic SAR controller whichcombines the counting part with SAR part was reported [11]to further reduce circuit size and power consumption. How-ever, the timing control for asynchronous operation in thiscircuit is very critical and it cannot be used in wide fre-quency and power supply range.

The SAR logic unit in Fig. 5 consists of dieren-tial dynamic flip-flop [11] (Fig. 6(a)) and phase generator(Fig. 6(b)) to trigger the next SAR logic unit. The timingchart of the SAR operation is shown in Fig. 7.

From the sampling phase to the time previous stage((k 1)-th stage) restoring the comparator output data, [k]are low and the outputs of the flip-flop (a[k]/a[k]) are pulledup. Therefore, [k + 1] is high and [k + 1] is low. Thisstate corresponds to Init phase in Fig. 7. Then, preceding

Fig. 5 Conventional asynchronous SAR logic overview.

Fig. 6 (a) Conventional dynamic dierential flip-flop in SAR logic unit,and (b) internal phase generator in SAR logic unit.

Fig. 7 Conventional asynchronous controller operation, (a) the write margin is too short, (b) the writemargin is in best condition, (c) the write margin is too long. The arrow indicates the each trigger timingin asynchronous operation.

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(k 1)-th SAR unit asserts the [k] and k-th SAR unit be-comes data starving (DS) state. At the rising edge of inter-nal clock, the comparator starts the voltage comparison, andafter a while (tcomp), the outputs of the comparator (Cp/Cn)are decided. Depending on the Cp and Cn, one of the out-puts (a[k] or a[k]) of the k-th flip-flop goes low (write stateW in Fig. 7) and the [k + 1] changes from high to low,which turn o M3/4 and holds the flip-flop data. Just afterthat, [k + 1] changes from low to high and brings the nextSAR logic unit into DS state.

In parallel with the above SAR logic unit operations,the clock generator controls the comparator state. That is,after the comparator output is determined, the clock gener-ator starts to pull down the clock signal to reset the com-parator. Because the comparator reset time is much largerthan the SAR writing time, before the Cp and Cn go low,SAR logic unit stores comparator output. The clock gener-ator waits some time for the DAC settling and then pulls upthe clock signal to enter the next SA step.

There are two potential problems in this circuit. Thefirst one is the data retention of the dynamic flip-flop. If thepower supply voltage becomes low, the transistor operates insub-threshold region and imbalance of the leakage currentof M3/4 brings data retention error. The second problemis the critical timing control required for proper operation.As shown in Fig. 7(a), if the clock margin time (twait1) isshorter than twrite, the flip-flop in the k-th SAR unit doesnot become Hold state because the input signal (Cp, Cn)goes low before data being correctly stored. On the otherhand, if twait1 takes longer than twrite, the flip-flop in the k-th SAR unit captures data (Fig. 7(b)). However if twait1 ismuch longer than twrite, the data go through to the next bitfor wrong data storing (Fig. 7(c)). Since the twait1 and twrite isdetermined independently, critical timing control is requiredto guarantee the relation between these timing.

Moreover, in the case of low supply voltage, the com-parator takes much longer time to reset. This remains thecomparator outputs (Cp, Cn) after CLK goes low to in-crease the eective wait time and makes wrong data storing.These features are not suited for scalable ADC because widerange of frequency and power supply is required.

4. Circuit Implementation

4.1 Proposed Fast and Stable Combined SAR Logic(Asynchronous and Static)

To solve these problems, we propose low-power and sta-ble asynchronous SAR controller (Fig. 8) which operates inwide range in frequency and power supply voltage withoutsevere timing estimation.

As shown in Fig. 8, the OR gate monitors whether thecomparator is in comparison mode or reset mode and con-trols each SAR logic unit to prevent incorrect data write asshown in Fig. 7(c)). Furthermore, the dierential flip-flopis modified as shown in Fig. 9(a). In the proposed circuit,M3/4 and M9/10 form cross coupled inverters, and M5/6

Fig. 8 Proposed asynchronous SAR logic overview.

Fig. 9 (a) proposed circuit schematic of SAR Logic Unit, (b) internalphase generator of SAR Logic Unit.

Fig. 10 Proposed SAR logic operation.

are added to bypass the input transistors M1/2 in the holdmode. This topology enables the static operation in holdmode, which solves the problem of the data retention evenat ultra-low-voltage operation. To control the gates of M5/6,d[k+1] is generated by the circuit shown in Fig. 9(b). Onlyafter the comparator is reset and ready signal becomeslow, the d[k+1] goes high and the next flip-flop enters intostandby (SB) mode before going data starving (DS) mode(Fig. 10). This prevents incorrect data write into (k+1)-thSAR logic unit. The detail operation of the proposed SARcontroller is explained in the following.

During the external sampling signal (samp) is high,the ADC is in the sampling mode. The output of the flip-flop in 0-th SAR logic unit (a[0]/a[0]) are pre-charged toVDD and phase signal [1] and d[1] are low. This corre-sponds to Init state of SAR logic unit. Then [1] negatesthe flip-flop in the 1-st SAR logic unit as the same way as the0-th stage flip-flop. This flip-flop initialization propagates to

SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC447

Fig. 11 Simulated shmoo plot of write wait timing margin. Conventionalasynchronous controller only work red colored area (within dashed lines),the proposed asynchronous controller operates within blue colored area(within solid lines).

the flip-flop in the final SAR logic unit and the FIN sig-nal becomes low to ready for data conversion cycle. At thesame time, MSB bit (D[0]) is set to 0 and all the other bits(D[1:8]) are set to 1 (see Fig. 5), which is the initial valueof the SAR operation [11].

When samp goes low, the ADC begins data conver-sion. At first, [0] and d[0] goes high, and the comparatoroutput (Cp/Cn) is written into the 0-th flip-flop. After theflip-flop output (a[0]/a[0]) are determined in the write op-eration (twrite), the [1] becomes high and brings the nextSAR logic unit into SB mode. At the same time, D[0] andD[1] change and the DAC setting code is updated for nextSA step automatically. After the clock generator resets thecomparator, Cp and Cn become low to pull down the readysignal. At this moment, d[1] goes high to turn on the M5/6in 0-th flip-flop and hold the data. At the same time, d[1]also triggers the next flip-flop into DS mode by turning onthe M7/M8. Since the data sampling of the flip-flop startsonly after the output of comparator being reset, the incorrectdata write never occurs and guarantees the stable operationat wide frequency and power supply voltage range (Fig. 10).The same operation proceeds to the next SAR logic unit un-til the final unit are determined.

Figure 11 shows the shmoo plot of twait1 and VDD. Inthe previous reported SAR controller, critical timing controlis required and it strongly depends on the supply voltage.On the other hand, in our SAR controller, the timing marginis greatly relaxed.

4.2 Clock Generator and Controllable Delay Element

The circuit schematic of asynchronous clock generator in-spired by [11] is shown in Fig. 12. During the sampling sig-nal (samp) is high, the output of delay element (DE) andFIN are low. Therefore, the internal asynchronous clock(CLK) stays low. When samp becomes low, CLK im-mediately goes high to start data conversion cycle. When thefirst comparison finishes, one of the comparator output (Cpor Cn) goes high and pull down the output of completion de-tector (CD). This falling action in the CD immediately pullsdown the CLK to start reset operation. On the other hand,

Fig. 12 Clock generator architecture.

Fig. 13 Delay element in the asynchronous clock generator, (a)schematic of delay element (b) node waveform of the delay element. (c)capacitive voltage divider (CVD).

this falling action is delayed in DE and keeps CD output lowby tloop1. After it takes tloop1, NOR gate pulls up and CD getsready for next comparison. Then it goes to 2nd delay loopfor the remaining DAC settling. After the delay (tloop2) byDE, the output of DE is pulled up and CLK goes high thenSAR controller enters next SA step.

Here, tloop1 and tloop2 determines the asynchronous pe-riod. The asynchronous operation is automatically triggeredby the combination of the proposed SAR logic and the clockgenerator as long as the delay tloop1 is longer than compara-tor reset time. Generally speaking, data latching time isenough short (see Fig. 11) than the comparator reset timebecause comparator has large load capacitance.

Delay element is one of the most important circuits inasynchronous SAR ADCs. For the fast operation, the delayin clock generator should be minimized. However, too smalldelay leads to incomplete settling in DACs and degrades theaccuracy especially in high resolution mode. To obtain theoptimum delay, the delay time can be controlled during theSAR operation [2], [14]. However, the wide tuning range ofdelay element causes large power and area. Therefore wedeveloped delay element with small size, low power, andwide delay control range.

Figure 13(a) shows the circuit schematic of the pro-

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Fig. 14 Delay element Comparison (a) Capacitor load control, (b) pro-posed CVD method, (c) Delay element power eciency against the re-quired delay amount.

posed delay element. As shown in Fig. 13(c), it has internaltwo 5-bit controlled capacitive voltage dividers (CVD) tocontrol the gate voltage amplitude in node B and C. Thosevoltages can be expressed by using capacitive coupling asfollows,

VB =CA

CA + CBVDD (1)

By controlling the voltage dividing ratio of CVDP, Vgsof MP can be changed and rise time of delay element can bechanged. On the other hand, by changing the dividing ratioof CVDn, Vgs of MN can be changed and fall time of delayelement can be changed.

Especially at low voltage operation (near sub-thresholdregion), the drivability of the MOSFETs strongly dependson the gate voltage. Therefore, by controlling the gate volt-age by using CVD, the wide delay range can be ecientlyobtained. The power of the delay element is almost constantof 3 nW/MHz at 0.4 V supply voltage with all the delay timefrom 12 nsec to 150 nsec in the circuit simulation. The diearea of whole clock generator (including delay element) oc-cupies only 12 m 8 m.

Figure 14 compares the required power to realize thedelay element by using simple capacitive load and our ca-pacitive voltage divider. If simple variable capacitive load isused, the power consumption and area increase proportionalto the required delay amount. On the other hand, the powerconsumption of our circuit is only 3 nW/MHz and does notdepend on the required delay. Another way to realize thewide delay range is to use current starved inverter. Howeverthe current starved inverter requires current source circuitwhich is dicult to design at ultra low voltage with smallcircuit area. The total capacitance of the delay element isonly 22 fF.

4.3 DAC Calibration Circuit and Method

The principle of the DAC calibration is based on capacitanceto voltage transfer [15]. Figure 15(a) shows the circuit im-plementation of the DAC calibration unit (DCU). The DCU

Fig. 15 (a) Circuit implementation of the DAC calibration unit (DACCAL in Fig. 3(a) and its operation, (b) DAC calibration operation.

is placed between SAR logic and DAC (Fig. 3(a)) to provideDAC the calibration setting code during calibration mode(CAL=1).

The DCU provides initial state signal (INI[0:3] inFig. 15(b)) and swapped state signal (SWA[0:3]). Dur-ing sampling phase, DAC samples the comparator commonmode level with the digital input of INI[0:3] for example,INI[0:3]=[0111] for MSB calibration. When samp goeslow (conversion phase), the sampling switch turns o andafter that the digital code is swapped to SWA[0:3]=[1000].Those two digital codes are set to the same amount of capac-itance ideally. Then, the DAC output should be the same. Ifthe DAC output becomes positive, the total capacitance ofthe capacitors connected to SWA[0:3] is larger than that ofconnected to INI[0:3].

The internal oset calibrated comparator detects thevoltage polarity to decide which side capacitor has larger ca-pacitance. Then connections of sub capacitors are changedto balance the capacitance between the capacitors connectedto INI[0:3] and SWA[0:3] through binary search algorithm.After the capacitance becomes balanced, it moves to nextbit calibration. Then INI[0:3] is set to [0011] and SWA[0:3]is set to [0100]. The calibration procedure is done by LSB([0001] = [0010]). Because SAR logic outputs do not dealwith the DAC during calibration (see Fig. 15(a)), the com-parator outputs can be stored to SAR logic. The stored dataread out to o chip as the same way to read out ADC out-put and procedure calibration by o chip in this work. Aftercalibration, CAL is set to 0 and the DCU works just buers.

4.4 SAR ADC Building Block Power Budget

Figure 16 shows the simulated power budget of the con-ventional SAR ADC (Fig. 16(a)) and the proposed SARADC (Fig. 16(b)) at 10 bit mode and 0.4 V supply volt-age. Only SAR logic and delay element in clock gener-ator are the dierent between the two. The conventionalstatic SAR ADC (Fig. 16(a)) employed 128 fF capacitiveload delay element to achieve almost equal delay amount(see Fig. 14). In this condition, SAR logic in [11] did not

SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC449

Fig. 16 (a) power budget of the conventional SAR ADC which usesstatic SAR logic and capacitive load delay element, (b) power budget ofthe proposed ADC which uses the proposed SAR logic and delay element.The power is normalized with the conventional SAR ADC.

work because of too long write margin time problem (seeFig. 7(c)). Calibration in Fig. 16 means power consump-tion of DCU (Fig. 3(a) and Fig. 15(a)). Therefore DAC re-lated block consumes relative large in this ADC.

The proposed SAR logic and delay element requiresonly 1/3 power and totally 25% power improvement wasachieved.

5. Measurement Results

Figure 17 shows the microphotograph of the developedADC core. It has been designed and fabricated in a 40 nmstandard CMOS technology and the ADC active area occu-pies only 100 m 130 m. Only a single power supply isrequired for the circuit operation. The covered power supplyranges from 0.4 to 1 V.

Dierential nonlinearity (DNL) and integral nonlin-earity (INL) were evaluated based on code-density mea-surement. With a 100 kHz sinusoidal signal at 160 kS/secconversion rate, the measured peak DNL and INL were+1.67/1 LSB and to +1.43/1.79 LSB, respectively at10 bit mode by using DAC calibration technique proposedin [3], [4] (Fig. 18). The unit capacitance of 0.5 fF was em-ployed and it divided to 0.4 fF main capacitor and 0.1 fF subcapacitor. The maximum and minimum DNL/INL charac-teristic against the operational resolution is shown in Fig. 19.The proposed ADC employed asymmetry DAC operationat 10 bit mode to halve the number of unit capacitors com-pared to ordinary 10 bit binary weighted capacitor DAC.This makes the calibration step size twice eectively andmakes it dicult to calibrate at 10 bit mode operation. Thisdirectly aects the SNDR of the proposed ADC at higher bitmode.

Figure 20 shows the measured FFT plot with a 100 kHzsinusoidal input, and sampling rate of 160 kHz. Becauseof the instrument used in this experiment, the minimuminput signal frequency is 100 kHz. Therefore higher thanNyquist frequency (80 kHz) signal is put into the ADC.SNDR and spurious free dynamic range (SFDR) of the ADCare 49.8 dB and 57.5 dB, respectively.

Figure 21 shows the relation between the SNDR and

Fig. 17 Chip photograph.

Fig. 18 Measured (a) DNL and (b) INL. With sampling rate of160 kS/sec and input frequency is around 100 kHz, measured with 16 timesaveraged 4096-point input (65536 data) at 0.4 V and 10 bit mode.

Fig. 19 Maximum and minimum DNL/INL against operation resolution.With sampling rate of 160 kS/sec and input frequency is around 100 kHz,measured with 16 times averaged 4096-point input (65536 data) at 0.4 V.

Fig. 20 Measured 4 times averaged 4096-point FFT plot (16384 data)with sampling rate of 160 kS/s within under sampling rate input of around100 kHz (under sampling) at 0.4 V supply voltage.

Fig. 21 ENOB against delay code at supply voltage of 0.4 V. The largerdelay code indicates larger delay amount in the clock generator.

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Fig. 22 SNDR against Sampling Frequency with 100 kHz input (belowsampling frequency of 200 kHz) and Nyquist frequency (sampling fre-quency of above 200 kHz).

Fig. 23 FoM against sampling frequency with 100 kHz input (belowsampling frequency of 200 kHz) and Nyquist frequency (sampling fre-quency of above 200 kHz).

Fig. 24 SNDR against sampling frequency at various power supplyvoltage.

delay setting code in the clock generator. The delay in-creases as the delay setting code is increased. In high res-olution mode, the SNDR degrades as the delay decreasesbecause the DAC settling error becomes fatal compared tothe low resolution mode.

Figure 22 shows the measured SNDR against samplingfrequency at various resolution modes. The delay code isset at optimum value which keeps good SNDR at each res-olution mode. By optimizing delay time against resolution,the sampling frequency can be increased as the operatingresolution is lowered.

Figure 23 shows the ADC figure of merit (FoM) againstsampling frequency at dierent resolution mode. At eachresolution mode, as the sampling frequency exceeds thespeed limitation, the SNDR and FoM begin to degrade. Thebest FoM of 3.4 fJ/conv. was achieved at 10 bit mode withsampling frequency of 160 kS/s.

From Figs. 18 to 23, all the measurements were carriedout at power supply voltage of 0.4 V.

Fig. 25 FoM against sampling frequency at various power supplyvoltage.

Table 2 Performance summary.

The performance of the fabricated ADC was also mea-sured at dierent power supply voltage.

The relation between the SNDR and maximum sam-pling frequency (Fs max) at each resolution mode is shownin Fig. 24 with the power supply voltage of 0.4, 0.5, 0.7and 1.0 V. Fs max is defined as the maximum sampling fre-quency which all the conversion cycle is completely finishedat each resolution mode. For example, at VDD of 0.4 V, itcorresponds to the envelope of all the curves in Fig. 22. Ifthe power supply is increased to 1.0 V, ENOB of 8.7 bit is

SHIKATA et al.: A 410 BIT, 0.41 V POWER SUPPLY, POWER SCALABLE ASYNCHRONOUS SAR-ADC451

Fig. 26 Performance (Fs) comparison with the previous reportedscalable ADCs.

Fig. 27 Performance (FoM) comparison with the previous reportedscalable ADCs.

obtained at 10 MHz and the ADC operates at 100 MHz with4 bit resolution mode.

Figure 25 shows the FoM against maximum samplingfrequency at VDD of 0.4 V, 0.5 V, 0.7 V, and 1.0 V. Even at1.0 V, the ADC achieves FoM lower than 10 fJ/conv.step at10 MHz and ENOB of 8.7 bit.

Table 2 summarized the proposed ADC performance.Figures 26 and 27 show the performance comparison withthe previous reported wide operation range SAR ADCs [5],[6]. In our ADC, if high speed operation is important, highersupply voltage can be used. On the other hand, if powereciency is emphasized, ultra-low voltage operation can bechosen.

6. Conclusion

By using modified SAR logic and wide range delay element,the proposed ADC reduced total power by 25% at 0.4 V and10 bit mode operation compared to the conventional SARlogic using static logic gates and the delay element usingcapacitive load.

The prototype ADC achieved high eciency of below100 fJ/conv. in 410 bit mode at 0.40.7 V. The best e-ciency is achieved at 0.4 V supply and 10 bit mode opera-tion with sampling rate of 160 kS/sec. The achieved SNDRis 49.8 dB and the power consumption is 0.14 W resultingFoM of 3.4-fJ/conversion step. And in the 4-bit mode and1 V supply, the ADC operates up to 100 MHz.

Acknowledgments

This work was carried out as a part of the Extremely LowPower (ELP) project supported by METI and NEDO.

References

[1] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E.A.M.Klumperink, and B. Nauta, A 10-bit charge-redistribution ADCconsuming 1.9 W at 1 MS/s, IEEE J. Solid-State Circuits, vol.45,no.5, pp.10071015, May 2010.

[2] R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, A 40 nm50 S/S8 MS/S ultra low-voltage SAR ADC with timing optimizedasynchronous clock generator, IEEE ESSCIRC Dig., pp.471474,Sept. 2011.

[3] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, A 0.5 V1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level compara-tor in 40 nm CMOS, IEEE, Symp. VLSI Circuits Dig., pp.262263,June 2011.

[4] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, A 0.5 V1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level compara-tor in 40 nm CMOS, IEEE J. Solid-State Circuits, vol.47, no.4,pp.10221030, April 2012.

[5] M. Yip and A.P. Chandrakasan, A resolution-reconfigurable 5-to-10b 0.4-to-1 V power scalable SAR ADC, IEEE ISSCC Dig.,pp.190192, Feb. 2011.

[6] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. De Groot, A 7-to-10b 0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step, IEEE ISSCC Dig., pp.472474, Feb. 2012.

[7] P.J.A. Harpe, C. Zhou, Y. Bi, N.P. van derMeijs, X. Wang, K. Philips,G. Dolmans, and H. de Groot, A 26 W 8 bit 10 MS/s asynchronousSAR ADC for low energy radios, IEEE J. Solid-State Circuits,vol.46, no.7, pp.15851595, July 2011.

[8] Y. Chen, S. Tsukamoto, and T. Kuroda, A 9-bit 100-MS/s 1.46-mWtri-level SAR ADC in 65 nm CMOS, IEICE Trans. Fundamentals,vol.E93-A, no.12, pp.26002608, Dec. 2010.

[9] J.J. Kang and M.P. Flynn, A 12b 11 MS/s successive approximationADC with two comparators in 0.13 m CMOS, IEEE Symp. VLSICircuits Dig., pp.240241, June 2009.

[10] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13 m CMOS Process, IEEE, Symp.VLSI Circuits Dig., pp.236237, June 2011.

[11] J.-H. Tsai, Y.-J. Chen, M.-H. Shen, and P.-C. Huang, A 1-V, 8b,40 MS/s, 113 W charge-recycling SAR ADC with a 14 W asyn-chronous controller, IEEE, Symp. VLSI Circuits Dig., pp.264265,June 2011.

[12] H. Park, K.Y. Nam, D.K. Su, K. Vleugels, and B.A. Wooley, A0.7-V 870-mW digital-audio CMOS sigma-delta modulator, IEEEJ. Solid-State Circuits, vol.44, no.4, pp.10781088, April 2009.

[13] M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, A low-noiseself-calibrating dynamic comparator for high-speed ADCs, IEEEASSCC Dig., pp.269272, Nov. 2008.

[14] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, A 10b50 MS/s 820 W SAR ADC with on-chip digital calibration, IEEEISSCC Dig., pp.384385, Feb. 2010.

[15] J.L. McCreary and D. Sealer, Precision capacitor ratio measure-ment technique for integrated circuit capacitor arrays, IEEE Trans.Instrum. Meas., vol.IM-28, no.1, pp.1117, March 1979.

452IEICE TRANS. FUNDAMENTALS, VOL.E96A, NO.2 FEBRUARY 2013

Akira Shikata received B.S. and M.S.degrees in electronics and electrical engineer-ing from Keio University, Yokohama, Japan, in2008 and 2010, respectively, where he is cur-rently working toward the Ph.D. degree. Hiscurrent research interests lie in low-power andlow-voltage data converters.

Ryota Sekimoto received B.S. degrees inelectronics and electrical engineering from KeioUniversity, Yokohama, Japan, in 2011, wherehe is currently working toward the M.S. degree.Since 2010, he has been working on ultra lowpower ADC for wireless sensor network.

Kentaro Yoshioka received B.S. degrees inelectronics and electrical engineering from KeioUniversity, Yokohama, Japan, in 2012, wherehe is currently working toward the M.S. degree.His current research interests lie in low voltageand high speed data converters.

Tadahiro Kuroda received the Ph.D. de-gree in electrical engineering from the Univer-sity of Tokyo, Tokyo, Japan, in 1999. In 1982,he joined Toshiba Corporation, where he de-signed CMOS SRAMs, gate arrays and stan-dard cells. From 1988 to 1990, he was a Vis-iting Scholar with the University of California,Berkeley, where he conducted research in thefield of VLSI CAD. In 1990, he was back toToshiba, and engaged in the research and devel-opment of BiCMOS ASICs, ECL gate arrays,

high-speed CMOS LSIs for telecommunications, and low-power CMOSLSIs for multimedia and mobile applications. He invented a VariableThreshold-voltage CMOS (VTCMOS) technology to control VTH throughsubstrate bias, and applied it to a DCT core processor and a gate-arrayin 1995. He also developed a Variable Supply-voltage scheme using anembedded DC-DC converter, and employed it to a microprocessor coreand an MPEG-4 chip for the first time in the world in 1997. In 2000,he moved to Keio University, Yokohama, Japan, where he has been aprofessor since 2002. He was a Visiting Professor at Hiroshima Univer-sity, Japan, and the University of California, Berkeley. His research inter-ests include low-power, high-speed CMOS design for wireless and wire-line communications, human computer interactions, and ubiquitous elec-tronics. He has published more than 200 technical publications, includ-ing 60 invited papers, and 21 books/chapters, and has filed more than100 patents. Dr. Kuroda served as the General Chairman for the Sympo-sium on VLSI Circuits, the Vice Chairman for ASP-DAC, sub-committeechairs for A-SSCC, ICCAD, and SSDM, and program committee mem-bers for ISSCC, the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC,ISLPED, SSDM, ISQED, and other international conferences. He is a re-cipient of the 2005 P&I Patent of the Year Award, the 2006 LSI IP DesignAward, the 2007 ASP-DAC Best Design Award, the 2009 IEICE Achieve-ment Award, and the 2011 IEICE Society Award. He is an IEEE Fellow, anelected AdCom member for the IEEE Solid-State Circuits Society and anIEEE SSCS Distinguished Lecturer.

Hiroki Ishikuro received the B.S., M.S.and Ph.D. degrees in electrical engineering fromthe University of Tokyo, Tokyo, Japan, in 1994,1996, and 1999, respectively. In 1999, hejoined the System LSI Research and Develop-ment Center, Toshiba Corp., Kawasaki, Japan,where he was involved in the development ofCMOS RF and mixed-signal circuits for wire-less interface chips. In 2006, he joined the De-partment of Electrical Engineering at Keio Uni-versity as an assistant professor and started a re-

search on high-speed inductive-coupling links for 3-D chip integration andnon-contact connector. He is currently an associate professor of Keio Uni-versity, and focuses on the mixed-signal circuit and system designs for ex-tremely low-power interfaces. He is a member of the Technical ProgramCommittee for Symposium on VLSI Circuits.

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 300 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth 8 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /FlateEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 1200 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /FlateEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile () /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

/Description > /Namespace [ (Adobe) (Common) (1.0) ] /OtherNamespaces [ > /FormElements false /GenerateStructure false /IncludeBookmarks false /IncludeHyperlinks false /IncludeInteractive false /IncludeLayers false /IncludeProfiles false /MultimediaHandling /UseObjectSettings /Namespace [ (Adobe) (CreativeSuite) (2.0) ] /PDFXOutputIntentProfileSelector /DocumentCMYK /PreserveEditing true /UntaggedCMYKHandling /LeaveUntagged /UntaggedRGBHandling /UseDocumentProfile /UseDocumentBleed false >> ]>> setdistillerparams> setpagedevice