diplexing distributed power amplifier for mobile applicationsdiplexing distributed power amplifier...
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Diplexing Distributed Power Amplifier for
Mobile Applications
Der Technischen Fakultät
der Universität Erlangen-Nürnberg
zur Erlangung des Grades
DOKTOR-INGENIEUR
Vorgelegt von
M. Sc. Wei Wang
Erlangen, März 2012
Verteilte Mehrtor Leistungsverstärker für
Mobilfunkanwendungen mit
Diplexerfunktion
Als Dissertation genehmigt von
der Technischen Fakultät
der Universität Erlangen-Nürnberg
Tag der Einreichung: 11. 08. 2011
Tag der Promotion: 19. 03. 2012
Dekanin: Prof. Dr.-Ing. Marion Merklein
Berichterstatter: Prof. Dr.-Ing. Georg Fischer
Prof. Dr.-Ing. Wolfgang Heinrich
I
Acknowledgements
My foremost appreciation goes to Mr. Christian Korden at TDK-EPC Corporation, Munich
and Prof. Dr.-Ing. Robert Weigel, the Chair of Electronics Engineering at University of
Erlangen-Nuremberg, Germany. They gave me the opportunity to work on this interesting
topic.
I also wish to express my gratitude to Prof. Dr.-Ing. Georg Fischer, who has supervised me
throughout my work. Without his helpful guidance and instruction I wouldn’t have finished
my dissertation.
My sincere thanks also go to Dr. Ir. Léon van den Oever at Radio Semiconductor B.V.
Nijmegen, the Netherlands. As one of the most experienced engineers in the field of mobile
phone power amplifier, he always gave me valuable suggestions and instructions.
Furthermore, I would like to thank my colleagues at the chair of Electronics Engineering at
the University of Erlangen-Nuremberg and at TDK-EPC Corporation for all their assistance
during my PhD study.
Finally I would like express my appreciation to my parents and wife for their support,
understanding and love.
II
Abstract
For the purpose of multiband mobile phone power amplifier (PA) design, the prospect of
using a distributed amplifier (DA) has been investigated, which over the last 50 years is well
known for its excellent broadband behaviour. In order to better adapt the DA to mobile phone
PA applications, a new concept is proposed, namely the linear diplexing tapered DA. To
verify this concept, the following designs have been investigated:
Single stage PCB demonstrator
Two-stage on-chip design, which has tapered DA as driver and the diplexing
tapered DA as a final PA stage
Due to the unique properties of the (diplexing tapered) DA, some commonly used techniques
in Single-Ended-PA designs are not applicable. Therefore modifications and adaptations are
made. Furthermore, the supplementary properties of the diplexing tapered DA are discussed:
Stage bypass for PAE enhancement of DA during large back-off (BO) operation
Due to multiple feedback loops and nonlinear devices, large signal and parametric
stability are characterised by system identification method
Due to the inferior linearity of DA, a special dynamic biasing circuit to
compensate for the gain expansion is proposed
The ability to apply spectrum aggregation and load balancing techniques
III
Kurzfassung
In der vorliegenden Arbeit wurde für die im Mobilfunk eingesetzten
Multibandleistungsverstärker (Multiband PA) die Verwendung von verteilten Verstärker
(Distributed Amplifier - DA) untersucht, die seit langem für ihre ausgezeichnete
Breitbandigkeit bekannt sind. Als neues Konzept wurde der linear verteilte Mehrtorverstärker
mit Diplexerfunktion verwendet. Zur Überprüfung der Funktionsweise wurde ein einstufiger
PCB-Demonstrator mit diskreten Bauteilen aufgebaut und charakterisiert, sowie ein
zweistufiges IC-Design mit einem tapered DA als Treiber und einem tapered Mehrtor-DA
mit Diplexerfunktion als Endstufe verifiziert.
Aufgrund der speziellen Eigenschaften von verteilten Verstärkern mit Diplexerfunktion
lassen sich einige bekannte und häufig verwendete Techniken zur Verbesserung von
Linearität und Wirkungsgrad - wie sie häufig zur Auslegung von Single-Ended-PAs
verwendet werden, nicht anwenden. Daher wurden folgende Techniken adaptiert und neu in
Schaltung und Simulation eingeführt:
Bypass-Stufe zur Erhöhung des Verstärkerwirkungsgrads (PAE) im Back-Off
(BO)
Analyse der parametrischen und Großsignalstabilität
Dynamische Bias-Schaltung zur Linearitätsverbesserung bzw. zur Kompensation
der Verstärkungsexpansion
Berücksichtigung von Last-Balancierung- und Spektrum-Aggregationstechniken
IV
Table of contents
Acknowledgements ................................................................................................................................ I
Abstract................................................................................................................................................. II
List of abbreviations ........................................................................................................................... VI
1. Introduction................................................................................................................................... 1
2. Power amplifier fundamentals ...................................................................................................... 3
2.1. PA characteristics .................................................................................................................. 3
2.1.1. Efficiency ....................................................................................................................... 4
2.1.2. Gain ................................................................................................................................ 4
2.1.3. Maximal output power and back-off .............................................................................. 5
2.1.4. Linearity ......................................................................................................................... 6
2.2. Operation class comparison: Class A and Class AB .............................................................. 9
3. The power amplifier bandwidth .................................................................................................. 12
3.1. Transistor’s figure of merits ................................................................................................. 12
3.2. Matching limitation.............................................................................................................. 14
3.2.1. Bode-Fano limit ........................................................................................................... 14
3.2.2. Limitation of LC matching ........................................................................................... 15
3.3. Broadband amplifier topologies ........................................................................................... 18
3.3.1. Common source (CS) amplifier .................................................................................... 19
3.3.2. Lossy matched (LM) amplifier ..................................................................................... 19
3.3.3. Shunt negative feedback (FB) amplifier ....................................................................... 20
3.3.4. Balanced amplifier (BA) .............................................................................................. 20
3.3.5. Distributed amplifier (DA) ........................................................................................... 21
3.3.6. Comparison of topologies............................................................................................. 21
4. PAE enhancement method .......................................................................................................... 26
4.1. Dynamic bias ....................................................................................................................... 26
4.2. Stage bypass in different circuit topologies.......................................................................... 28
4.2.1. Stage bypass in conventional multistage PA ................................................................ 28
4.2.2. Linear switched Doherty amplifier ............................................................................... 29
4.2.3. Stage bypass in BA. ..................................................................................................... 30
4.2.4. Distinguished stage bypass in DA ................................................................................ 31
4.3. Spectrum aggregation and load balancing ............................................................................ 31
V
5. Distributed Amplifier for mobile phone ...................................................................................... 34
5.1. Introduction ......................................................................................................................... 34
5.2. Design procedure of tapered DA.......................................................................................... 35
5.3. The linearity of DA .............................................................................................................. 38
5.4. Stability consideration ......................................................................................................... 39
5.5. Distinguished stage bypass in DA........................................................................................ 43
6. Directional Distributed Amplifier based on CRLH structure ...................................................... 48
6.1. CRLH-TL ............................................................................................................................ 48
6.2. The diplexing DA ................................................................................................................ 49
6.3. Linear tapered diplexing DA................................................................................................ 51
6.4. Circuit application discussion .............................................................................................. 56
6.5. PCB demonstrator ................................................................................................................ 56
6.5.1. Circuit description ........................................................................................................ 57
6.5.2. Measurement results ..................................................................................................... 58
6.6. On-chip demonstrator .......................................................................................................... 66
6.6.1. Circuit description ........................................................................................................ 66
6.6.2. Simulation results ......................................................................................................... 68
6.7. Triplexing and multiplexing DA opportunity....................................................................... 71
7. Conclusions and future work ...................................................................................................... 74
Appendix A: The mathematical expression of IMD............................................................................ 76
Appendix B: The system identification process .................................................................................. 77
Biboliography ..................................................................................................................................... 80
Author’s publications .......................................................................................................................... 88
VI
List of abbreviations
AC Alternating Current
ACLR Adjacent Channel Leakage Ratio
ACPR Adjacent Channel Power Ratio
ADS Advanced Design System
AV Low frequency voltage gain
BO Back-off level
BW Band Width
C Capacitance
CRLH Composite Right/Left- Handed structure
DA Distributed Amplifier
DC Direct Current
EM ElectroMagnetic
EVM Error Vector Magnitude
FEM Front End Module
FET Field Effect Transistor
fmax Maximal oscillation frequency
ft Maximal transit frequency
GaAs Gallium Arsenide
GSM Global System for Mobile Communications
GT Transducer power gain
HB Harmonic Balance or High Band
HBT Hetrojunction Bipolar Transistor
HSPA High Speed Package Access
I Current
IM Intermodulation
VII
IMN Input Matching Network
ISO Isolation
LB Low Band
LH Left Handed structure
LSG Large Signal Gain
LTE Long Term Evolution
MAG Maximal Available Gain
MEMS Micro- Electro Mechanical System
OFDM Orthogonal Frequency Division Multiplexing
OMN Output Matching Network
PA Power Amplifier
PAE Power Added Efficiency
PCB Printed Circuit Board
PHEMT Pseudo High Electron Mobility Transistor
Q Quality factor
QAM Quadrature Amplitude Modulation
QPSK Quadrature Phase Shift Keying
RF Radio Frequency
RH Right Handed structure
RX Transceiver
SC-FDMA Single Carrier Frequency Division Multiple Access
SDR/CR Software Defined Radio/Cognitive Radio
TX Transmitter
TL Transmission Line
TWA Travelling Wave Amplifier
UMTS Universal Mobile Telecommunications System
Vcc Supply Voltage
VIII
VSWR Voltage Standing Wave Ratio
WCDMA Wideband Code Division Multiple Access
WLAN Wireless Local Area Network
Z0 Characteristic impedance
β Propagation constant
Γ Reflecting coefficient
ηD Drain efficiency
λ Wavelength
θ Phase shift
ω Angular frequency
1. Introduction
1
1. Introduction
Over the last decade, the expansion in the mobile phone market became one of the global
technology driving forces. As evidence of this, over 1.2 billion mobile phones were sold in
2009, and the growth of this market did not stop even during the economic crisis. After the
emergence of the 3rd
generation (3G) or high speed packet access (HSPA, 3.5G) mobile
phone standards, the multiple standards capability of GSM, 3G and 3.5G has been commonly
adopted. As the technology evolves, the additional standard Long Term Evolution (LTE)
should also be supported in the future.
As a portable device, the operation of mobile phone should be possible all over the world
(international roaming), despite each region using different frequency bands. In Figure 1.1, a
standard front-end module (FEM) supporting quad-band GSM (850/900/1800/1900 MHz)
and triple-band WCDMA (2100/1900/850 MHz) is depicted [1]. In this module, 5 power
amplifiers (PA), 3 duplexers, 6 filters and a Single-Pole-Nine-Throw (SP9T) switch are
included.
For the ease of customer, additional services such as Global Positioning System (GPS),
WLAN (IEEE802.11 a/b/g/n) and Bluetooth (IEEE 802.15.1) are added to the single mobile
phone. These additional functionalities are accompanied by further RF building blocks.
Moreover, power added efficiency (PAE) performance is an important criterion because it is
directly linked to talk and standby time. For this reason, additional complexity has to be
added.
However, with regards to the mobile phone manufacturer, an increase in number of features
can only be realized by multiple paths of single band single standard and unit selection.
Apparently this is a trade off against fabrication cost or time to market. It therefore becomes
clear that new concepts are needed to simplify this architecture.
Some novel architecture has already been introduced in [2-4]. The main concept is that each
function is realized by a single building block for all frequency bands and standards. Passive
building blocks like the filter, duplexer, coupler and antenna are realized by metamaterial
structures or tuneable devices. Multiband capability of active building blocks like the low
noise amplifier (LNA), frequency synthesizer, and so on, is realized by the incorporation of
these novel passive building blocks or broadband circuit topologies. As the multiband PA is
one of the key building blocks for the new architectures, this dissertation focuses on its
approaches.
Many multiband PA approaches have been reported, e.g. distributed amplifier (DA) [5,6],
balanced amplifier [7-12], dual- and multiband matching [13-17], tuneable and frequency
agile matching networks based on switches or varactors [18-21], impedance tracking [22] and
so on. Although all the approaches partially demonstrate the opportunities available to
achieve the final goal, they all have huge drawbacks and are hence not commonly adopted.
1. Introduction
2
UMTS B2 TX
UMTS B5 TX
LB TX
GSM 850,900HB TX
GSM 1800, 1900
GSM 1900 RX
GSM 1800 RX
GSM 850 RX
GSM 900 RX
UMTS B1 TX
UMTS B5 RX
UMTS B2 RX
UMTS B1 RX
Figure 1.1: The block diagram of a standard front-end module with quad-band GSM and
triple-band UMTS capability.
A new concept of diplexing DA has been proposed by Mata and Xie [23,24] (Figure 1.2).
The new structure inherits the broadband nature of DA. Following incorporation with the
Composite Right Left Handed Transmission Line (CRLH-TL) structure, the amplified signal
can be automatically diplexed to the corresponding output ports according to the input
frequency. In order to improve its performance in mobile phone application, an additional
feature of tapering has been added in this work. Design, application and performance
improvements especially in terms of efficiency and linearity are the main objective of this
dissertation.
Linear Tapered
Diplexing DA
RFinLB OMN
HB OMN
RFout1
RFout2
Figure 1.2: The proposed single PA solution for multiband UMTS front-end module.
2.1. PA characteristics
3
2. Power amplifier fundamentals
For successful mobile phone communication, the PA boosts the small digitally modulated
signal to an adequate output power level before being radiated by the antenna. It is the most
power consuming device in the whole transmitter chain, and hence dominates the
performance of the complete system. In PA design it is always a challenge to facilitate higher
linearity, efficiency, bandwidth, lower manufacturing cost, and so on [25-30] .
2.1. PA characteristics
In Figure 2.1 a typical common source power amplifier is depicted. The transistor is the basic
component responsible for the power amplification. GaAs enhancement mode Pseudo High
Electron Mobility Transistor (E-PHEMT) and Heterojunction Bipolar Transistor (HBT) are
the mainstream technologies for mobile phone PA design [31,32]. Since current signal is
required at the input for HBT, it is not adequate for class AB DA design. Therefore only E-
PHEMT is envisaged in this work.
DC block
RFin
Z0
IMN
RF bypass
OMN Load
ZL
RL
PoutPdiss
DC block
VCC
RF bypass Vbias
RF
choke
RF
choke
Figure 2.1: Schematic of a common source power amplifier.
The Input Matching Network (IMN) and Output Matching Network (OMN) are inserted
between the source, load and the transistor, respectively. As a result, the desired impedances
are presented to the transistor at the fundamental and optionally the harmonic frequencies.
The input of the transistor is biased through an RF choke, which determines the operation
class of the PA. The input signal is applied through a DC-block capacitor to the transistor’s
gate. The DC supply feeds the transistor’s drain through another RF choke.
2.1. PA characteristics
4
2.1.1. Efficiency
Part of the supplied DC power is converted to a RF signal and flows to the load at
fundamental and harmonic frequencies. The other part is wasted by heating the transistor.
The ratio of the conversion is defined as the drain efficiency ( ):
Equation 2.1
where Pout equals the RF power delivered to the load at fundamental frequency and Pdc
reflects the power supplied by the DC source. Since the drain efficiency does take into
account the RF power fed into the PA, the power added efficiency (PAE) is a more important
parameter, which is defined as:
Equation 2.2
where Pin denotes the power of the input signal and GT is the transducer power gain of the PA.
2.1.2. Gain
The transducer power gain GT is defined as:
Equation 2.3
It is determined by the transistor’s ability to amplify a small signal, in other words the
transconductance (gm):
|
Equation 2.4
where VGS, VDS and IDS(VGS) are the DC voltage and current. The gm is a strong non-linear
function of the bias voltage VGS ( Figure 2.2). For small signal amplification, the gm is
constant within an infinitesimal small range and the GT is only a function of the gate bias
voltage VGS. For the case of a large signal excitation, gm(VGS) is not constant during the input
voltage swing, and hence the large signal gain (GT) is also dependent on the probability
density function (pdf) of the input voltage swing duration. As a result, it is not constant as
input power changes.
2.1. PA characteristics
5
0.3 0.6 0.9 1.20.0 1.5
100
200
300
400
0
500
-1000
-500
0
500
-1500
1000
VGS [V]
Gm
[m
S]
Gm
3 [m
S/V
2]
Ig
m3
[mS
/V2]
gm
[mS
]
IVgs [V]
Figure 2.2: The gm and gm3 of a typical E-PHEMT transistor (ATF541m4) from DC
measurement.
In Figure 2.3, a typical class AB gain response is presented.
-3 2 7 12 17-8 22
5
10
15
20
25
30
0
35
11
12
13
14
10
15
RFpower
dB
m(V
load[1
],Z
load[0
]) P_gain
_tra
nsducer
I
Gain
[dB
]P
out[d
Bm
]
Pin [dBm]
1dB gain
compression
PsatP1dB
BO
Figure 2.3. The AM/AM, gain characteristics and the definition of P1dB, Psat and back-off.
2.1.3. Maximal output power and back-off
The maximal available output power, or the saturation power (Psat) is an important issue for
every standards. On one hand it ensures that communication can work even in the worst
environment, and on the other hand, for a linear modulation scheme, a specific back-off (BO)
power level is mandatorily reserved between the maximal average linear output power and
the Psat, so that the symbol with peak power can be correctly amplified. For a mobile phone
PA, due to the small battery supply voltage (typically 3.6V for a lithium battery), after
properly choosing the transistor the Psat is determined by the load impedance:
( )
Equation 2.5
2.1. PA characteristics
6
where Vk denotes the knee voltage of the transistor (typical 0.4V for GaAs E-PHEMT). In
order to deliver roughly 1W maximal output power for typical applications, the load
impedance is as low as a few ohms.
There is another important point called the 1dB compression point (P1dB), where the gain is
1dB less than the peak gain (Figure 2.3). Up to this point the PA is quasi-linear.
2.1.4. Linearity
The classical case is the GMSK modulation used in GSM, which has a constant envelope and
therefore does not need linear amplification. As high data rate communication was adopted,
modern shaped-pulse digital modulations like QPSK, QAM and CDMA were adapted to
improve the spectrum efficiency. In these applications, the signal must be amplified linearly
to ensure its own successful communication of and that of its neighbour [26,33].
The transistor is always a non-linear device, even if the output power is much smaller than
P1dB. When an input voltage swing is applied at the transistor’s gate, the amplified drain
source current Ids contains unavoidably non-linear components. Generally there are three
types of non-linear phenomenon.
AM/AM and AM/PM distortion
The first type of non-linearity is the gain and phase distortion. As the input power level
changes, the gain and phase of the output signal changes correspondingly. This phenomenon
is often called AM/AM and AM/PM distortion. The main reason for this is the non-linearity
of the transconductance and the change in the gate and drain impedances at different power
levels [34].
In digital communication based on linear modulation formats, the instantaneous power of
each symbol is different, so the deviation of the amplified symbol to the ideal symbol in the
constellation diagram is different between symbols (Figure 2.4). Furthermore, the transition
from one non-ideal constellation point to another point results in further non-ideality. When
the deviation of the non-ideal constellation is large enough, the correct symbol can no longer
be reconstructed on the receiver side.
2.1. PA characteristics
7
Q Q
I I
(a)EVM=2.1% (b)EVM=10.3%
Figure 2.4: The constellation diagram of a 16QAM signal. (a) The constellation of the input
signal. (b) The constellation of the distorted output signal.
From a statistical point of view, the average of the entire error vector is specified by Error
Vector Magnitude (EVM), which is defined as:
√∑ | |
∑ | |
Equation 2.6
where Sk is the received vector, Rk is the input or reference symbol vector and K denotes the
total number of symbols.
A direct derivative of the AM/AM, AM/PM and probability functions of the input signal to
EVM can be found in [34].
Harmonics and Intermodulation Distortion (IMD)
The second type of non-linearity is caused by the harmonics and mixing products. Assuming
an input signal Vi consisting of 2-tones at frequencies f1 and f2 with amplitudes V1 and V2,
respectively.
Equation 2.7
At the output the following frequencies can be observed:
Equation 2.8
At each frequency fh a spectrum peak can be observed. The coefficients m and n in the upper
equation are non-negative integers. When m or n equals 0, fh represents the frequencies of
harmonic distortion. When m and n are non-equal positive values, fh represents the
frequencies of intermodulation products. The most critical product is the third order
intermodulation product (IM3), where m=2, n=-1 or m=-1, n=2. They are very close to the
fundamental frequency and cannot be filtered out. Similar to the large signal GT, the large
signal IM3 is a function of the third order derivative of the transconductance (gm3) (Figure 2.2)
and also the probability density function of the input signal.
2.1. PA characteristics
8
1.0G 2.0G 3.0G 4.0G 5.0G0.00 6.0G
-20
-10
0
10
20
-30
30
freq, Hz
Spectr
um
1.874 1.878 1.882 1.8861.870 1.890
-20
-10
0
10
20
-30
30
freq, GHz
Spectr
um
_zoom
ed
II
I
Outp
ut
Pow
er
Outp
ut
Pow
er
3f1
-2f2
2f1
-f2
2f2
-f1
f1 f2 3f2
-2f1
f2-f1
In-b
and
pro
ducts
2f0
and m
ix
pro
ducts
3f0
and m
ix
pro
ducts
(a) (b)
Figure 2.5: (a) The output spectrum of a PA with 2-tones excitation. (b) The in-band products
are zoomed in.
For digital communications, the signal has a broad bandwidth. For example, WCDMA signal
has a bandwidth of 3.84 MHz, and an LTE signal has a bandwidth of up to 20 MHz. It is not
obvious that the 2-tone sinusoidal signal adequately conveys the interference problem from
the neighbourhood channel. Therefore two specifications are adopted for this situation,
namely the spectral emission mask and the Adjacent Channel Power Ratio (ACPR).
1.8725 1.8775 1.8825 1.88751.8675 1.8925
-80
-60
-40
-20
-100
0
Frequency (Hz)
Spe
ctr
um
Em
issio
ns (
dB
m)
I
I
Outp
ut
Pow
er
[dB
m]
-70
-50
-30 -
10
10
30
1867.5 1872.5 1877.5 1882.5 1887.5 1892.5
Frequency [MHz]
Main
channel
adjacent
channel
adjacent
channel
alternate
channel
alternate
channel
Spectral
Mask
Figure 2.6: The output spectrum, ACPR and spectral emission mask.
The spectrum emission mask defines the spectral regrowth for a given frequency range as
shown in Figure 2.6. The Adjacent Channel Power Ratio (ACPR) is defined as the power
contained in a defined bandwidth (e.g. 3.84 MHz for WCDMA) at a defined frequency offset
(e.g. 5 MHz and 10 MHz for WCDMA) from the centre frequency of the main channel,
divided by the power in the main channel:
(∫
∫
) Equation 2.9
where the PSD reflects the power spectral density.
2.2. Operation class comparison: Class A and Class AB
9
These two types of non-linearity phenomenon cannot be treated separately, notwithstanding
they have no direct linear relationship. It has been extensively studied by mathematical
calculation and practical measurement that the 1 degree AM/PM deviation can cause a 6dBc
IM3 increase, the phase of the IM3 changes as the gain changes, and the harmonic and
mixing product causes gain compression once again as an iterative process [28].
Memory effect
For an ideal memoryless condition, the output signal of a PA is a function only of the input
signal. For a PA with memory effect, the output signal is a function of the current and
previous input signal. Therefore both the EVM and ACPR are deteriorated. The main reason
for the memory effect is the self-heating of the transistor during long term operation. A
detailed explanation can be found in [35,36].
2.2. Operation class comparison: Class A and Class AB
The gate bias voltage determines the conduction angle of the drain current, which defines the
operation class in cooperation with the load impedance. From the aspects of linearity and
manufacturing cost, only class A and class AB are commonly used for 3G/WIFI/LTE mobile
phone PA nowadays, and hence other classes are not described in this work.
-100.0
m
100.0
m
300.0
m
500.0
m
700.0
m
900.0
m
-300.0
m
1.1
00
0.000
100.m
200.m
300.m
400.m
-100.m
500.m
FET_IV_Gm_PowerCalcs..DC.VGS
vs(D
C.ID
S.i[V
DS
index], D
C.V
GS
)
ts(HB.Vgate)ts(FET_dynamic_LL_classA..HB.Vgate)
IDS vs VGS at VDS specified by m1
1 2 3 4 5 60 7
0.0
0.1
0.2
0.3
0.4
-0.1
0.5
Vout_wave
ids
VGS=100.mVGS=200.mVGS=300.mVGS=400.m
VGS=500.m
VGS=600.m
VGS=700.m
VGS=800.m
VGS=900.m
VGS=1.00
VDSts(FET_dynamic_LL_classA..HB.Vdrain)
-0.3 0.1 0.5 0.9
VGS [V] (a)
0 1 2 3 4 5 6 7
VDS [V] (b)
I DS
[mA
]
-100
100 3
00 5
00 Class A Class AB
I DS
[mA
]
-100
100 3
00 5
00
Figure 2.7: (a) The DC input IV curve and large signal full driven IV curve (b) The DC
output curve and dynamic loadline of class A and class AB.
In Figure 2.7.a, the input IV curves of class A and class AB are depicted. For class A PA, the
quiescent current (Idq) is set to the middle between its maximal drain current value and 0. Due
to the symmetrical swing of Vgs on both sides of the bias voltage and the roughly linear gm
increment in that range, the GT is roughly constant. For class AB operation, the gain is
smaller because of part of the input swing across the 0-transconductance range. As the input
2.2. Operation class comparison: Class A and Class AB
10
power increases, the percentage of “useful” voltage swing increases, and hence the power
gain increases (gain expansion). Figure 2.7.b illustrates the different dynamic loadline with
the same load termination under full drive condition. The power dissipation is the triangular
area under the dynamic loadline, where the drain voltage and current are simultaneously non-
zero. Due to the clipping of the loadline, the “dissipation triangle” of class AB is smaller than
in the class A operation case. As a result, the efficiency of class AB is higher than with class
A.
When Ids is high but Vds is low, the Ids reaches the left corner in Figure 2.8.b. That is the
corner where the FETs operate in the so-called linear region, where gm drops and input
capacitance increases, so that power gain and output power will saturate. The current clipping
makes the slope of a class AB loadline steeper when Vds is low, and hence it postpones the
current reaching the left corner. In Figure 2.8.b, both PAs reach the P1dB points. The
maximal current of the class AB PA is a slightly higher, although the output voltage swing is
smaller (Figure 2.8.b). This mathematical derivation has been comprehensively studied, e.g.
in [27]. The result is that the deep class AB PA has a slightly higher maximal output power
than the class A case.
-300.0
m
-100.0
m
100.0
m
300.0
m
500.0
m
700.0
m
900.0
m
1.1
00
-500.0
m
1.3
00
0.000
100.m
200.m
300.m
400.m
-100.m
500.m
FET_IV_Gm_PowerCalcs..DC.VGS
vs(D
C.ID
S.i[V
DS
index], D
C.V
GS
)
ts(HB.Vgate)ts(FET_dynamic_LL_classA..HB.Vgate)
IDS vs VGS at VDS specified by m1
1 2 3 4 5 60 7
-0.0
0.1
0.2
0.3
0.4
0.5
-0.1
0.6
Vout_wave
ids
VGS=100.mVGS=200.mVGS=300.mVGS=400.m
VGS=500.m
VGS=600.m
VGS=700.m
VGS=800.m
VGS=900.m
VGS=1.00e+003mVGS=1.10
VDSts(FET_dynamic_LL_classA..HB.Vdrain)
I DS
[mA
]
VGS [V] (a) VDS [V] (b)
I DS
[mA
]
First clipping
Second clippingClass A Class AB
Figure 2.8: The overdriven condition.
As the input power increases from linear operation to the slight overdriven range, the peak of
Ids is clipped due to the constraint of the output IV curve (Figure 2.8.b). From the view of
gain, as the peak current drops far below the DC transconductance curve (Figure 2.8.a),
strong gain compression takes place. In contradiction with class A PA, the small gain
expansion of class AB operation could partially cancel the strong gain compression and
postpone the P1dB.
In Figure 2.3 a typical gain response of class AB PA is illustrated. The bias voltage is slightly
higher than Vt. At small power levels when the voltage valley of the input swing is still
higher than Vt, the PA actually works in class A operation with higher gain. As the power
increases, the input voltage valley becomes lower than Vt and hence part of the voltage swing
is truncated. The operation becomes class AB. The gain expansion effect resulting from the
first clipping can be seen in the middle power range. When the PA is driven near to the
saturation range, a sharp gain compression resulting in the second clipping takes place for
2.2. Operation class comparison: Class A and Class AB
11
both class A and class AB PA (Figure 2.8). The non-constant gain response results in IMD
non-linearity. In the middle power range, the IMD of class AB is therefore worse than class A.
5 10 15 20 250 30
1
2
3
4
0
5
pout
evm
5 10 15 20 250 30
30
40
50
60
20
70
Pout
AC
LR
5 10 15 20 250 30
20
30
40
50
60
10
70
Pload_dBm
Plo
ad_dB
m-P
load_IM
3_dB
mP
load_dB
m-P
load_IM
3_dB
m_A
5 10 15 20 25 300 35
-0.5
0.0
0.5
-1.0
1.0
Pout
delta
_g
ain
5 10 15 20 25 300 35
-8
-6
-4
-2
0
2
-10
4
Pout
delta
_p
ha
se
`
5 10 15 20 25 300 35
20
40
60
0
80
Pout
pa
e
0 10 20 30 0 10 20 30
Pout [dBm] (a) Pout [dBm] (b)
0 10 20 30 0 10 20 30
Pout [dBm] (c) Pout [dBm] (d)
∆g
ain
[d
B]
-1
0
1
PA
E [
%]
0 2
0
40
6
0 8
0
∆p
hase [
˚]
-10
-6
-2
2
IM3
[d
Bc]
10
30
50
70
Class A Class AB
0 10 20 30 0 10 20 30
Pout [dBm] (e) Pout [dBm] (f)
AC
PR
[d
Bc]
20
3
0 4
0 5
0 6
0 7
0
EV
M [
%]
0
1
2
3
4
510 MHz
5 MHz
Overdriven class A
PA has higher PAE
than 50%
Figure 2.9: Performance comparison between class A and AB operation.
The phase of the IM3 can be estimated from the derivative of the gain response. In class AB
operation, the strong gain compression type of IM3 has the opposite sign to the small gain
expansion type of IM3 [37]. At one specific power level, the amount of both types of IM3 is
completely cancelled out (IM3 sweet spot). Except for the specific point, the partial
cancellation is also beneficial to IM3. Furthermore, the IM3 sweet spot is controllable by bias
voltage, so that the class AB PA may have a better IM3 from the medium to high power level.
With envelope simulation assuming a WCDMA signal, the same trend was observed.
3.1. Transistor’s figure of merits
12
3. The power amplifier bandwidth
For a broadband / multiband mobile phone PA, the following is required:
1. The input and output voltage standing wave ratio (VSWR) should be good enough
when the load is matched to cascade other stages or building blocks in the
communication chain. For example, to be better than 1.2.
2. Due to the antenna mismatch, the load of PA is most of the time deviated from 50Ω,
so the PA should operate properly within a typical VSWR=3 situation.
3. The transducer power gain (GT) of a single stage should be larger than 10 dB, so that
the PAE is not significantly degenerated by the gain.
4. The low frequency gain should be compensated for by stability and constant gain.
5. Within the bandwidth, the presented load impedance by the OMN of the PA stage
should be within e.g. the 0.5 dB loadpull contour.
Requirements 1-4 are determined by the transistor’s figure of merit ft and fmax, input and
interstage matching network and amplifier’s topology, whereas requirement 5 is determined
by the bandwidth of the output matching network and circuit topology.
3.1. Transistor’s figure of merits
A typically small signal model of a FET transistor is shown in Figure 3.1. The maximum
transit frequency (ft) is also called the current gain cut-off frequency [38]. It is measured by
the injection of a small AC current into the gate and by shorting the transistor’s drain source,
the short current gain is given by [39]:
(
)
Equation 3.1
and when the term :
Equation 3.2
At ft, the magnitude of reduces to unity.
3.1. Transistor’s figure of merits
13
Cgs
Cgs
Cds
Cds
Rgs
Rgs
Rds
Rds
GG
SS S
S
DD
GG
DD
SS
VinVout≡
Ids=-gm*Vin
Figure 3.1: Symbol and model of a FET transistor.
The transistor provides the maximum power gain (MAG) when both the input and output are
conjugate matched. MAG is defined as:
(
)
Equation 3.3
where
√
Equation 3.4
At the maximum oscillation frequency (fmax), the MAG becomes unity. In the upper
approximation, the gate drain capacitor (Cgd) is ignored. In fact, it strongly influences MAG
and fmax. Due to feedback by Cgd, the transistor may oscillate, especially at low frequencies
when S21 is high. When the circuit may present oscillation with any passive source/load
termination, the MAG is not defined, and is replaced by the maximal stable gain (MSG),
which is defined as:
| | | | Equation 3.5
For a FET device, as the peripheral (W) increases, the following relationships arise:
Equation 3.6
Equation 3.7
Equation 3.8
Equation 3.9
Inserting these equations into Equation 3.2 and Equation 3.4, it can be concluded that ft and
fmax are independent of W. Therefore they are also defined as figures of merit of a device
technology.
For a mobile phone PA, the output is typically not conjugate matched, but loadline matched
by RL (RL<<Rds), the maximum large signal gain (LSG) at one frequency is defined as:
(
)
Equation 3.10
and
√
Equation 3.11
By using the same transistor, three constant gain the PAs were realized, which are matched at
different high band frequencies and mismatched at low frequencies. Obviously PA2 is best
3.2. Matching limitation
14
suited for our requirements in term of gain and cut-off frequency. The transistor technology is
suitable for this application.
1E
9
1E
10
1E
8
2E
10
10
20
30
0
40
freq, Hz
LS
GM
AG
dB
H2
1
MS
G/
1e8 1e9 1e10 2e10Frequency [Hz]
[dB
]0 10
2
0
30 40
ft
fmax
h21 MSG/MAG LSG
PA1
PA2
PA3
Matched points
Figure 3.2: A typical frequency response of PHEMT (WIN PH5000 process).
3.2. Matching limitation
Two limitations are presented to the matching network. Theoretically the bandwidth is
limited by the Bode-Fano equation. In reality, as the passive elements are lossy, the
assumption of using an arbitrary number of passive elements is not possible, and hence the
bandwidth is also limited by the limited number of elements.
3.2.1. Bode-Fano limit
Bode and Fano [40,41] derived theoretical limitations to matching the resistive source/load to
reactive impedance 50 years ago. By adding an arbitrary number of lossless passive elements,
the product of bandwidth and the reflection term
| | is limited by
, where R and C
are resistor and capacitor defined in Figure 3.4. As a result, there is always a trade-off
between these two terms.
∫
| |
Equation 3.12
3.2. Matching limitation
15
ω ω1 ω2 ω0
Γ
1
0
Figure 3.3: The reflection coefficient limited by the Bode-Fano equation.
For the ideal assumption, Γ is constant over the desired bandwidth from ω1 to ω2. Outside this
frequency range, Γ is 1. From Equation 3.12 the following can be obtained:
| | Equation 3.13
where Q1 is defined in Figure 3.4, and equals X/R for a serial network and R/X for a shunt
network. Considering the FET model in Figure 3.1, the two networks are its input and output
network, respectively. Q2 is the fractional bandwidth, which is defined as:
Equation 3.14
where denotes the mid-band frequency.
Cgs
Cgs
Rgs
Rgs
IMNRds
RdsOMN
Cds
Cds
Q2=ω0/(ω2-ω1) Q2=ω0/(ω2-ω1) Q1=1/ω0RC Q1=ω0RC (a) input of a FET (b) output of a FET
Figure 3.4: The Bode-Fano limitation at the Input and output of a FET transistor.
Therefore, a lower Q1 is beneficial for better broadband matching. By considering its
definition in Figure 3.4, a large RC product for the transistor’ input and a small RC product
for the transistor’s output are preferred for broadband matching. However, both cases
decrease the transistor’s gain [42].
3.2.2. Limitation of LC matching
The matching network should also be used to transform a small resistance into a larger
resistance value (Figure 3.5). The transformation ratio (m) is thus defined as:
Equation 3.15
3.2. Matching limitation
16
Theoretically there is no dependence between the transformation ratio and bandwidth. By
using a complicated lossless structure large bandwidth is possible, even if the transformation
ratio is high. In reality, by utilizing some low loss technology, this goal can be achieved [43].
However, in this work, only the common lumped LC matching network is used, whose high
loss limits the realization of complicated structure.
Rout
RoutLC
Rin
Figure 3.5: Lossless single-section LC low pass matching network.
The simplest l-shape single section LC matching network is shown in Figure 3.5. The quality
factor Q is proportional to the square root of the transformation ratio, which is defined as:
√ Equation 3.16
From Equation 3.16 it is clear that higher transformation ratio results in higher Q. The
bandwidth (BW) is inversly proportional to Q [44]. The S21 of 3 different transformation
ratios are shown in Figure 3.6.
0.8 0.9 1.00.7 1.1
-2.5
-2.0
-1.5
-1.0
-0.5
-3.0
0.0
freq, GHz
dB
(S(2
,1))
dB
(S(4
,3))
dB
(S(6
,5))S21
m=2
S2
1 [d
B]
-3
-
2
-1
0
S210.7 0.8 0.9 1 1.1
Frequency [GHz]
m=12.5
m=25
Figure 3.6: The bandwidth of an L-shape lossless low pass matching network with different
transformation ratio.
Normally the bandwidth is referred to 3 dB bandwidth. At the band edge S21 reduces to -3
dB. In other words, 50% of the power is lost. However, in the case of PA’s output matching
only 0.5 dB bandwidth is acceptable (10% power loss), because a 3 dB bandwidth means
twice the transistor size of the large PA stage and half the PAE.
From Figure 3.6 the 0.5 dB bandwidth covers complete 800-1000 MHz when the
transformation ratio is 12.5. However, the bandwidth based on the loadpull model is much
smaller. In Figure 3.7 the presented load impedance of the same single section matching
network with a transformation ratio of 12.5 is plotted in a Smith chart with a 0.5 dB power
contour. Obviously the presented load impedance is partially outside the 0.5 dB power
3.2. Matching limitation
17
contour. According to Cripps’s discussion [28], the real bandwidth according to the loadpull
model is much smaller than the theoretical predicted value in Figure 3.6.
indep(Pdel_contours_scaled) (0.000 to 22.000)
Pdel_
conto
urs
_scale
d
freq (800.0MHz to 1.000GHz)
transfo
rmation_ra
tio..
S(3
,3)
indep(Pdel_contours_scaled1) (0.000 to 16.000)
Pdel_
conto
urs
_scale
d1
indep(Pdel_contours_scaled2) (0.000 to 16.000)
Pdel_
conto
urs
_scale
d2
transfo
rmation_ra
tio..
S(7
,7)
S21
800 MHz
Z0=4 Ω
VSWR=1.67 circle
S21
900 MHz
1000 MHz
Single section OMN
800 MHz
1000 MHz
2-section OMN
800 MHz
1000 MHz
Figure 3.7: Smith chart with 0.5 dB loadpull contour at 800, 900 and 1000 MHz of a WIN E-
PHEMT. The presented load impedance of a single section LC matching network from 800-
1000 MHz is also shown.
One way to extend the small fractional bandwidth of the LC matching network is to use
multiple sections. By using a 2-section matching network, each with a transformation ratio of
√ , the same transformation ratio of m and a much larger bandwidth is obtained. From
Figure 3.7, the 2-section OMN presents the load impedance within the 0.5 dB loadpull
contours over the whole frequency from 800-1000 MHz. For its high pass counterpart, the
bandwidth is similar.
There are matching networks which are able to match impedance at two different frequencies
[45]. Such networks consist of two resonant networks. In the following, the output matching
from 4Ω to 50Ω is given as an example in Figure 3.8.
The impedance of the inductor increases as the frequency increases and the impedance of
capacitor decreases as the frequency increases. For simple approximation, an inductor is
“short” at low frequency and “open” at high frequency. The behaviour of a capacitor is the
other way round. Therefore at low frequency (890 MHz), the serial inductor L1 is short and
the shunt capacitor C2 is open. C1 and L2 transform Zin to 50Ω. At high frequency (1.88
GHz), the serial capacitor C1 is short and the shunt inductor L2 is open. L1 and C2 transform
Zin to 50Ω.
Outside the centre frequency the presented impedance of the dual band matching networks
changes more rapidly than the 2-elements network because the other two elements ignored
work as parasites. The bandwidth of the dual band matching is smaller than the single band
matching network in each corresponding band. Furthermore, as the number of passive
elements of the dualband matching networks is higher, the insertion loss worsens.
3.3. Broadband amplifier topologies
18
C1L1 L2 C2
Zin=4Ω 50Ω
Figure 3.8: The schematics of a dual band matching network.
In Figure 3.9 a comparison is made of the bandwidth of different matching networks.
0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.10.7 2.2
-2.5
-2.0
-1.5
-1.0
-0.5
-3.0
0.0
freq, GHz
dB
(S(2
,1))
dB
(dualb
and_m
atc
hin
g3..
S(2
,1))
dB
(_2section_m
atc
hin
g..
S(2
,1))
S21 S2
1 [d
B]
-3
-
2
-1
0
S210.7 1. 2 1.7 2.2
Frequency [GHz]
Single section
2 section
Dual-band
Figure 3.9: Bandwidth comparison of matching networks.
In conclusion, the 0.5 dB bandwidth of the output LC matching is the most critical. It requires:
More than 14 lossless sections to cover the complete frequency band from 824 MHz
to 1980MHz. By considering the realization and loss, this is impossible.
Dualband matching can cover small frequency spans in LB and HB, but it cannot
cover the complete LB or HB bands.
Reconfigurable or tunable OMN may be possible. As an immature technology, it is
not within the focus of this work.
Two sections may have a fractional BW of 15% according to the loadpull model,
which may be enough to separately cover the complete HB (1710 MHz to 1980 MHz)
or LB (824 MHz to 915 MHz).
3.3.Broadband amplifier topologies
In this section, some constant gain amplifier topologies are shown and compared. In each
topology, the frequency responses of input and output impedances are different, which are
important issues when cascading broadband stages.
The small signal performance is first compared, starting from the methods introduced by
Niclas [46]. For simplicity we assume that the output is broadband loadline matched, because
then it is ensured that the optimal load impedance lies within the 0.5 dB loadpull contour.
3.3. Broadband amplifier topologies
19
Single section lowpass LC IMN is applied to each topology, except for the distributed
amplifier. The S-parameters are compared. Obviously, a more complicated matching network
can improve the VSWR of each topology. In the end, the fractional bandwidth of the 0.5 dB
Psat is compared by inserting the identical single section L-shape OMN.
3.3.1. Common source (CS) amplifier
In Figure 3.10 a common source amplifier is depicted. The input is matched at the high
frequency band end, and hence the GT at high frequency band end equals LSG. Due to the
large transformation ratio, the bandwidth of the IMN is small. At low frequencies, the gain is
compensated for by imperfect matching.
RFin
50Ω
RL=18Ω
L=2.3 nH
C=3.9 pF
Figure 3.10: A common source amplifier.
3.3.2. Lossy matched (LM) amplifier
In a LM amplifier, the input is also conjugate matched at the high frequency end. By adding
additional lossy elements, the small reflection bandwidth is enlarged. A commonly used
method to stabilize the amplifier at low frequencies is shown in Figure 3.11. At low
frequency, the serial capacitor is nearly open and the signal is attenuated by the resistor. On
the one hand, the reflected power at low frequency is absorbed by this resistor. On the other
hand, high serial resistance makes input matching easier according to the Bode-Fano equation.
As the frequency increases, the resistor is (partially) bypassed so that it does not affect the
gain at high frequencies.
RFin
Rgs
RL=18 Ω 10 pF
5Ω C=4.1 pF
L=2.3 nH
Figure 3.11: A lossy matched amplifier.
3.3. Broadband amplifier topologies
20
3.3.3. Shunt negative feedback (FB) amplifier
In a negative feedback amplifier [41,47], the low frequency gain (AV,FB) is compensated for
by higher level of negative feedback. The low frequency voltage gain is defined as:
Equation 3.17
where
Equation 3.18
Assuming and :
Equation 3.19
where
Equation 3.20
Equation 3.21
As RFB decreases, more feedback results in lower gain. When RFB=∞, the voltage gain equals
the common source amplifier. Furthermore, the input/output impedance becomes more
constant.
RFin
50Ω
L=2.4 nH
C=3 pF
Cgs
Cgs
Rgs
Rgs
Rds
Rds
G
SS
D
Vin
Zin
RFB=90Ω
RFB=90Ω
RL=
18Ω
RL=
18Ω
DC-blockDC-block
IFB
IoutIin
Ids=-gm*Vin
Figure 3. 12. A shunt negative feedback amplifier.
3.3.4. Balanced amplifier (BA)
In a balanced amplifier [7-10,48,49], 2 identical amplifiers are inserted between two 90
degree quadrature couplers (Figure 3.13). In this topology, any reflected power at the input
and output are cancelled at the isolation (ISO) port, so that the S11 and S22 are ideally -∞
over a relative large frequency range, despite the fact that the S11’ and S22’ of each single
stage may be much worse. For broadband microwave amplifier applications, the BA is thus
often used for its excellent cascading ability over broad frequencies. For mobile phone PA
design, however, the large and costly quadrature coupler makes the broadband cascading
ability less attractive.
3.3. Broadband amplifier topologies
21
S11' S22'S11
S22RFin
50Ω
50Ω
OMN
OMN
CS amplifier in section 3.3.1
Ideal broadband matching
3dB quadrature
hybrid
50Ω
RL=18Ω
Figure 3.13: Simulated balanced amplifier.
In practice, the impedance of the antenna is not 50 Ω most of the time and the PA’s
performance and reliability are strongly influenced by it. In BA, due to the absorption of
reflected power by the 50Ω termination resistor, the PA has a more constant linearity and
PAE if the antenna is mismatched. Usually one PA works well, with higher gain and better
linearity, while the other has smaller gain and worse linearity. This balanced configuration is
sometimes called load insensitive PA (LiPA) [9,49] and is used in mobile phone application.
The ideal operation of the 90˚ phase difference between the 2 stages is only valid at the centre
frequency. Outside the centre frequency, the frequency response of the quadrature coupler
worsens. By using a novel metamaterial coupler, its bandwidth is enlarged. One
implementation shows a fractional bandwidth of 97.8% [50], where the return loss is smaller
than -10 dB. However, the 0.5 dB bandwidth is still not enough to cover the complete mobile
phone frequency of 800-2000 MHz. Furthermore, by considering the bandwidth limitation of
the OMN together, the BA can cover the complete LB or HB [11,12], but it is still very
challenging to cover complete 3G mobile phone bands of 800- 2000 MHz.
In the simulation example in Figure 3.14, the CS amplifier in section 3.3.1 is used for both
stages. The reference impedance of the output hybrid and load is set as RL, so that the
bandwidth limit by output matching is eliminated for better comparison with other topologies.
3.3.5. Distributed amplifier (DA)
The distributed amplifier is the main focus of this work. Both flat gain and good input- and
output VSWR can be obtained simultaneously. The detailed discussion is shown in chapter 5.
In this following comparison, the driver stage amplifier of section 6.6 is used.
3.3.6. Comparison of topologies
3.3. Broadband amplifier topologies
22
1.0 1.5 2.00.5 2.5
10
15
20
5
25
freq, GHz
ga
in
1.0 1.5 2.00.5 2.5
-30
-20
-10
-40
0
freq, GHz
ga
in
1.0 1.5 2.00.5 2.5
-30
-25
-20
-15
-10
-5
-35
0
freq, GHz
ga
inS
21
[d
B]
5
1
0
15
2
0
25
0.5 1 1.5 2 2.5
Frequency [GHz]
S11
[d
B]
-40
-30
-2
0 -
10
0
0.5 1 1.5 2 2.5
Frequency [GHz]
0.5 1 1.5 2 2.5
Frequency [GHz]
S2
2 [d
B]
-30
-
20
-10
0
CS LM FB
DA BA
LSG
Normalized S21 of BA
with the same periphery.
3.3. Broadband amplifier topologies
23
1.0 1.5 2.00.5 2.5
-30
-20
-10
-40
0
freq, GHz
gain
0.5 1 1.5 2 2.5
Frequency [GHz]
S1
2 [d
B]
-40
-3
0
-
20
-10
0
Figure 3.14: Frequency comparison of different topologies.
The small signal performances of all the 5 broadband topologies are compared in Figure 3.14.
The reflection coefficients comparison of CS, LM, FB and DA are similar to Niclas’s work
[46], where the validation is explained in more detail. Some of the topologies can be
combined together for more VSWR improvement, e.g. FB and LM amplifiers. The best
performance of a single topology is obtained by DA, which has S11<-15 dB and S22<-10 dB
in the desired frequency of 800-2000 MHz for 3G mobile phones. Within a much smaller
frequency range (1200-1600 MHz) where the 90˚ operation of the hybrid coupler can be
tolerated, the BA presents the best VSWR performance.
The above discussed structures with IMN and broadband load can be understood both as
driver and final PA stage. In the case where PA stage is considered, the IMN is understood as
interstage matching.
RFin
LB OMN
Driver+IMN
18 Ω 4 Ω 50 Ω
PA+interstage
matching
HB OMN
50
Ω
50
Ω
Figure 3.15: The block diagram of a 2-stage broadband PA.
The block diagram of a 2-stage broadband PA is shown in Figure 3.15. Each of the 2
triangles represents the constant gain broadband amplifier with an input/interstage matching
network. From the discussion above, the bandwidth of each stage may be sufficient of 800-
2000 MHz with relatively good input/output VSWR.
For the purpose of output matching, a tuneable or reconfigurable output matching network
which supports the entire bandwidth can be applied. Due to its high loss and non-linear
characteristics, it is also very challenging. When only conventional lumped LC matching
3.3. Broadband amplifier topologies
24
networks are considered, 2 separate matching networks with a band selection switch are
required. As discussed previously, a dualband LC OMN is not possible.
1.8E9 1.9E9 2.0E91.7E9 2.1E9
26.75
26.50
27.00
freq
Pout
S21
Nom
inal P
satd
Bm
]
-0.5
-0
.25
0
S211.7 1.8 1.9 2 2.1
Frequency [GHz]
CS: 13.9%
LM: 16.3%
DA: 12.3%
FB: 15.5%
The center frequency
of hybrid is 1.9 GHz
BA: 17.8%
Figure 3.16: Nominal 0.5 dB bandwidth/ fractional bandwidth of Psat.by using single section
lossless low pass OMN.
By applying the same OMN to LB or HB, the 0.5 dB bandwidth of maximal output power is
also different from topology to topology, because the area, frequency response of the loadpull
contour and VSWR are different. For a simple comparison, the outputs of the 5 topologies
above are now connected to an identical single section l-shaped HB OMN with a typical
transformation ratio of 12.5, instead of the broadband RL from the previous discussion. By
overdriving the input, the aspect of gain is eliminated, and the 0.5 dB bandwidths of Psat of
each topology are shown in Figure 3.16.
The DA topology has the smallest fractional bandwidth because the tapering condition is
strongly influenced by the load impedance. The area of the 0.5 dB loadpull contour is the
smallest. The BA only has the largest fractional BW when the centre frequency of the 90˚
hybrid coupler is 1.9 GHz. By changing it to 1.4 GHz, which is the centre frequency between
800 and 2000 MHz, the performance degrades significantly due to the inferior VSWR.
3.3. Broadband amplifier topologies
25
indep(Pdel_contours_p_DA) (0.000 to 68.000)
Pd
el_
co
nto
urs
_p
_D
A
indep(Pdel_contours_p_BA) (0.000 to 98.000)
Pd
el_
co
nto
urs
_p
_B
AS21
DA
VSWR=1.67 circle
S21
BA
1000 MHz
Load impedance of OMNS21Z0=50 Ω
Figure 3.17: 0.5 dB loadpull contours after the OMN.
A comparison between DA and BA has been shown in Figure 3.17. Due to the special
topology of BA, the loadpull contours are plotted at the output port after the OMN. The result
is, in principle, the same because the output matching of the 2 topologies is the same.
Ignoring the impedance tracking effect, the area of the 0.5 dB power contour of BA is larger,
so that the fractional BW is larger.
When each matching network contains a 2-section L-shape matching network, its bandwidth
according to the 0.5 dB maximal Pout may increase. For a DA which has the smallest
fractional BW, it may be still sufficient to completely cover the LB or HB.
4.1. Dynamic bias
26
4. PAE enhancement method
Conventional power amplifiers may be designed and optimized for maximum output power,
however they may be often operated at much lower output power level where the PAE is very
low. Low PAE results in shorter battery life and heating of the transistor, which degrades its
performance and reliability. In order to reduce current consumption at a lower output power
level, PAE enhancement methods are nowadays used in roughly all the 3G mobile phone PAs
[51,52]. In the following section, some of the commonly used methods are explained. After
that, two high level PAE enhancement methods, namely load balancing and spectrum
aggregation techniques are introduced.
4.1.Dynamic bias
Linearity and PAE are two contradictory terms. In the case of the typical class A/B, higher
bias voltage results in better linearity but worse PAE. The non-linearity of a power amplifier
increases as the output power increase, so the linearity at its maximal output level is the most
critical. In order to make the PA satisfy the linearity requirement at its maximal output power
level, a relative high gate bias voltage should be applied. Consequently, the linearity and PAE
trade-off for small output power levels is not optimised. For this reason, it makes sense to
decrease the bias voltage at small output power levels for better PAE while slightly
decreasing the linearity. The dynamic bias circuit senses the input power level, and adjusts
the optimal bias voltage for each power level using a diode or capacitor [53-56]. In Figure
4.1.a, a typical dynamic bias circuit [57,58] is shown. As the input power increases, more RF
signal leaks to the rectifier capacitor Cb, and hence the bias voltage increases.
For broadband amplifiers, e.g. DA, the input does not well match the whole frequency, and
hence the gain expansion may sometimes be much higher than well matched cases. In this
special case, the linearity at maximal power level is not so critical because of the presence of
an IM3 sweet spot. However, the linearity at medium power levels (e.g. 10 dB back-off) is
more critical. To satisfy the linearity requirement at medium power levels by conventional
bias circuit, much higher quiescent current should be applied. At the same time, the IM3
sweet spot near the maximal output power level may vanish due to the near class A operation.
4.1. Dynamic bias
27
Cb
RFin
Cin
Cb
Lbias
RFin
Cin
Figure 4.1: Dynamic bias circuit to compensate (a) gain compression. (b) gain expansion.
In this special case, a special dynamic bias circuit can be adapted [59] (Figure 4.1.b). In this
circuit, the dynamic bias circuit senses the input signal level. As the input signal level
increases, the gate bias voltage decreases rather than increases, so that the gain in the high
power level decreases due to lower bias voltage. As a result, the gain expansion can be
compensated. From the simulation, the IM3 also increases up to the slightly left-shifted IM3
sweet spot.
Other methods can also be used to shape the bias voltage curve, e.g. replacing the bias
inductor by a large resistor. In this case, the bias voltage drop is very small at medium power
level because the gate current is very small. At the small back-off level, the bias voltage
drops more rapidly because of the exponentially increased gate current. As a result, the
suitable bias voltage shape as shown in Figure 4.2 cannot be obtained.
Except for the gate bias circuit, no modification is required for the PA circuit, and hence this
method is simple and low cost. However, at low power level, all the stages are on with a large
back-off level, so the PAE enhancement is minor.
There are also advanced dynamic biasing techniques for the drain supply voltage [60].
Implementations based on SiGe technologies have been reported, e.g. in [61,62]. More
advanced CMOS PA using this technique has been introduced, e.g. in [63]. However, due to
the high cost and complexity implied, it is not commonly used in today’s mobile phone PA.
4.2. Stage bypass in different circuit topologies
28
12 177 22
8
10
12
14
6
16
10
20
30
40
50
0
60
Pout
gain
PA
E
12 177 22
20
30
40
50
10
60
0.25
0.30
0.35
0.40
0.20
0.45
Pout
IM3
Vb
ias
0
13 17 23 28
Pout [dBm]
Gain
[d
B]
6
8
1
0
1
2
14
013 17 23 28
Pout [dBm]
PA
E [%
]
60
5
0 4
0
30
2
0
Vbia
s[V
]
0.4
5 0
.4 0
.35
0.3
0.2
5
conventional Special dynamic bias
0
IM3
[d
Bc]
10
2
0
3
0
4
0
5
0
Figure 4.2: Two tone simulation at 1.88 GHz with and without the special dynamic bias
circuit in Figure 4.1.b: (a) gain and PAE (b) IM3 and bias voltage.
4.2.Stage bypass in different circuit topologies
The stage bypass is the commonly used method in today’s mobile phone PA products.
According to the PA’s topology, the realization of the stage bypass technique is different and
hence different names have been given, but they all contain the two following features.
Part of the stages is completely off in back-off level and consumes no power.
Loadline improvement in low power mode(s).
4.2.1. Stage bypass in conventional multistage PA
4.2. Stage bypass in different circuit topologies
29
In Figure 4.3, the block diagram of a classical stage bypassed PA is illustrated. The two
stages have separate bias circuits. At high power level, the bypass switch is off and the PA
works like a conventional 2 stage PA. At low power level, the power stage is biased off and
the switch is on. Due to the extra impedance transformation network, the load impedance of
the driver stage is increased to reduce the back-off level. Many variations of this method can
be found e.g. in [56,64-66].
Driver stage
RFin Power stage
Impedance
transformation network
RFout
High power
mode
Low power
modeVbias1Vbias2
Figure 4.3: Block diagram of a stage bypass PA.
4.2.2. Linear switched Doherty amplifier
The Doherty PA is a classical configuration for PAE enhancement [67]. A small auxiliary
transistor is biased at the class AB operation point and a large main transistor is biased at the
class C operation point. At low power level, only the small auxiliary PA is working. Due to
the impedance inverter, the auxiliary PA looks to a high load impedance and thus the back-
off level is reduced.
At medium power level, the auxiliary PA works in the small back-off level which contributes
to gain expansion. The class C main PA starts to work, which also contributes gain expansion.
The expansion of the total PA is double and hence the linearity is worse. The PAE is high due
to the small back-off level of the auxiliary PA and class C operation of the main PA.
At high power level, the gain of the auxiliary PA starts to compress and the main PA retains
gain expansion. Consequently, the overall gain is linear due to the compensation of the two
PAs. At this point, the peak PAE is normally higher than the single class AB PA.
In conclusion, the Doherty PA has a high PAE in a large dynamic range and good linearity at
high power level but poor linearity at medium power level.
4.2. Stage bypass in different circuit topologies
30
RFin
Auxiliary PA
Main PA
RFout
90˚ delay line
Impedance
inverter
AC shunt
switch
Figure 4.4: The block diagram of the switched Doherty PA.
For the base station PA, the poor linearity at medium power level can be improved by
complicated pre-distortion methods [68,69]. For mobile phones, due to reasons of cost, a new
method has been reported by Apel [70,71]. With his method, linearity can be improved by an
AC shunt switch. By switching it on, the class C operation of the main PA at medium power
level is avoided. Linearity at medium power level is only determined by the linearity of the
auxiliary PA. Consequently, the new configuration retains the advantage of the conventional
Doherty PA at high power level but improves the linearity at medium power level.
4.2.3. Stage bypass in BA.
The balanced amplifier topology has two identical PA chains. By switching off one of the
two identical chains and switching off or short circuiting the isolation resistor, about 4 dB
back-off level has been measured in [9].
Furthermore, as depicted in Figure 4.5, an additional low power PA stage can be inserted
between the ISO port of the input and output hybrid couplers. In the high power mode, the
low power path is deactivated. This PA operates in the same way as a classical BA. In low
power mode, both high power stages are biased off, which presents a high mismatch to the
hybrid couplers. When the low power stage is switched on, the complete signal is amplified
through the low power stage [72-74].
4.3. Spectrum aggregation and load balancing
31
HP1
HP2
IN
0˚
90˚
ISO LP
90˚
0˚
ISO OUT
Figure 4.5. Block diagram of a sequential balanced amplifier.
The above depicted structure can also be cascaded for more power modes. For instance, two
of the above structures can be coupled by two quadrature couplers to form a new, larger
balanced PA.
4.2.4. Distinguished stage bypass in DA
Due to the multi-stage nature of DA, a distinguished stage bypassing technique versus partial
or complete bias off or switching off stage is adopted. The detailed characterisation of which
will be shown in chapter 5.5.
4.3.Spectrum aggregation and load balancing
Spectrum aggregation is one of the key technologies for LTE release 10 (IMT-advanced). By
utilising the spectrum aggregation technique, it is possible to simultaneously allocate up to
100 MHz spectrum to a single end user in multiple frequency bands for higher data rates. The
communication frequency bands with lower traffic can be allocated with high priority. This
scheme can avoid the case where a large number of users are competing for resources on one
frequency, while resources in the other frequency are wasted as they are unused [75-78].
Strictly speaking, it is not a pure PAE enhancement method. But as the load of the high
traffic frequency band can be kept lower than a threshold, the total transmission energy of the
base station can be decreased [76]. Especially when the number of connections within one
frequency band is extremely high, the spectrum allocation scheme can significantly improve
the overall PAE.
In addition, the load balancing technique can be used to decrease the overall back-off level.
Figure 4.6.a illustrates a typical worse case for the base station. The band 13 PA has a good
PAE due to its small back-off level. At the same time, the PAE of the band 17 PA has very
poor PAE due to the large back-off level. The overall PAE of the two PAs is therefore worse.
This worst case can be solved by a PA which is capable of a load balancing technique (Figure
4.3. Spectrum aggregation and load balancing
32
4.6.b). When the two band’s signals are simultaneously amplified by a single PA, the overall
back-off level is smaller and thus the PAE is higher.
Besides, since the two frequency bands are rarely fully loaded at the same time, the size of
the dual outputs PA in Figure 4.6.b can be smaller than the total size of the PAs in Figure
4.6.a. As a rule of thumb, the transistor cost of each watt output power is approximately 1
USD, and the total product cost of the PA can also be decreased.
However, the LTE uplink TX side uses the Single Carrier FDMA scheme which limits the
application of the techniques described above. But these techniques may be attractive for
future releases, e.g. LTE rel.11, if a high upload speed is also demanded. In addition, these
technologies have the potential to improve the PAE of a mobile phone multi-standard PA.
The handset PA for Bluetooth, WLAN and so on are smaller and work at a larger back-off
level than the UMTS PA (Figure 4.6.c). When the UMTS and WLAN signals are
simultaneously amplified by one PA, there is almost no power increase in comparison with
only UMTS signal amplification, the linearity deterioration is also minor. The detailed
characterisation is illustrated in chapter 6.
4.3. Spectrum aggregation and load balancing
33
LTE Band 13
RFin
LTE Band 17
RFin
RFinLTE Band 13
LTE Band 17
BO=10
BO=30BO<13(a)
UMTS, LTE,...
RFin
Bluetooth/WLAN...
RFin
RFin
(b)
(c)
(d)
824-849
869-894
824-849
869-894
880-915
925-960
880-915
925-960
2.45 GHz2.45 GHz
824-849
869-894
824-849
869-894
880-915
925-960
880-915
925-960
2.45 GHzBluetooth/WLAN
UMTS, LTE,...
Figure 4.6: Comparison of the spectrum aggregation and load balancing technique.
In the conventional configuration, the output band selection switch limits the possibility of
concurrent 2-signal amplification. Even if a single output broadband PA is used, the band
selection switch cannot be eliminated because the corresponding filter should also be selected.
The diplexing PA (Figure 4.6.d) can solve this problem by directing different signals to
different filters.
From this discussion, the conclusion can be made that a PA with spectrum aggregation and
load balancing capability improves the PAE of the overall system. The diplexing tapered DA
introduced in chapter 6 has this ability.
5.1. Introduction
34
5. Distributed Amplifier for mobile phone
5.1.Introduction
A distributed amplifier [79-85] is a well-known broadband amplifier. The gates of multiple
transistors are connected successively by inductors and capacitors forming an artificial
transmission line (Right Handed TL, RH-TL), which absorbs the transistor’s input
capacitance. Therefore, the f3dB and gain/bandwidth product (GBW) can be simultaneously
enhanced. The mismatched power at frequencies lower than the f3dB is absorbed by a
termination resistor, so that the input VSWR at low frequency is improved. On the output
side, the phase delay between stages, which is caused by the input artificial TLs, is again
compensated by artificial TL, so that the output current of all stages are added together in-
phase, without energy loss [28,79,81]. In classical design, on left side of the drain line, a
terminator resistor is required also. However, in order to improve the efficiency, the tapering
technique is usually used. The schematic of a tapered distributed amplifier is illustrated in
Figure 5.1.
PHEMT
RH-TL
Cin1
RFout
RFin
Cgs
4RL4RL 4RL 4RL
4RL 2RL 4/3RL RL
Cds
Ids
Figure 5.1: The schematics of a travelling wave amplifier, the dashed box represents a FET
transistor model and the RH-TL.
Since the effective gate capacitance of all stages is completely absorbed, the bandwidth of
DA is limited by gate artificial TL [79,86]. After considering the gate resistance attenuation,
the GBW is defined as [79]:
5.2. Design procedure of tapered DA
35
√
Equation 5.1
Equation 5.2
where Lg and Cg denote the inductance and capacitance value of the gate line. For frequencies
lower than f3dB, the characteristic impedance of the gate line section is defined as:
√
Equation 5.3
Generally, Z0g can be arbitrary chosen. This flexibility makes the input and interstage
matching easier.
5.2.Design procedure of tapered DA
In order to get comparable PAE as a single ended PA, each single stage of the DA should
have the optimal load impedance. And hence the tapering technique is used. In the following,
the design procedure of a tapered DA is described.
The input signal travels through the gate line (Figure 5.2) and is attenuated by the gate
resistor Rgs at each stage. Therefore the voltage swing at the right stage is smaller than at the
left stage. The voltage swing at node Vin,n it is defined as:
Equation 5.4
where αg represents the attenuation per line section, and βg represents the phase constant of
the gate line. They can be expressed as:
Equation 5.5
√ Equation 5.6
The drive level of all stages should be equalized by input coupling capacitors. The serial Cin
and Cgs are voltage divider. The “useful” input voltage Vgs,n swing across Cgs is:
Equation 5.7
Cin,n is used to equalize the input voltage swing of all stages. By combining the equations
from Equation 5.4 to Equation 5.7, the coupling capacitor Cin is defined as:
Equation 5.8
5.2. Design procedure of tapered DA
36
Lossy TL section
Cin1
Z0g
Rgs
Cgs
Cin2
Rgs
Cgs
……..
Vin
Z0g
Vgs1 Vgs2
Cin,n
Rgs
Cgs
Vgs,n
Vin2Vin1 Vin,n
L/2L/2L/2 L/2
Figure 5.2: Equivalent gate line representation.
The attenuation term is larger than 1, so the following generally holds:
Equation 5.9
Since the equivalent serial capacitance of Cin and Cgs is smaller than Cgs, smaller Lg is
required for the same desired Z0g according to Equation 5.3. Therefore the f3dB of the gate line
can be increased by:
√
Equation 5.10
Equation 5.11
RL
MRLMRL
id1
….
I1 In-1
Id2 Id,n
RM
IM
RLMRL MRL/2
MRL
….
Id,MMRL
I2
MRL/n
In IM-1
Figure 5.3: Equivalent drain lines representation.
The load impedance of all the stages should also be equalized. This condition has been
carried out by the drain line tapering technique. In Figure 5.3, the tapered drain line is shown.
5.2. Design procedure of tapered DA
37
In conventional TWA, not only the gate line, but also the drain line contains a termination
resistor and hence 50% of power is wasted. After eliminating it, the S22 is traded off against
PAE. From left to right, the characteristic impedance of the n-th TL section is defined as:
√
Equation 5.12
where M is the number of total stages. The load impedance of the n-th stage (ZL,n) is defined
as:
( )
Equation 5.13
where Vd,n is the voltage at the n-th node of the drain line, Id,n is the output current of the n-th
transistor stage, The In-1 equals the current flow from drain line to the n-th node, which is
defined as:
Equation 5.14
The complex propagation constant of the drain line αd+jβd is defined as:
Equation 5.15
√ Equation 5.16
where and represent the inductance and capacitance of the n-th drain line section,
respectively. denotes the parasitic resistance of the inductor . Based on ideal
assumptions, the current flow to the n-th node ( In-1) is given by:
Equation 5.17
Combining Equation 5.14 and Equation 5.17, drain line loss should be compensated by:
Equation 5.18
In other words, as indicated by the exponential expression , the drain line current
should be larger than the ideal case. Starting from the leftmost stage, the current relationship
holds:
Equation 5.19
Furthermore, the phase alignment between gate and drain line section requires:
√ √ Equation 5.20
When all the upper equations are satisfied, every stage of the tapered DA operates in its
optimal condition. Paradoxically, as the tapering process tries to equalize all the transistor
stages, it introduces new non-ideal conditions:
From Equation 5.19, the drive level of each stage has to be different to compensate
the drain line loss. As a result, the left stages reach Psat earlier than the right stages,
which contributes more non-linearity to the overall circuit.
5.3. The linearity of DA
38
The input matching of each stage is a function of the input coupling capacitor, since
the capacitor values increases from left to right stages according to Equation 5.9, the
input matching of each stage, which influences significantly the linearity, is different.
In practice, these two non-ideal effects can be overcome by circuit optimisation, especially
through tuning the Cin value at each stage. In conclusion, the PAE and linearity of a tapered
DA is slightly lower than that of a single ended PA.
5.3.The linearity of DA
Although these two non-ideal effects only have a small influence on PAE, the linearity is
greatly deteriorated. Here, the linearity of a single stage is discussed at first and then the
overall linearity is shown.
The linearity of single stages is determined by input and output matching when the bias is
fixed. The output impedance of the tapered DA is roughly loadline matched as with the single
ended PA. The input impedance is often non-optimal. In practice, the linearity of each stage
is worse than with a single ended PA due to its non-optimal input and output impedance.
As evidence of this, the gain expansion may show up to be much greater than with a single
ended PA for the same amount of quiescent current. After increasing the quiescent current to
about 40% of the maximal drain source current (4stages*50mA=200mA), the gain expansion
decreases to an acceptable value of only 1dB.
The overall linearity differs by EVM and ACPR.
18 20 22 24 26 28 3016 32
-5
-4
-3
-2
-1
0
-6
1
Pout2
delta_phase
18 20 22 24 26 28 3016 32
-0.5
0.0
0.5
1.0
-1.0
1.5
Pout2
delta_gain
(b)16 20 24 28 32 16 20 24 28 32
Pout [dBm] (a) Pout [dBm] (b)
∆P
hase [
˚]
-6
-4
-2
0
∆G
ain
[d
B]
-1
0
1
Stage 1-4 Complete DA
Figure 5.4: AM/AM and AM/PM conversion effects of each stage and of overall the PA in
section 6.5.
The overall AM/AM and AM/PM conversion effects show up as the mathematical average of
all single stages. Since the deviation of AM/AM and AM/PM characteristics of each stage are
of the same order, a compensation effect could take place (Figure 5.4). The overall AM/AM
and AM/PM conversion effects are still comparable to a single ended PA up to its P1dB point.
5.4. Stability consideration
39
As discussed in section 2.1.4, the EVM is mainly referred to the AM/AM and AM/PM
characteristics, and hence the EVM performance of a DA is comparable to single ended PA
even in the non-tapered case.
The IM3 compensation only occurs when the magnitude at each stage is roughly the same
and the phase is opposite. A conventional DA thus exhibits much worse IM3 performance
because of the difference in drive level at each stage. The tapered DA should have the same
IM3 performance as a single ended PA if all the stages operate at under exactly the same
operation conditions. But in practice, the common case is that the paradoxical non-equal
condition results in an increase in IM3 by more than 10 dB (10 times larger) at the worst
stage. It is not possible to overcome this IM3 degradation effect. The overall IM3 is not a
mathematical average of all the stages, but is worse than the worst stage because IM3
compensation cannot take place under different power levels. As a result, the ACPR
performance of the tapered TWA is much worse than that of a single ended PA.
15 20 2510 30
-40
-30
-20
-10
-50
0
dBm(mix(Vout2,1,0))+3
Po
ut_
t1_
IM3
_d
Bm
Po
ut_
t2_
IM3
_d
Bm
Po
ut_
t3_
IM3
_d
Bm
Po
ut_
t4_
IM3
_d
Bm
dB
m(m
ix(V
ou
t2,
2,-
1)
)
10
10 15 20 25 30
Pout [dBm]
Stage 1-4 Complete DA
10
IM3 [
dB
c]
-50 -4
0
-30
-20 -1
0
0
Figure 5. 5: The simulated IM3 product of the demonstrator.
In summary, the tapered DA yields similar EVM performance to a single ended PA. But the
ACPR is commonly much worse. Typically more than 2 times larger quiescent current is
required to achieve the same linearity as with a single ended PA.
5.4.Stability consideration
Stability is an important issue for all power amplifier designs. The in-band and out-of-band
oscillations may make the PA unusable. Under extreme situations, it can destroy the PA. The
spurious emission with low power degrades the PA’s maximal output power and the PAE. On
the one hand, the decreased maximal output power level decreases the back-off level and
hence the linearity at a specific output power level. On the other hand, the spurious emissions
mixed with signals at fundamental and harmonic frequencies, introduce new intermodulation
products and may be located within the adjacent channel.
5.4. Stability consideration
40
Matching or
stabilization
network
Matching or
stabilization
network
Zs ZL
Vout, Iout
ΓsΓs ΓoutΓoutΓin ΓL
Iother
Figure 5.6: A two-port amplifier with reflection coefficient.
Defining Γ as the reflection coefficient, the input and output reflections in Figure 5.6 are
defined as:
Equation 5.21
Equation 5.22
where the S-parameter are those of the power amplifier circuit including its matching
networks. Γin and Γout are functions of Γs and ΓL , respectively. In the absence of current
injection from other stages (Iother), two types of conventional stability conditions are defined
as follows:
1. Conditional stability: The network is conditionally stable if | |<1 and | |<1 are
fulfilled only for a certain range of passive source and load impedances, and the
presented impedance is located within this range.
2. Unconditional stability: The network is unconditionally stable if | | <1 and
| |<1 are fulfilled for all passive source and load impedances.
In practice, the unconditional stability condition is desired for any PA design. In same design,
only the conditional stability criterion is met. By considering Iother, the third condition is
defined as:
3. Stable by current injection from other stages: The network is stable for a
multistage PA if | |<1 and | |<1 are fulfilled not only for passive source and load
impedances, but also in the case of current injection from other stages, where the load
impedance is defined as:
Equation 5. 23
where Vout and Iout are the output voltage and current of the network, respectively. The real
part of the modulated can be positive, 0 or negative, which is exactly the case with the
multistage nature of a DA. In particular, the PHEMT is often capable of substantial gain at
high frequency, so that internal oscillation not only occurs at low frequencies, but also at high
frequencies [29].
The conventional stability analysis is based on S-parameters. As the system behaviour
changes by large signal excitation, the conventional method cannot guarantee stability under
every situation, i.e. at every output power level. Assuming a common case in measurement,
5.4. Stability consideration
41
by sweeping the frequency at relatively high power levels, a sudden drop in the output power
is observed, typically of 1-3 dB, within a narrow range of frequency. Outside the frequency
range, the output power becomes normal. The reason for this effect is the spurious emission
at one special frequency when a large signal is applied in a particular frequency range and
power. This type of oscillation is referred to as large signal parametric oscillation [29].
Conventional large signal simulation is based on the harmonic balance (HB) method, which
only concerns the fundamental and its harmonic frequencies. As the spurious emission is
often caused by the oscillation of noise outside these frequencies, a method including HB and
noise frequencies characterisation is required.
Here a new method [87-90], using the system identification in closed loop simulation, is
adopted in the DA’s design. This method can not only find the small signal internal
oscillation in multistage PA, but can also detect the large signal parametric oscillations.
ZL
1. tone, large signal drive
Vout,ss
Sweeping 2. tone,
small signal Iin,ss
Figure 5.7: Illustration of the large signal oscillation detection method
The simulation setup is illustrated in Figure 5.7: a 2-tone harmonic balance simulation has
been carried out at first. The frequency and power of the first tone is defined as the typical
operation condition of the PA (large signal tone). The second tone has very low power, e.g. -
50 dBm, and the power can be injected into any node of the DA. By sweeping the frequency
of the second tone, the linear transfer function
of the non-linear system at the
large signal condition of first tone is obtained. Theoretically, any loop of the complete system
contains the same pole, zero information, unless complete pole, zero cancellation or filtering
takes place.
The pole-zero information of the transfer function obtained should be identified, so that a
program based on the Levenberg-Marquardt algorithm (LMA) presented in [91] is run.
Details about this program are explained in Appendix B.
In Figure 5.8, the pole-zero diagram of the PCB demonstrator is depicted for 0 dBm
excitation at 1.88 GHz. From system theory, the third stability condition is equivalent to the
condition where all the poles are located on the left half surface. Any positive or 0 poles
indicate spurious emissions, and the oscillation frequency can be readout from the y-axial.
5.4. Stability consideration
42
Imagin
ary
part
[G
Hz]
-4.7
-3
.2
-1
.6
0
1.6
3
.2
4.7
-4.7 -3.2 -1.6 0 1.6 3.2 4.7
Real part [1E9]
Zerox Pole
Figure 5.8: Pole-zero diagram of the PCB demonstrator when Pin=0dBm at 1.88 GHz.
In Figure 5.9 and Figure 5.10, the contour of the real part of the critical poles is illustrated for
1.88 GHz and 890 MHz large signal excitation, respectively. The y axis value identified in
red along the contour indicates the most critical frequency at a specific input power because
the real part of the pole is closer to the real axis. The black colour indicates the safest range
where the real part of the pole is much smaller than -2E8.
0
`
Fre
qu
en
cy [G
Hz]
0
1
2
3
4
5 0
-40
-80
-120
-160
-200
Real P
art o
f critic
al p
ole
s [1
E6
]
0 5.5 11 16.5 22
Pin [dBm]
Figure 5.9: Contour of the real part of the critical poles (fin=1.88 GHz).
5.5. Distinguished stage bypass in DA
43
0`
`
Fre
qu
en
cy [G
Hz]
0
1
2
3
4
5 0
-40
-80
-120
-160
-200
Real P
art o
f critic
al p
ole
s [1
E6
]
0 5.5 11 16.5 22
Pin [dBm]
Figure 5.10: Contour of the real part of the critical poles (fin=890 MHz).
From Figure 5.9 and Figure 5.10, the most critical pole lies at about 300 MHz. The evolution
of this pole is shown separately in Figure 5.11. The real part of the critical pole increases at
the middle power level, accompanied by the gain expansion. At high power level, its real part
has the obvious trend to decrease. This can be explained in that the PHEMT becomes lossy,
when the Schottky barrier of approximately 0.8V is reached. Similar as Figure 5.11, the
evolution of the pole at other frequencies can be plotted similarly.
-1.0E+08
-8.0E+07
-6.0E+07
-4.0E+07
-2.0E+07
0.0E+00
0 5.5 11 16.5 22Pin [dBm] (a)
Re
al P
art
of critica
l
-1.0E+08
-8.0E+07
-6.0E+07
-4.0E+07
-2.0E+07
0.0E+00
0 5.5 11 16.5 22
Re
al P
art
of critical
Pin [dBm] (b)
Figure 5.11: The most critical pole at about 300 MHz evolutions by power sweeping at: (a)
890 MHz. (b) 1.88 GHz.
In reality, the negative real part of all poles cannot guarantee stability because the fabrication
variation and inaccuracy of the device modelling could shift the pole unintentionally. In some
situations, the parametric oscillation still occurs despite the real part of the poles being
negative. As an example, spurious emissions at 300 MHz and 2.3 GHz are observed in Figure
6.18.b. These results are in line with the findings from Figure 5.9 and Figure 5.10. A
relatively critical value can be readout at these frequencies. As a result, a stability margin
smaller than 0 (e.g. <-2E8) should be maintained for robust design.
5.5. Distinguished stage bypass in DA
5.5. Distinguished stage bypass in DA
44
Z02=8 Ω Z01=16 Ω
RFin
T1 T2 T4T3
RFout
C1+Cds1 C2+Cds2 C3+Cds3 C4+Cds4
L1 L2 L3
Cin1 Cin2 Cin3 Cin4
Vbias1 Vbias2 Vbias3 Vbias4
Z02=5.3 Ω
Figure 5.12: Block diagram of the stage bypassed DA.
Stage bypass should also be implemented in DA if PAE enhancement is required [92]. For
this aim the gate of each transistor is coupled with a separate bias circuit adapted to control
the amplifier device. The bias circuit enables the control of the amplifier devices to be
managed independently of each other, so that the DA may operate in different power modes
by switching off part of its stages. For the ease of description, the 4 power modes are defined
as:
Power mode Mode1 Mode2 Mode3 Mode4
“On” stage(s) T1 T1+T2 T1+T2+T3 All
Table 5.1: The power modes definition.
The bias circuit is illustrated in Figure 5.13. A feedback circuit is used to set a stable bias
voltage. Two resistors are used as a voltage divider to set a clear logic level of the control
signal Vmode. When the Vmode signal turns high (>2V), the 2 E-PHEMT switches are on. The
upper switch short the reference current to ground and hence the feedback circuit is
deactivated. As a result, the Vbias voltage becomes 0.
The lower AC shunt switch is used to short the input signal of the off-stage. Without this
switch, the off-stage operates in class C, which contributes to the whole DA strong non-
linearity, even at the medium power level. In Figure 5.14 the gain and third order
intermodulation product (IM3) are compared with and without the AC shunt switch. The AC
shunt switch avoids class C operation because of the decreased gain expansion and increased
IM3. Near P1dB, the IM3 is better without the AC switch, because of the gain compensation
effect of class C and class AB PA. But the linearity is still not in line with the specification.
The Rbias, Lbias and Cbias work as a RF choke and bypass capacitor, respectively, similar to a
conventional bias circuit.
5.5. Distinguished stage bypass in DA
45
Vcc
Switch to deactivate the
feedback bias circuit
AC shunt switchVmode
CbiasLbiasRbias Vbias
Iref
Figure 5.13: Schematic of a bias circuit for switched DA.
5 10 15 20 250 30
8.0
8.5
7.5
9.0
Pout
ga
in
With AC shunt switch
Without AC shunt switch
-
-0 5 10 15 20 25 30
Pout [dBm] (b)
Gain
[dB
]
7.5
8 8.5
9
IM3
[d
Bc]
20
40
6
0
8
0
5 10 15 20 250 30
8.0
8.5
7.5
9.0
Poutg
ain
5 10 15 20 250 30
30
40
50
60
70
20
80
Pout
im3
With AC shunt switch
Without AC shunt switch
-
-
Ga
in [d
B]
7.5
8
8
.5
9
IM3 [
dB
c]
20
40
60
80
With shunt switch Without shunt switch
Operation range
0 5 10 15 20 25 30
Pout [dBm] (a)
0 5 10 15 20 25 30
Pout [dBm] (b)
Operation range
Figure 5.14: Gain and IM3 comparison in mode2 with and without the AC shunt switch.
After setting the Vmode of one transistor stage to high, two effects take place for the PAE
enhancement:
Quiescent current consumption: In the case where each transistor stage is designed equally,
switching off one stage results in a ¼ quiescent current saving. For example, the quiescent
current is only 30 mA instead of 120 mA in mode1.
Impedance up-transformation: Here the situation for mode1 is given as an example. The
characteristic impedance of the second transmission line section is 2RL (here 8Ω). The Z2
defined in Figure 5.15 is modulated by the output current i2 of the transistor stage T2. When
T2 is off, Z2 becomes 8 Ω. At the same time, the capacitance Cds of T2 decreases to about 30%
of its original value. The load impedance Z1 transformation of the transistor stage T1 in the
two situations is plotted in a Smith chart. As a result, impedance Z1 is higher than 4RL (16Ω).
5.5. Distinguished stage bypass in DA
46
Cds1+C1
0.3*Cds2+C2
L1
Z1>16Ω
Z2=8Ω
(b)
Cds1+C1
Cds2+C2
L1 Z1=Z2=16Ω
(a)
L1
Cds2+C2Cds1+C1
Z0=8Ω Z0=8Ω
Z1=16Ω Z2=(i1+i2)*8Ω/i1=16Ω
i2=i1
i1L1
0.3Cds2+C2Cds1+C1
Z0=8Ω Z0=8Ω
Z1>16Ω Z2=8Ω
i2=0
i1
Figure 5.15: Impedance seen by stage T1 when: (a) its right stages are on (b) its right stages
are off.
Although the higher impedance Z1 is non-controllable and non-optimal, it more or less
improves the PAE over the whole frequency range of 800 MHz-2000 MHz. Furthermore, for
a PHEMT transistor, the load impedance only determines the maximal output power and has
a small impact on its linearity.
In other power modes, the effect of the impedance up-transformation takes place in a similar
manner. The evidence for which can be found in Figure 5.16. b: Assuming the load
impedance of each stage is 16Ω in each mode, the gain decreases by 1.7dB (25%), 3dB (50%)
and 4.7dB (75%) from mode4 to mode1, respectively, according to:
Equation 5.24
where Pout and Pin are the input and output power, n equals the number of the on-stage, and
Iout denotes the output current of each on-stage. In reality, the gain decreases by 1dB, 2.8dB
and 4dB, respectively. The reason for the smaller gain decrease is given by the fact, that the
actual load impedance is higher than 4RL.
From mode4 to mode1, the PAE is enhanced by trading-off gain and maximal output power.
Up to a specific maximal output power level (solid circle in Figure 5.16), the simulated
adjacent channel power ratio (ACPR) is larger than 40 dBc at the 5 MHz offset bandwidth
and larger than 50 dBc at the 10 MHz offset. The error vector magnitude (EVM) is smaller
than 3% using WCDMA signal excitation.
5.5. Distinguished stage bypass in DA
47
15 20 25 3010 35
10
20
30
40
50
0
60
Pout
PA
E
15 20 25 3010 35
6
7
8
9
10
5
11
Pout
ga
in
10 15 20 25 30 35
Pout [dBm] (a)
Gain
[dB
]
5 6 7
8
9
1
0 1
1
0.6 1.1 1.6 2.1 2.6 3.10.1 3.6
5
10
0
15
freq, GHz
S2
1
`
S21 [dB
]
0
5
1
0 1
5
Mode4 Mode3 Mode2 Mode1
10 15 20 25 30 35
Pout [dBm] (b)
0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6
Frequency [GHz] (c)
`
PA
E [%
]
0 10 20 30 4
0 50 60
Figure 5.16: Performance of the four power modes at 1.88 GHz: (a) PAE (b) gain (c) S21.
After switching off stages, the DA becomes more and more non-ideal. It can be seen as a
lossy matched multistage amplifier. Accompanying the decreased gain, the bandwidth also
decreases (Figure 5.16.c).
6.1. CRLH-TL
48
6. Directional Distributed Amplifier based on CRLH
structure
In this chapter, the Composite Right- and Left- Handed Transmission Line (CRLH-TL) is
first introduced as the enabling building block for diplexing DA. Then the new circuit
concept and realizations are shown in the following sections. Application and performance
improvement are discussed. The opportunity to expand the diplexing DA to triplexing and
multiplexing DA is considered at the end.
6.1.CRLH-TL
The left handed TL (LH-TL) section is inverse from the conventional artificial transmission
line (Right Handed TL, RH-TL) section by replacing serial L with shunt L, and shunt C with
serial C (Figure 6.1.a and b). Its phase response has a different sign to RH-TL.
CRH
LRH/2
CLH/2LRH
CLH/2
CRH
CLH/2 CLH/2
(a) RH-TL (b) LH-TL
(c) CRLH-TL
LRH/2
LRH
LRH/2 LRH/2
Figure 6.1: T-type unit cells of artificial (a) RH- (b) LH- and (c) CRLH TLs.
Combing the LH-TL and conventional RH-TL together, the CRLH-TL (Figure 6.1.c) has the
characteristics of both TL types [93]. The detailed mathematical expression of CRLH-TL can
be found in [94]. Assuming the phase delay of each unit section is electrically small (θ<λ/10),
the approximated characteristic impedance and phase responses are:
6.2. The diplexing DA
49
√
Equation 6.1
√
Equation 6.2
√
√
Equation 6.3
√ Equation 6.4
√ Equation 6.5
√
√ Equation 6.6
where , and are the characteristic impedance, and , and are
the phase shift of the RH-, LH- CRLH-TL unit section, respectively.
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-8
-6
-4
-2
-10
0
f req, GHz
dB
0.5 1.0 1.5 2.0 2.5 3.0 3.50.0 4.0
-90
0
90
-180
180
f req, GHz
phase
0 1 2 3 4 0 1 2 3 4
Frequency [GHz] Frequency [GHz]
S21 [dB
]
-10
-5
0
Phase o
f S
21 [˚]
-180
0
1
80
RH- LH- CRLH-TL
Figure 6.2: Magnitude and phase response of RH-, LH- and CRLH-TL unit sections.
One important feature of the CRLH-TL is that the phase response can be positive, 0 or
negative for different frequencies (Figure 6.2). Based on this, many novel microwave passive
building blocks, such as enhanced-bandwidth couplers, dualband components, zeroth order
mode resonators [16,93-97], and so on, have been realized. By utilizing these passive
building blocks, some new multiband amplifiers or amplifiers with special features, have
been reported [13,23,24,50,98].
6.2.The diplexing DA
The concept of distributed amplifier is based on wave propagation along the gate and drain
line RH-TLs coupled by active devices. The maximal gain and efficiency is only achieved
when the phase between the gate and drain line perfectly aligns. In mathematical expression,
the maximal gain is achieved when:
6.2. The diplexing DA
50
Equation 6.7
Since both phase constants are negative, only one solution is possible. By replacing the gate
line [23] or both the gate and drain line [24] RH-TLs to CRLH-TLs, two gain peaks are
possible when:
| | | | Equation 6.8
where g and d are defined by Equation 6.4 and Equation 6.6 for RH- and CRLH- TL type,
respectively. The two terms could have the same sign or opposite sign (Figure 6.3).
9.0E8 1.1E9 1.3E9 1.5E9 1.7E9 1.9E97.0E8 2.1E9
-150
-50
50
150
-250
250
freq_swp
ph
ase
9.0E8 1.1E9 1.3E9 1.5E9 1.7E9 1.9E97.0E8 2.1E9
-200
-150
-100
-50
-250
0
freq_swp
ph
ase
(Ic1
.i[1
])p
ha
se
(Ic2
.i[1
])p
ha
se
(Ic3
.i[1
])u
nw
rap
(ph
ase
(Ic4
.i[1
]))
Ph
ase
[˚]
50
15
0
25
0
Ph
ase
[˚]
-25
0
0
2
50
0.7 1.4 2.1 0.7 1.4 2.1
frequency [GHz] (a) frequency [GHz] (b)
θg,n=-θd,n
θg,n=θd,n
θg,n=θd,n
Figure 6.3: Phase relationship between stages of circuit in section6.6 (a) tapered DA as driver
(b) diplexing tapered DA as PA stage.
Since the CRLH-TL section contains more elements, the loss across each section is higher
than that of RH-TL. In the design of Xie [23], CRLH-TL is only used with gate line design
while RH-TL is used for the drain line (Figure 6.4 [23]). A higher PAE can be achieved at the
same time since fewer passive elements are required.
LB
Port
RFin
CRLH-TL
RH-TL
………..
HB
Port
βL
βH
Figure 6.4: Schematic of a diplexing distributed amplifier from [23].
At low frequencies, the phase shift of CRLH-TL in gate line θg is positive and the phase shift
of RH-TL in drain line is negative. When Equation 6.8 is satisfied, the power of all stages is
combined in the LB output port. At high frequencies, the CRLH-TL has roughly the same
properties as the RH-TL, the output power of all stages is combined at the HB output port.
The low band gain (GLB) and high band gain (GHB) are given by [99]:
6.3. Linear tapered diplexing DA
51
( [
]
[ ]
)
Equation 6.9
( [
]
[ ]
)
Equation 6.10
where Z0d,0g denote the characteristics impedances of the drain and gate transmission lines,
are the phase shift over each transmission line section, and N is the number of the cells
that form the transmission line. An additional parameter to specify the band selection, the
isolation of the diplexing feature, is defined as:
| | Equation 6.11
The typical performance of the conventional FET switch is illustrated in Table 6.1 [100]. In
the band selection application, a 20 dB isolation of the diplexing DA can save a pair of large
power FET switches and a 0.3-0.4 dB insertion loss. In other words, 3.6% overall PAE
increase is obtained.
frequency Insertion Loss [dB] Isolation [dBc]
Low band 0.3 22
High band 0.4 18
Table 6.1: Typical performance of one pair of FET band switches
The conditions for ISO peak and gain peak are different. If more ISO value is required, the
maximal gain is traded off against imperfect phase alignment.
6.3. Linear tapered diplexing DA
Similar to the tapering technique in classical DA, the tapering technique should also be
applied in the diplexing DA to improve the PAE and linearity performance [101]. Figure 6.5
presents the block diagram for the proposed linear tapered diplexing DA.
6.3. Linear tapered diplexing DA
52
Cin1 Cin2 Cin3 Cin4
OM
N
LB
OM
N
LB
50
Ω
50
Ω
RFin βL
βH
Z0,2=8Ω Z0,1=5.3Ω Z0,3=5.3Ω
OM
N
HB
50
Ω
id1 id2 id3 id4
T1 T2 T3 T4
4Ω @HB4Ω@LB
TL TL
CRLH-TL
Figure 6.5: The proposed new linear tapered diplexing DA.
One stage of the tapered diplexing DA is illustrated in Figure 6.6. In comparison with the
classical tapered DA, the only difference is the additional LH-TL section. Except for
absorbing the gate source capacitance, the gate line should also equalize the drive level and
adjust the phase relationship between stages.
Drive level equalization is the same as for the tapered DA by setting the input coupling
capacitor value as:
Equation 6. 12
The phase shift on its left and right nodes is also shown in Figure 6.6 also. The two gain
peaks are also determined by the phase response in Equation 6.9 and Equation 6.10.
Generally, the phase relationships between stages always hold:
Equation 6. 13
Equation 6. 14
PHEMT
Cin
LRH LRH
Rgs
Cgs
Vgs
Vg
CLHCLH
LLH
∆ 1 =
2
Id
∆ 2 = +
2
θ= 0
Figure 6.6: One cell of the gate line in the tapered diplexing DA.
In practice, since the diplexing operation requires the fulfilment of the relative phase
relationship rather than meeting an absolute phase value, CRLH-TLs are only required in the
6.3. Linear tapered diplexing DA
53
2 centre stages. A complete schematic of the gate line is plotted in Figure 6.7. Only five
additional passive elements (blue in Figure 6.7) are required in comparison to the classical
tapered DA. The resultant drain current of four stages is shown in Figure 6.8.
Cin2
LRH
CLH
0.5CLH
LLH
Cin3
LRH LRH
CLH
LLH
Cin1
LRH/2
Cin4
LRH/2
T1
RFin
T2 T3 t4
Figure 6.7: The complete schematic of the gate line.
For tapered drain line design, the following phase relationship is required:
9.0E8 1.1E9 1.3E9 1.5E9 1.7E9 1.9E97.0E8 2.1E9
-300
-200
-100
0
-400
100
freq_swp
ph
ase
0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
frequency [GHz]
Ph
ase
[˚
]
-25
0
-15
0 -
50
50
1
50
2
50
θ1<θ2< θ3 < θ4
θ1>θ2>θ3>θ4
Figure 6.8: The phase of the drain current.
In case those low ohmic loads are terminated in both output ports, Meta and Xie [23,24] have
concluded that even with an un-tapered DA, 50% of power is wasted by the termination
resistor at the unwanted port. Therefore a low pass matching network is added at the LB
output port and a high pass matching network is added at the HB output ports, which
transforms the load impedance to 50Ω at the corresponding frequency and has high
impedance at the unwanted frequency. Since the impedance is much higher than the drain
line impedance at the unwanted frequency, a rough open circuit is presented at the output
node. The same situation of classical tapered DA can be reached. Besides, this high reflection
matching network increases the ISO (Figure 6.5).
6.3. Linear tapered diplexing DA
54
Due to the symmetrical output port on both sides, strict drain line tapering is impossible. For
example, when the leftmost drain line section has a characteristic impedance of 4RL as in the
classic case (Figure 6.9), considering the three right transistors as a single device, they thus
look into the 4RL section at a low band frequency. Consequently, the total maximal output
power of the three right stages ( is limited by:
Equation 6.15
.
Cin1 Cin2 Cin3 Cin4
OM
N
LB
OM
N
LB
50
Ω
50
Ω
RFin βL
βH
Z0,2=8Ω Z0,1=16Ω
Z0,3=5.3Ω
OM
N
HB
50
Ω
id1 id2 id3 id4
T1 T2 T3 T4
4Ω @HB4Ω@LB
TL TL
CRLH-TL
Figure 6.9: An incorrect schematic when strict tapering is applied in diplexing DA.
Which is only a third of the desired value, and hence the Pout,max of the complete DA
decreases. As a result, the characteristic impedance of the leftmost drain line section should
be decreased to . For a high band the case is reversed (Figure 6.5). Theoretically, there
is always one out of the total four stages facing non-optimal load impedance conditions. In
practice, the lumped characteristic increases the load of the non-optimal stage. Here the high
band case is explained as an example. The phase shift of TL between stage T1 and T2 (Figure
6.5) is smaller than λ/10, so the two stages can be seen as lumped connected and together
look into the centre TL with characteristic impedance of 2RL, the impedance is thus:
Equation 6.16
The impedance of stage T2, T3 and T4 can be calculated as the conventional tapered DA
according to Equation 5.13:
Equation 6.17
Equation 6.18
Equation 6.19
For low band frequencies, the load impedance of stage T4 is improved by the same effect. As
a result, all the transistors face quasi-optimal load impedance conditions at both frequency
6.3. Linear tapered diplexing DA
55
bands. In Figure 6.10 the loadlines of all the four stages are shown. At both frequencies, the
stages far away from the corresponding output have slightly higher drain current to
compensate for the drain line loss according to Equation 5.19.
1 2 3 4 50 6
0.1
0.3
-0.1
0.5
vds
ids
1 2 3 4 50 6
0.1
0.3
-0.1
0.5
vds
ids
0 1 2 3 4 5 6
VDS [V] (a) 890 MHz
I DS
[A
]
-0.1
0.1
0.3
0.5
Ideal class A 16Ω load line
I DS
[A
]
-0.1
0.1
0
.3
0
.5
0 1 2 3 4 5 6
VDS [V] (b) 1.88 GHz
Ideal class A 16Ω load line
Loadlines of Stage 1-4
Figure 6.10: The four stages loadline of the diplexing TWA from EM/HB co-simulation.
Similar to a classical tapered DA, the stage bypass for PAE enhancement is also available for
this new structure. As the two stages located near the corresponding output port are switched
off, the two stages that are still in operation together face the centre drain line section with
Z0=2RL. Furthermore, the up-transformation effect still takes place.
For the case where three stages near the corresponding output port are switched off, the single
on-stage faces a low impedance of 4/3RL, rather than 4RL with the classical tapered case. The
small load impedance undermines the benefit of the ¼ quiescent current in this mode. The
up-transformation effect cannot help due to the small inductance value. Therefore only two
power modes are available for this diplexing tapered DA.
6.4. Circuit application discussion
56
6.4. Circuit application discussion
A single output matching network to cover the entire 3G TX bandwidth of 800-2000 MHz is
very challenging. Therefore with conventional broadband PA design, a band selection switch
with two separate matching networks for LB and HB is much easier. As discussed in the
previous section, by using this new tapered diplexing DA, switches can be eliminated and
hence 3.6% more PAE can be obtained while preserving the same ISO value of 20 dBc. The
module architecture of this configuration is illustrated in Figure 6.11.
Besides which, this structure is capable of load balancing and spectrum aggregation
techniques. This topic has been introduced in section 4.3 and practically achievable
functionality and performance will be presented in the next section.
Diplexing
TWA
RFin
LB
OMN
HB
OMN
824-915 MHz
1710-1980 MHz
824-849
869-894
880-915
925-960
1710-1755
2110-2155
1850-1910
1930-1990
1920-1980
2110-2170
Figure 6.11: Module architecture by using the diplexing DA.
6.5. PCB demonstrator
This section briefly describes the realization of the diplexing tapered DA demonstrator. The
hardware implementation provide an opportunity to verify the new circuit concept and to
measure its performance, as it is not possible to capture all the effects from the simulation.
The functionalities of the PCB demonstrator to be verified includes:
Diplexing
Tapering: The PAE should be higher than the reported value from [23] of the non-
tapered diplexing TWA.
Linearity: As a benefit of tapering.
6.5. PCB demonstrator
57
Spectrum aggregation and load balancing ability
Backoff modes: In this mode, the trend of PAE improvement and P1dB decrease
should be observed. However, since the AC shunt switch is not implemented in the
PCB design, the linearity requirement in the back-off mode cannot be satisfied
6.5.1. Circuit description
The Avago’s enhancement mode PHEMT transistor ATF-541M4 is selected, due to its small
package size (Minipak, 1.4*1.2mm) and the availability of a large signal model. Each of the
total four stages comprises two identical transistors. The circuit is implemented in a Rogers
RO4450 double layer configuration, each of which is 100 um thick. The reason for choosing
such a thin material is that the realized conductor has a smaller inductance, making it easy to
realize the drain artificial transmission line with characteristic impedance in the range of
some ohm.
The drain line design is critical because the required inductance is very small (0.2 nH and 0.6
nH) and the distance between the two stage transistors is constrained by the transistor’s large
physical size (>1mm). As a result, a very wide drain line (800 um width) is fabricated on the
lower layer (shadow in Figure 6.12). The conductor beside the drain line on the upper layer is
the common ground. Furthermore, the transistors must be rotated to shorten the distance
between two stages in the layout. The gate line has higher characteristic impedance (18 Ohm)
than the drain line, so its realization is easier. It is implemented by a long microstripe line of
300 um width on the upper layer.
In order to match the gate line to the common interface impedance of 50 Ω at the input, a
dual band impedance matching network with two L shape sections has to be used. This
matching network limits the fractional bandwidth of the circuit. The low band output port is
matched by a low pass L shape matching network at 890 MHz and the high band output port
is matched by a high pass L shape matching network at 1.88 GHz, so that both ports have
high reflection at unwanted frequencies.
Each stage is connected to a separate bias circuit. It enables the possibility of switching off
part of the stages. The bias circuit comprises an LC and an RC section. The RC low pass
section stabilizes the circuit at low frequency.
In the end, the complete layout has been simulated using ADS momentum, and then used
again in circuit simulation. The circuit contains around 140 internal and single ports.
6.5. PCB demonstrator
58
input
Output
LB
Output
HB
Vcc
Drain line in
lower layer can
be seen a little
Dual
narrowband
matching
Bias
Bended
gate line
Bias
Bias
Bias
Figure 6.12: Layout of the PCB demonstrator, PCB size 5 cm*5 cm.
6.5.2. Measurement results
The measured 3-port S-parameters of the demonstrator are shown in Figure 6.13. Port 1 is the
input port and port 2 and 3 are output ports for LB and HB, respectively. The maximal small
signal gains of about 10 dB are accomplished at 920 MHz and 1830 MHz. Obviously the
bandwidths are limited by the bandwidth of the input and output matching network, which
are used to match the 50Ω common interface. The isolation between the two output ports is
more than 20 dB at both output frequency ranges.
6.5. PCB demonstrator
59
0.5 0.9 1.3 1.7 2.10.1 2.5
-25
-15
-5
5
-35
15
freq, GHz
dB
(S(2
,1))
dB
(S(4
,3))
-2d
B(S
(1,1
))d
B(S
(2,2
))d
B(S
(4,4
))
dB
(S)
S21S31
S22S11
S33
Figure 6.13: The measured S-parameters of the PCB demonstrator.
The single-tone measurement has been performed first and the results are plotted in Figure
6.14. The output power is measured by a broadband power meter, so that the harmonic
content is also regarded as fundamental power. Since the second harmonic is at least 20 dBc
lower than the fundamental power as measured by a spectrum analyser, the accuracy of the
power measurement is still better than 99% without harmonic filtering.
For LB operation, the second harmonic is measured at the HB output port. Since the
fundamental power is suppressed at the HB port, the second harmonic content has
comparable power to the fundamental power at the HB port. The measured output power at
the HB port is thus the sum of the fundamental tone and second harmonic (Figure 6.14.e).
The real ISO by LB excitation is 3 dB better.
Nevertheless, diplexing functionality with more than 15 dBc ISO has been proven.
6.5. PCB demonstrator
60
6
7
8
9
10
16 20 24 28 32
ga
in [
dB
]
Pout [dBm]
Measurement LB_Port
Simulation_LB_Port
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
-15
-5
5
15
25
35
5 10 15 20 25
Po
ut
[dB
m]
Pin [dBm]
6
7
8
9
10
16 20 24 28 32
ga
in [
dB
]Pout [dBm]
Measurement_HB
Simulation_HB
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
-15
-5
5
15
25
35
5 10 15 20 25
Po
ut
[dB
m]
Pin [dBm]
(a) (b)
(c) (d)
(e) (f)
Figure 6.14: Measured performance of the PCB demonstrator in comparison to the simulation.
Left: fin=890 MHz; Right: fin=1.88 GHz.
The reason for the P1dB degradation showing up with the measurement is a result of
incorrect modelling of the transistor. The Avago’s Advanced Curtice model (Figure 6.15),
which is modelled for LNA purposes, is used in the original circuit design. From DC
measurement, the transistor reaches its maximal allowed current when VGS=0.75 V. The
model is only valid up to this point and hence the transconductance compression
characteristic is not included. As the input voltage peak exceeds about 0.75V, the power gain
decreased sharply because in reality the transconductance decreases.
6.5. PCB demonstrator
61
20 24 2816 32
5
6
7
8
9
4
10
Pout
ga
in
0.2 0.4 0.6 0.80.0 1.0
200
400
600
0
800
VGS [V]
Gm
[m
S]
16 20 24 28 32
Pout [dBm] (b)
0 0.2 0.4 0.6 0.8 1
VGS [V] (a)
Gain
[d
Bm
]
4
5
6
7 8
9
1
0
DC
g
m[m
S]
0
40
0
8
00
Avago’s Curtice model Author’s own simplified statz model
Modelithics model
of ATF 54143Measurement
Real measured
data because
maximal DC
current reached
The gm shape of Modelithics model
forecasts the measured gain shape most
accurately.
The own model is the most
pessimistical.
Avago’s curtice model is the most
optimistical.
Figure 6.15: (a) DC transconductance (b) gain at 1.88 GHz according to different models and
measurements. (Modelithics models utilised under the university license program from
Modelithics, Inc., Tampa, FL, USA)
Based on our own measurements, a simplified Statz model has been created. This model has
very similar performance to the Modelithics one and offers a more accurate model of the
ATF54143, which has the same chip design as ATF541M4 except for the packaging, and
hence their DC transconductance should be comparable.
Both our own Statz model and that of the Modelithics show more accurate transconductance
shapes, which reaches their peak when VGS= 0.75V and then starts going into compression.
Based on own Statz model, the lowest gm value results in the lowest P1dB point. Based on
Avago’s Curtice model, the highest gm value results in the best P1dB performance. In the
middle, the Modelithics model represents the DC gm with best accuracy, which reflects a gain
shape closer to the measurements. However, the parasitics of the Modelithics ATF54143
model is different, so that it cannot be used to directly simulate the RF gain.
In Figure 6.16 the performance in back-off mode is plotted. The trend of the PAE
improvement and P1dB decrease, behave as desired. The gain with the measured data is
higher than with the simulation, due to the incorrect modelling of the drain source
capacitance Cds in Avago’s model, which has a constant Cds value. In practice, this capacitor
decreases to approximately a third of its original value when the transistor is in the off-state,
and hence the up-transformation of the load impedance occurs. This phenomenon is
previously explained in 5.5.
6.5. PCB demonstrator
62
6
7
8
9
10
16 20 24 28 32
ga
in [
dB
]
Pout [dBm]
Meassurement_LB_Port
Simulation_LB_port
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
6
7
8
9
10
16 20 24 28 32
ga
in [
dB
]
Pout [dBm]
Measurement_HB_Port
Simulation_HB_Port
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
(a) (b)
(c) (d)
Figure 6.16: Measured performance of the PCB demonstrator in comparison to the simulation
when only two stages are on. Left: fin=890 MHz; Right: fin=1880 MHz.
A conventional 2-tone measurement setup is used to verify the load balancing capability.
Two signals with frequencies of 890MHz (LB signal) and 1.88GHz (HB signal) are added
together through a power combiner to the PA’s input port. The amplified signal at both output
ports is combined through another power combiner. The combined signal is measured by
spectrum analysers and power meters.
Figure 6.17.a and b illustrate the measured results by power sweeping the LB signal. A
constant HB signal of 6 dBm is applied during the power sweeping. The performance
degradation in comparison with the single tone power sweeping measurement (Figure 6.14.a
and c) is negligible. Similar results are obtained for HB sweeping while applying a constant
LB signal of 6 dBm (Figure 6.17.c and d in comparison with Figure 6.14. b and d). Due to the
agreement between 1-tone and 2-tone measurements, the difference between simulation and
measurement results of 2-tone performance is also caused by the incorrect modelling.
By sweeping the power of both tones simultaneously, the PAE enhancement in a large back-
off level and the decrease of the P1dB point are also as intended.
6.5. PCB demonstrator
63
(f)(e)
(d)(c)
(b)(a)
7
8
9
10
11
16 20 24 28 32
ga
in [
dB
]
Pout [dBm]
Meas Sim
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
6
7
8
9
10
16 20 24 28 32
ga
in [
dB
]
Pout [dBm]
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
6
7
8
9
10
16 20 24 28 32
ga
in [
dB
]
Pout [dBm]
0
10
20
30
40
50
16 20 24 28 32
PA
E [%
]
Pout [dBm]
Figure 6.17: Measured performance by two carrier excitation in comparison to the simulation.
(a,b) Pin,HB=6dBm, sweeping Pin,LB. (c,d) Pin,LB=6dBm, sweeping Pin,HB . (e,f) Pin,LB= Pin,HB,
sweeping 2 tones simultaneously.
Figure 6.18 shows the spectrum of the same measurement. Similar to a conventional closely
spaced 2-tone measurement, the IMD products are not avoidable, but the space between the
IMD and the fundamental tone is much larger. In other words, these IMDs can be filtered out
without deteriorating the linearity.
6.5. PCB demonstrator
64
Ref 20 dBm Att 45 dB*
1 AP
CLRWR
B
3DB
RBW 3 MHz
VBW 10 MHz
SWT 35 ms
590 MHz/Start 100 MHz Stop 6 GHz
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
1
Marker 1 [T1 ]
11.15 dBm
884.775641026 MHz2
Marker 2 [T1 ]
8.56 dBm
1.877564103 GHz
Date: 30.AUG.2010 10:00:14
Ref 20 dBm Att 45 dB*
1 AP
CLRWR
B
3DB
RBW 3 MHz
VBW 10 MHz
SWT 35 ms
590 MHz/Start 100 MHz Stop 6 GHz
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
1
Marker 1 [T1 ]
0.77 dBm
884.775641026 MHz2
Marker 2 [T1 ]
9.32 dBm
1.877564103 GHz
Date: 30.AUG.2010 10:05:19
(b) Output power at f1 is 9 dB lower than at f2.
f1=890MHz
Pout=24dBmf2=1880MHz
Pout=23dBm
2f1
f2-f1
3f1-f2 2f2-3f14f1-f2
f1+f2
f1=890MHz
Pout=14dBm
f2=1880MHz
Pout=23dBm
f2-f1f1+f23f1-f2 2f1
Spurious emission
(a) Same Output power at both f1 and f2
Figure 6.18: Spectrum by 2-tone excitation at 890 MHz and 1880 MHz.
6.5. PCB demonstrator
65
Ref 20 dBm Att 40 dB*
1 AP
CLRWR
A
190 MHz/Start 100 MHz Stop 2 GHz
3DB
RBW 3 MHz
VBW 10 MHz
SWT 5 ms
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
Date: 16.SEP.2010 17:00:39
UMTS at f1=890 MHz
Pout=27dBmWLAN at f2=1.88 GHz
Pout=17dBm
f2-f1 2f13f1-f2
25dBc
Figure 6.19: Spectrum by simultaneous UMTS and WLAN signal excitation.
The circuit can be simultaneously driven by two modulated signals at different frequencies.
Here simultaneous amplification of a UMTS and a WLAN (802.11a, 64QAM OFDM) signal
is given as an example. Since this circuit is designed for a UMTS LB and HB frequency, in
the measurement the UMTS signal is generated at 890 MHz and the WLAN signal is fed at
1.88 GHz instead of 2.45 GHz. In principle it does not impact on the verification of this
concept.
In Figure 6.19 the spectrum with the fundamental and mixing products is shown. The mixing
products have large frequency distance in relation to the fundamental signal, and hence they
can be filtered out easily, without degradation of linearity. The most significant mixing
product lies at the frequency f2-f1 which is 25 dBc lower than the fundamental power of LB.
It is possible to suppress this directly with a conventional output duplexer filter in order to
fulfil the specification of -30dBm/MHz, without the effort of fitting an additional narrowband
filter or new duplexer filter design.
In Table 6.2, the maximal linear output power and the corresponding PAE by different signal
excitations are listed. The linearity of UMTS is limited by ACP_5MHz>40 dBc and the
linearity of the WLAN is limited by EVM<5.62%. The PA’s ability for not only conventional
single signal (UMTS, WLAN) amplification, but also for simultaneous dual signal
amplification has been verified. For the case of simultaneous UMTS and WLAN signal
amplification, the total PAE is enhanced. The total PAE in the 2-tone case is calculated as:
Equation 6.20
6.6. On-chip demonstrator
66
LB signal Output
power[dBm]
HB signal Output power
[dBm]
LB Pout,max,lin [dBm]
HB Pout,max,lin [dBm]
PAE/ Total PAE in
2tone case [%]
UMTS
25.6
25.1
UMTS
23.5 16
WLAN 15.8 7.5
Single tone
Pout=14
UMTS 22.2 17.1
UMTS Single tone
Pout=14
24.9 25.2
UMTS
Pout=23
WLAN 15.8 21.2
UMTS
Pout=17
WLAN 15.8 14.4
Table 6.2: The maximal linear output power and the corresponding PAE by different signal.
Although the simultaneous amplification of 2 UMTS signals has not been measured due to
lack of equipment, it should also be possible.
6.6.On-chip demonstrator
Due to physical restrictions and lack of an accurate transistor model, the performance of the
previous PCB demonstrator is not good. The real achievable performance of the circuit
concept should be explored in an on-chip demonstrator. In the new demonstrator, the driver
stage is also included, so that the cascading ability between 2 stages can be verified and the
bandwidth data of the complete circuit can be obtained.
Furthermore, the new bias circuit is applied in this design. The linearity is improved and the
concept of PAE enhancement with reduced power level is verified.
6.6.1. Circuit description
For the chip design, WIN PH5000 E/D mode GaAs PHEMT technology is used. The block
diagram of the 2-stage PA is shown in Figure 6.20. A conventional tapered distributed
amplifier is used in the driver stage and the new diplexing tapered distributed amplifier is
used in the second stage.
6.6. On-chip demonstrator
67
18Ω 4 Ω 50 Ω 50 Ω
Driver
(tapered TWA)
RFin
Diplexing
tapered TWA
LB OMN
HB OMN
Load
Load
Bias
circuitLinearizing Bias1 with
AC shunt switch
No input
matching
No interstage
matching
Linearizing Bias2 with AC shunt switch
Figure 6.20: Block diagram of the on-chip demonstrator.
Due to the good cascading ability and flexibility for choosing suitable gate line impedance,
an input and interstage matching network is not required.
Stage1
Stage2
Stage4
Stage3
S33
freq_swp (890000000.000 to 1880000000.000)
Vd
s1
_re
fl[1
]/V
ds1
[1]
Vd
s2
_re
fl[1
]/V
ds2
[1]
Vd
s3
_re
fl[1
]/V
ds3
[1]
Vd
s4
_re
fl[1
]/V
ds4
[1]
Vce
1_
refl[1
]/V
ce
1[1
]V
ce
2_
refl[1
]/V
ce
2[1
]V
ce
3_
refl[1
]/V
ce
3[1
]V
ce
4_
refl[1
]/V
ce
4[1
]
PA
Driver
Figure 6.21: Load impedance of each stage at 890 MHz and 1880 MHz.
For the driver stage, the characteristic impedance of the gate line is 50 Ω. On the tapered
drain line, the characteristic impedances are 72 Ω, 36 Ω and 18 Ω. The maximal output
power of the driver is about 24 dBm. All the four stages are connected to single bias circuits
through resistors. The total quiescent current of the driver is approx. 60mA. For the PA stage,
the gate line has a characteristic impedance of 18 Ω, the drain line impedances are 5.3 Ω, 8 Ω,
5.3 Ω. The simulated load impedances of each stage are plotted in Figure 6.21. At both
frequencies, the load impedances of each stage equal 16 Ohm for PA stage and 72 Ohm for
the driver stage.
The dynamic bias circuit is used in the PA stage to compensate for the gain expansion. This
dynamic bias technique is a narrowband technique. For the desired shape of the bias voltage,
it requires different capacitance values for LB (10 pF) and HB (5 pF). Due to the poor
performance in LB without dynamic bias circuit, the suitable capacitor value for LB is used.
Since this value is larger than the required value for HB, the circuit supplies constant bias
6.6. On-chip demonstrator
68
voltage for HB as a classical bias circuit. As a result, the gain expansion for LB has been
decreased to 0.8 dB while it is still 1.6 dB for HB (Figure 6.25).
In addition, for the purpose of PAE enhancement, two separate bias circuits are used. Vbias1
controls stages T1 and T2, and Vbias2 controls stages T3 and T4.
The OMNs are off-chip. A two-section l-shape low pass OMN is applied at the LB output
port while a two-section l-shape high pass OMN is applied at the HB output port to increase
the bandwidth..
RFin
RFout_LB RFout_HB
driver_out
PA_in
Vcc
VccVmode1
Vmode2
Vcc for bias circuit
Driver stage
PA stage
Vbias1
Vbias2
Figure 6.22: The chip layout. Total chip size is 4 mm * 3 mm.
6.6.2. Simulation results
6.6. On-chip demonstrator
69
1.0 1.4 1.80.6 2.2
-25
-15
-5
5
15
-35
25
freq, GHz
dB
(S(2
,1))
dB
(S(3
,1))
dB
(S(1
,1))
dB
(S(2
,2))
dB
(S(3
,3))
dB
(S)
S21
S31
S22
S11
S33
Figure 6.23: S-Parameter.
The 3-port S-parameters are shown in Figure 6.23. Port 1 is the input port and ports 2 and 3
are the output ports for LB and HB, respectively. The maximal gain is located at 900 MHz
and 1.6 GHz. The 3 dB bandwidths are roughly 20%. The Psat is shown in Figure 6.24, which
presents the same trend as the S-parameter. The 0.5 dB bandwidth is 9.4% for LB and 28.7%
for HB. The large bandwidth for HB is achieved thanks to the fact that the frequency
response of the OMN stays within the power contour most of the time.
8.0E8 1.0E9 1.2E9 1.4E9 1.6E9 1.8E9 2.0E9 2.2E96.0E8 2.4E9
31.00
31.25
31.50
30.75
31.75
freq_swp
Pout1
Pout2
LB Port: 9.4%
HB Port: 28.7%
700 1100 1500 1900
Freqency [MHz]
Psat[d
Bm
]
30
.75
31
.25
3
1.7
5
Figure 6.24: Psat and the corresponding 0.5 dB BW.
The simulation results using power sweeping are plotted in Figure 6.25. Due to the high
quiescent current of the driver (60 mA) and PA stage (120 mA), the PAE is about 10% lower
than with the conventional narrowband PA at its maximal linear output power of 28dBm.
Fortunately significant PAE enhancement in the back-off mode is observed while preserving
enough IM3 performance.
6.6. On-chip demonstrator
70
14 16 18 20 22 24 26 28 3012 32
20
22
24
18
26
Pout1
ga
in
dBm(CRLH_PA_TL7..Vout1[1])
18 20 22 24 26 2816 30
15
20
25
30
35
40
10
45
pout
IM3
18 20 22 24 26 2816 30
15
20
25
30
35
10
40
pout
IM3
-8 -6 -4 -2 0 2 4 6 8-10 10
-10
0
10
20
30
-20
40
Pavs
po
ut
14 16 18 20 22 24 26 28 3012 32
10
20
30
40
50
0
60
Pout2
PA
E2
Pout22_dBm
PA
E22
14 16 18 20 22 24 26 28 3012 32
20
22
24
18
26
Pout2
ga
in
dBm(CRLH_PA_TL7..Vout2[1])
-8 -6 -4 -2 0 2 4 6 8-10 10
-10
0
10
20
30
-20
40
Pavs
po
ut
14 16 18 20 22 24 26 28 3012 32
10
20
30
40
50
0
60
Pout1
PA
E1
Pout11_dBm
PA
E11
12 16 20 24 28 32
Pout [dBm] (a)12 16 20 24 28 32
Pout [dBm] (b)
12 16 20 24 28 32
Pout [dBm] (d)
-10 -5 0 5 10
Pin [dBm] (e)
PA
E [
%]
0
2
0
40
60
Pout[d
Bm
]
-20
0
20
40
Gain
[d
B]
19
22
25
Gain
[d
B]
18
2
2
2
6
16 18 20 22 24 26 28 30
Pout [dBm] (g)
IM3
[d
Bc]
15
2
5 3
5
45
12 16 20 24 28 32
Pout [dBm] (c)
PA
E [
%]
0
2
0
40
60
P
out[d
Bm
]
-20
0
20
40
-10 -5 0 5 10
Pin [dBm] (f)
IM3
[d
Bc]
15
2
5 3
5
45
16 18 20 22 24 26 28 30
Pout [dBm] (h)
Full power mode Backoff mode
Opposite port Opposite port
Figure 6.25: The simulated performance of the chip. Left: Fin=890 MHz; Right: Fin=1.88 GHz.
The maximal linear output power of both frequency bands and power modes according to the
envelope simulation are plotted in solid circles.
The ISO in full power modes is approx. 25 dBc. In backoff mode, the ISO decreases to 20
dBc at LB and 15 dBc at HB, because the effect of phase cancellation decreases. The
maximal linear output power from the envelope simulation is shown in Figure 6.25. a and b.
6.7. Triplexing and multiplexing DA opportunity
71
6.7.Triplexing and multiplexing DA opportunity
By utilising the same principle of the diplexing DA, the concept can be extended for
triplexing and multiplexing DA design. In the following an example of a triplexing DA is
given (Figure 6.26) [102]. In this design, two different CRLH-TLs are used in the gate line
for frequency diplexing at two different frequencies. Conventional RH-TLs are used in the
drain line. The direction of each section’s phase constant is listed in Table 6.3. Since the
phase constant of the CRLH-TL decreases monotonous with frequency, the fourth
configuration at which β of CRLH-TL1 is negative while β of CRLH-TL2 turns positive is
therefore not possible.
Frequency
[MHz]
β of CRLH-TL1 (y-direction) β of CRLH-TL2 (x-direction)
fL=850 + (up) + (left)
fH1=1850 + (up) - (right)
fH2=2500 - (down) - (right)
Not possible - (down) + (left)
Table 6.3: The phase constant configuration of the two CRLH-TLs in Triplexing DA.
The drain line uses conventional TL and its phase direction follows the gate line. At fL=850
MHz, the information travels through CRLH-TL1 in the (+y)-direction and through CRLH-
TL2 in the (-x)-direction. And hence all the current is added in-phase at port 2. As the
frequency increases, the direction of CRLH-TL2 changes at first. At fH1=1850 MHz, the
information travels through CRLH1 still in the (+y)-direction but through CRLH-TL2 in the
(+x)-direction. The current is added at port 3. As the frequency continues to increase, the
CRLH-TL1 changes direction also. At fH2=2500 MHz, the information travels through
CRLH1 in the (-y)-direction and through CRLH-TL2 in the (+x)-direction. The current is
added at port 4 in-phase.
6.7. Triplexing and multiplexing DA opportunity
72
P2
P3
P4
f Lf H1
f H2
fL
fH1
fH2
RFin
P1
CRLH-TL1
CRLH-TL2
TL
X direction
Y d
ire
ctio
n
Figure 6.27: Block diagram of a 2 dimensional triplexing DA.
The S-parameters are shown in Figure 6.28. Three gain peaks are observed as predicted. The
ISO is only about 6 dB, because only one CRLH-TL section is responsible for one band
selecting in this simple design. By increasing the CRLH-TL sections for each band selecting
to three as in the previously introduced diplexing DA, an ISO of 20 dBc may be possible.
1.0 1.5 2.0 2.5 3.0 3.50.5 4.0
-10
0
10
20
-20
30
freq, GHz
dB
(S(2
,1))
dB
(S(3
,1))
dB
(S(4
,1))
dB
(S)
-30
-20
-1
0
0
1
0
2
0
0.5 1 1.5 2 2.5 3 3.5 4
Frequency [GHz]
S21
S31
S41
Figure 6.28: The S-parameter of the triplexing DA.
The principle of using CRLH-TLs for frequency selection at two different frequencies may
be expanded again for multiplexing DA. By combining two triplexing amplifiers through the
6.7. Triplexing and multiplexing DA opportunity
73
third CRLH-TL and several TLs, quadplexing can be obtained. The phase constant of each
CRLH-TL is shown in Table 6.4. The color filled area show the frequency of direction
change.
Frequency
[MHz]
2 identical triplexing amplifier β of CRLH-TL3
β of CRLH-TL1 β of CRLH-TL2
fL=850 + + +
fH1=1850 + - +
fH2=2500 - - +
fH3=5000 - - -
Table 6.4: The phase constant configuration of the two CRLH-TLs with triplexing DA. The
sign change of each section is emphasized by different colour.
P2
P3
TL
CRLH-TL3
P4
P5
RFin P1
Triplexing
DA
Triplexing
DA
Figure 6.29: Block diagram of a 3-dimensional quadplexing amplifier.
7. Conclusion and future work
74
7. Conclusions and future work
Within this dissertation, the tapering technique is firstly used in diplexing distributed
amplifier. Therefore two important requirements for mobile phone power amplifier are
achieved: linearity and a higher PAE.
In a (diplexing) distributed amplifier, since the characteristic impedance of the gate line can
be arbitrarily chosen, the input and interstage matching network can be eliminated, which
improves the bandwidth and simplifies the circuit structure.
The diplexing feature saves a pair of lossy SP2T switches, and hence the overall PAE is
improved by approx. 3.6% while preserving 20 dBc ISO. Since there is no switch between
the two output paths the two paths can be activated simultaneously, which enables load
balancing and spectrum aggregation techniques. Load balancing is used to improve the
overall efficiency by amplifying multiple frequency band signals. Spectrum aggregation
needs to be supported by the power amplifier for LTE Advanced.
For mobile applications, battery saving is also a very important issue. Due to the inherent
multistage nature of the (diplexing) distributed amplifier, the opportunity to support multiple
power modes is illustrated for the first time. The PAE at reduced power levels is improved.
The circuit contains multiple large and lossy inductors. As a consequence, the efficiency is
approx. 10% lower and the chip area is approx. 5 times larger than the single ended design in
a conventional process. The linearity of this circuit is poor and a new linearizing method is
shown to cure it.
Due to the multiple feedback loops and non-linear devices, the circuit presents the risk of
parametric and large signal oscillation. For this reason a special method to analyse the
stability at a large signal regime is provided.
Furthermore, the opportunity to expand the diplexing concept to triplexing and multiplexing
DA has been introduced. The new circuit concept contains the same advantages and
drawbacks of (diplexing) DA.
In future work, the multiplexing concept should be investigated in more detail. The on-chip
demonstrator has not yet been fabricated, but a real demonstrator would be very useful. In
addition, the opportunity to reduce the chip size by using LTCC/laminate for inductors and
transmission lines, or by using off-chip SMD LC filters, etc. should be investigated.
7. Conclusion and future work
75
Zusammenfassung und Ausblick
Im Rahmen dieser Dissertation wurde erstmals die stufenweise Anpassung des
Wellenwiderstandes (Tapering) in verteilten Mehrtorverstärkern mit Diplexerfunktion
eingesetzt. Zwei wichtige Anforderungen an die Mobilfunkanwendung wurden dabei erreicht:
Linearität und hoher Wirkungsgrad (PAE).
Da der Wellenwiderstand der Eingangsleitung in verteilten Verstärkern (mit Diplexerfunktion)
beliebig wählbar ist, kann das Anpassungsnetzwerk der Eingangs- und Interstufen eliminiert
werden, wodurch die Bandbreite erhöht und die Schaltungsstruktur vereinfacht wird.
Die Diplexerfunktion erspart verlustbehaftete Ausgangsbandumschalter, wodurch der
gesamte Wirkungsgrad unter Beibehaltung der 20 dBc ISO - um 3,6% verbessert wird. Da es
keinen Schalter zwischen den beiden Ausgangspfaden gibt, können sie simultan aktiviert
werden, wodurch Last-Balancierung- und Spektrum-Aggregationstechniken ermöglicht
werden. Mit Hilfe von Last-Balancierung wird die Gesamteffizienz verbessert, wenn
gleichzeitig mehrere Frequenzbänder zu verstärken sind. Die Spektrum-Aggregation wird für
Leistungsverstärker benötigt, die LTE-Advanced unterstützen.
Für Mobilfunkanwendungen ist die Minimierung der Stromaufnahme entscheidend. Hier
wird erstmals gezeigt, wie verteilte Verstärker (mit Diplexerfunktion) mehrere
Energiesparmodi unterstützen. Dabei wird die PAE bei reduzierter Ausgangsleistung
verbessert.
Die Schaltung enthält mehrere große und verlustbehaftete Spulen. Infolgedessen ist im
Vergleich zu herkömmlichen Designs ohne Spulen der Wirkungsgrad ca. 10% geringer, bei
zugleich fünfmal größerer Chipfläche. Um die unzureichende Linearität dieser Schaltung zu
verbessern, wird eine neue Linearisierungsmethode vorgestellt.
Aufgrund von mehreren Rückkopplungsschleifen und nichtlinearen Bauelementen birgt die
Schaltung das Risiko der Großsignalinstabilität in sich. Daher wird eine spezielle Methode
eingeführt, um die Großsignalstabilität zu analysieren.
Darüber hinaus hat die Erweiterungsmöglichkeit des Diplexer-Konzepts zum Triplexer- und
Multiplexer-DA geführt. In zukünftigen Arbeiten könnte diese Multiplexerfunktion noch
detaillierter untersucht werden. Ebenfalls denkbar sind kostenoptimierte Chipvarianten mit
minimierten Chlipflächen, bei denen die Induktivitäten extern als SMD oder
substratintegrierte Spulen ausgeführt sind.
Appendix A
76
Appendix A: The mathematical expression of IMD
Assuming an input signal Vi consisting of two tones at the frequencies f1 and f2, and having
amplitudes of V1 and V2, respectively.
Equation A.1
At the output side, the drain-source current may be approximated by a 2-dimensional Taylor
series if the transconductance is seen as the single nonlinearity source:
Equation A.2
Expanding it out:
( )
[ (
)
(
) ]
(
)
(
)
(
)
Equation A.3
where is the DC component. The exact expressions of G1, G2 and G3 can be found in
[103]. For commonly accepted approximation, they are defined as:
Equation A.4
Equation A.5
Equation A.6
As a result, despite the different physical means of G1,G2,G3 and gm,gm2,gm3, they are
treated similarly.
By large signal excitation, the total IM3 product is a probability function of the input voltage.
For simplicity, assuming , then the output power of fundamental and IM3 are defined
as:
(
)
Equation A.7
(
)
Equation A.8
Appendix B
77
[( )
(
)
] Equation A.9
Since the input voltage Vi depends on gate bias voltage Vbias and the magnitude of input
voltage swing, a 3D contour is plotted in Figure A.1. The obvious IM3 spot shift has been
shown. When the bias voltage follows this trend, the best linearity can be obtained.
Vbias [V] Vin [V]
IM3
[d
Bc]
0
5
0 1
00
Figure A.1: Typical IM3 dependence of Vbias and Vin. Simulated by WIN PH5000 process E-
PHEMT transistor.
Appendix B: The system identification process
The Levenberg–Marquardt algorithm (LMA) is used for the identification process, for its
fast convergence time and robustness. After being given the numbers of pole and zero,
the algorithm is illustrated in Figure A.2, where the initial guess is . In each
iteration, is replaced by . Here an approximation has been made:
( ) ( ) Equation A.10
where is the gradient of the function f at one specific point .
( )
Equation A.11
Returning to the variation:
Appendix B
78
( ) ‖ ( ) ‖ Equation A.12
In order that the variation is the smallest:
[ ( )] Equation A.13
where J denotes the Jocob-matrix. From the upper linear equations, the can be calculated
for next iteration. For better convergence, the algorithm has been modified by Marquardt:
( （ ）) [ ( )] Equation A.14
The process diagram is shown in Figure A.2.
β,μ0,ϑ,x0,k=0
Calculate
rk,sk,jk,Qk,gk,Ik
Solve
(Qk+μkIk)∆ =-gk
Calculate
xk+1,rk+1,sk+1
STOP? Output xk+1,sk+1
Check sk+1≤ sk+1+βgkT∆
Y
μk+1 =μk/ ϑ
k =k+1
μk+1 =μkϑ
N
Y
N
Figure A.2: Algorithm of the system identification program.
The solution can be obtained within 30 seconds with a normal PC. However, the numbers of
pole and zero are unknown. Due to the small convergence time, the simplest but the most
time consuming algorithm can be applied: sweeping the number of both pole and zero from 1
to 15, the global solution with the smallest error function is selected. The complete process
takes about 100 minutes.
Appendix B
79
107 108 109 1010
Frequency [Hz]
Rea
l Im
ag
107 108 109 1010
Frequency [Hz]
Figure A.3: The real- and imaginary part of the transfer function. Red: simulation, blue:
identified.
In Figure A.3, the real and imaginary parts of the simulated transfer function are compared
with the identified transfer function. The identified transfer function is smoother, because
parts of the non-critical pole-zero at high frequency have not been identified.
Biboliography
80
Biboliography
[1] U. Bauernschmitt, C. Block, P. Hagn, G. Kovacs, E. Leitschak, A. Przadka, and
C.C.W. Ruppel, “Frontend-Lösungen für Alleskönner,” EPCOS Components Magazin,
2007.
[2] G. Fischer, “Metamaterial Strukturen für den Einsatz in frequenzagilen
Hochfrequenzsystemen,” Gerotron EEEfCOM, Hamburg: 2006.
[3] G. Fischer, “Next-Generation Base Station Radio Frequency Architecture,” Bell Labs
Technical Journal, vol. 12, 2007, pp. 3-18.
[4] G. Fischer, W. Eckl, and G. Kaminski, “RF-MEMS and SiC/GaN as enabling
technologies for a reconfigurable multi-band/multi-standard radio,” Bell Labs
Technical Journal, vol. 7, Mar. 2003, pp. 169-189.
[5] L. Zhao, A. Pavio, and W. Thompson, “A 1 Watt, 3.2 VDC, High Efficiency
Distributed Power PHEMT Amplifier Fabricated Using LTCC Technology,”
International Microwave Symposium Digest, Philadelphia: 2003, pp. 2201-2204.
[6] K. Narendra, C. Paoloni, E. Limitfi, and J.M. Collantes, “High performance 1.5W
pHEMT Distributed Power Amplifier with Adjustable Inter-Stage Cascaded Network for 10 to 2000 MHz,” 14th conference on Microwave Techniques, Prague: 2008.
[7] K.M. Eisele, R.S. Engelbrecht, and K. Kurokawa, “Balanced Transistor Amplifiers for
Precise Wideband Microwave Applications,” International Solid-State Circuits
Conference, 1965.
[8] J. Shumaker, “High Power GaAs FET Amplifiers: Push-Pull versus Balanced
Configurations,” Wireless Symposium, San Jose: 2001.
[9] W. Bakalski, M. Zannoth, M. Asam, W. Thomann, B. Kapfelsperger, P. Pfann, and E.
Rampf, “A Load-Insensitive Quad-Band GSM/EDGE SiGeC-Bipolar Power Ampli er
with a Highly Ef cient Low Power Mode,” Radio and Wireless Symposium, Orlando:
2008, pp. 203-206.
[10] G. Zhang, S. Chang, S. Chen, J. Sun, W. Hillcrest, and N. Park, “Dual Mode
Efficiency Enhanced Linear Power Amplifiers Using a New Balanced Structure,”
Radio Frequency Integrated Circuits Symposium, Boston: 2009, pp. 245-248.
[11] Datasheet, RFMD RF6285.
[12] Datasheet, RFMD RF6281.
[13] J. GARCIA-Munoz, L. Jimeneny-Martin, V. Gonyaley-Posadas, and F.J.A.L. E.,
“Dual Band High Efficiency Power Amplifier Based on CRLH Lines,” Radio
Engineering, vol. 18, 2009, pp. 567-578.
Biboliography
81
[14] P. Colantonio, F. Giannini, R. Giofr, and L. Piazzon, “Simultaneous Dual-Band High
Efficiency Harmonic Tuned Power Amplifier in GaN Technology,” 2nd European
Microwave Integrated Circuits Conference, Munich: 2007.
[15] K. Uchida, Y. Takayama, T. Fujita, K. Maenaka, and C. Sciences, “Dual-Band GaAs
FET Power Amplifier With Two-Frequency Matching Circuits,” Asia-Pacific
Microwave Conference, Suzhou: 2005.
[16] S.H. Ji, C.S. Cho, J.W. Lee, and J. Kim, “Concurrent Dual-Band Class-E Power Ampli
er Using Composite Right/Left-Handed Transmission Lines,” IEEE Transactions On
Microwave Theory And Techniques, vol. 55, 2007, pp. 1341-1347.
[17] R.D. Boesch and R.C. Meadows, “Dual-band, Dual-mode Power Amplifier,” US
Patent No.: US 6,298,244 B1, 2001.
[18] F. Ali, E. Lourandakis, R. Gloeckler, K. Abt, G. Fischer, and R. Weigel, “Tunable
Multiband Power Amplifier using Thin-Film BST Varactors for 4G Handheld
Applications,” Radio and Wireless Symposium, New Orleans: 2010, pp. 236-239.
[19] C. Zhang and A.E. Fathy, “A Novel Reconfigurable Power Amplifier Structure for
Multi-Band and Multi-Mode Portable Wireless Applications using a Reconfigurable
Die and a Switchable Output Matching Network,” International Microwave
Symposium Digest, Boston: 2009, pp. 913-916.
[20] E. Lourandakis, M. Schmidt, and R. Weigel, “Tunable BST-Varactor-Based Matching
Networks for Mobile Radio Applications,” International Microwave Symposium
Workshop, Atlanta: 2008.
[21] D. Qiao, R. Mol, S.M. Lardizabal, B. Pillans, P.M. Asbeck, and G. Jerinic, “An
Intelligently Controlled RF Power Ampli er With a Recon gurable MEMS-Varactor
Tuner,” IEEE Transactions On Microwave Theory And Techniques, vol. 53, 2005, pp.
1089-1095.
[22] Y.-jan E. Chen, S. Member, L.-yuan Yang, and W.-chih Yeh, “An Integrated
Wideband Power Amplifier for Cognitive Radio,” IEEE transaction on microwave
Theory and Techniques, vol. 55, 2007, pp. 2053-2058.
[23] C. Xie, “Directional Dual Band Distributed Power Amplifier with Composite
Left/Right-handed Transmission Lines,” IEEE International Microwave Symposium
Digest, Atlanta: 2008, pp. 1135-1138.
[24] J. Mata-contreras, M.-G. T.M., and C. Camachopenalosa, “Experimental Performance
of a Meta-Distributed Amplifier,” 37th European Microwave Conference, Munich:
2007, pp. 743-746.
[25] A. Podell, “Power Amplifier ABC’s,” Besser Association Webinar.
[26] F.H. Raab, S. Member, P. Asbeck, S.C. Cripps, J.F. Sevic, N.O. Sokal, and L. Fellow,
“Power Amplifiers and Transmitters for RF and Microwave,” IEEE Transactions On
Microwave Theory And Techniques, vol. 50, 2002, pp. 814-826.
Biboliography
82
[27] S.C. Cripps, Advanced Techniques in RF Power Amplifier Design, Boston, London:
Artech House, 1999.
[28] S.C. Cripps, RF power amplifiers for wireless communications, Bosten, London:
Artech House, 2006.
[29] F. Sechi and M. Bujatti, Solid-State Microwave High-Power Amplifiers, Bosten,
London: Artech House, 2009.
[30] T. Lee, The design of CMOS radio-frequency integrated circuits, Cambridge
University Press, 1998.
[31] Avago, Development of E-pHEMT Technology White Paper.
[32] Avago, Characteristics of E-pHEMT vs HBTs for PA Applications White Paper.
[33] Juan Melero, eds., GSM, GPRS AND EDGE PERFORMANCE Evolution Towards
3G/UMTS, Wiley, .
[34] J.H. Kim, J.H. Jeong, S.M. Kim, C.S. Park, and K.C. Lee, “Prediction of error vector
magnitude using AM/AM, AM/PM distortion of RF power amplifier for high order
modulation OFDM system,” IEEE MTT-S International Microwave Symposium Digest,
2005., vol. 00, 2005, pp. 2027-2030.
[35] J. Vuolevi and T. Rahkonen, Distortion in RF Power Amplifier, Norwood, MA: Artech
House, 2003.
[36] A. Ahmed, M. Endalkachew, and G. Kompa, “Power Amplifier Linearization Using
Memory Polynomial Predistorters with Non-uniform Delay Taps,” International
Microwave Symposium Digest, Fort Worth: 2004, pp. 1871- 1874.
[37] P. Colantonio, J.A. Garcia, F. Giannini, E. Limiti, E. Malaver, J.C. Pedro, R. Tor, and
V. Politecnico, “High Linearity and Efficiency Microwave PAs,” 12th GAAS
Symposium, Amsterdam: 2004, pp. 183-186.
[38] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design, Prentice Hall, .
[39] K. Krishnamurthy, “Ultra-Broadband, Efficient, Microwave Power Amplifiers in
Gallium Nitride HEMT Technology,” phD Thesis at University of California, Santa
Barbara, 2000.
[40] R. Fano, “Theoretical limitations on the broadband matching of arbitrary impedances,”
Journal of the Franklin Institute, vol. 249, Feb. 1950, pp. 139-154.
[41] H.W. Bode, Network analysis and feedback amplifier design, New York: R. E. Krieger
Pub. Co;, 1945.
[42] A.S.M. Sayed, “Ultra wideband 5W hybrid power amplifier design using silicon
carbide MESFETs,” phD Thesis at Technical University of Berlin, 2005.
Biboliography
83
[43] W.J. Thompson, “Broad Band Impedance Matching Device With Coupled
Transmission Lines,” US Patent 6664935, 2002.
[44] B. Becciolini, “Impedance Matching Networks Applied to RF Power Transistors,”
Motorola Semiconductor Application Note AN721, 1993.
[45] D.S. Peckham, B. Hills, G.R. Black, and V. Hills, “Impedance Matching for a Dual
Band Power Amplifier,” US Patent No.: 6,243,566 B1, 2001.
[46] K.B. Niclas, “Multi-Octave Performance of Single-Ended Microwave Solid-State
Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, vol. 32, 1984.
[47] S. Keller, U. Mishra, M.J.W. Rodwell, and S.I. Long, “Broadband GaAs MESFET and
GaN HEMT resistive feedback power amplifiers,” IEEE Journal of Solid-State
Circuits, vol. 35, 2000, pp. 1285-1292.
[48] G. Zhang, S. Chang, Z. Alon, W. Hillcrest, and N. Park, “high performance Balanced
Power Amplifier and Its Integration into a Front-end Module at PCS Band,” IEEE
Radio Frequency Integrated Circuits Symposium, Hawaii: 2007, pp. 251-254.
[49] G. Zhang and S. Chang, “Power Amplifier Architectures for 3G Handsets: Balanced v.
s. Single-ended Structure,” Radio Frequency Integrated Circuits Symposium Workshop,
Hawaii: .
[50] C.-hsiung Tseng and C.-lin Chang, “Improvement of Return Loss Bandwidth of
Balanced Ampli er Using Metamaterial-Based Quadrature Power Splitters,” IEEE
Microwave and Wireless Components Letters, vol. 18, 2008, pp. 269-271.
[51] Y. Kwon and J.-hyun Kim, “Low-Power PAE Enhancement for 3G Handset Power
Amplifiers,” IEEE International Microwave Symposium Workshop, Boston: 2009.
[52] R.S. Pengelly, “Improving the Linearity and Efficiency of RF Power Amplifiers,”
High Frequency Electronics, 2002.
[53] J.H. Kim and C.S. Park, “MMIC power amplifier adaptively linearized with RF
coupled active bias circuit for W-CDMA mobile terminals applications,” IEEE MTT-S
International Microwave Symposium Digest, 2003, pp. 2209-2212.
[54] T. Yoshimasu, M. Akagi, N. Tanba, and S. Hara, “An HBT MMIC power amplifier
with an integrated diode linearizer for low-voltage portable phone applications,” IEEE
Journal of Solid-State Circuits, vol. 33, 1998, pp. 1290-1296.
[55] S. Reed, Y. Wang, F. Huin, and S. Toutain, “HBT power amplifier with dynamic base
biasing for 3G handset applications,” IEEE Microwave and Wireless Components
Letters, vol. 14, Aug. 2004, pp. 380-382.
[56] C.-hung Kao, C.-W. Chen, C.-M. Lin, Y.-S. Chang, and S.-C. Wong, “Linearized bias
circuit with adaptation,” US Patent No.: 7,358,817 B2, 2008.
Biboliography
84
[57] Y.S. Noh and C.S. Park, “Linearized High Efficient HBT MMIC Dual Band Power
Amplifier Module for L-Band Application,” Asia-Pacific Microwave Conference,
Taipei: 2001.
[58] Y.S. Noh, S. Member, and C.S. Park, “PCS/W-CDMA Dual-Band MMIC Power
Amplifier With a Newly Proposed Linearizing Bias Circuit,” IEEE Journal of Solid-
State Circuits, vol. 37, 2002, pp. 1096-1099.
[59] W. Wang, L. van den Oever, E. Spits, C. Korden, G. Fischer, and R. Weigel, “A novel
dynamic bias circuit for simultaneous improvement of linearity and efficiency for
mobile handset PA,” EEEfCOM, Ulm: 2010.
[60] J.-H. Chen, “Wideband dynamic biasing of power amplifiers for wireless handheld
applications,” phD Thesis at Georgia Institute of Technology, 2006, p. 129.
[61] P.M. Asbeck and L. Larson, with D.Y Lie, “A monolithic high-efficiency 2.4GHz 20-
dBm SiGe BiCMOS envelope-tracking OFDM power amplifier,” IEEE Journal of
Solid-State Circuits, 2006, p. 1271.
[62] D.Y.C. Lie, J.D. Popp, F. Wang, D. Kimball, and L.E. Larson, “Linearization of
Highly-Efficient Monolithic Class E SiGe Power Amplifiers with Envelope-Tracking
(ET) and Envelope-Elimination-and-Restoration (EER) at 900MHz,” IIEEE
Transactions on Circuits and Systems Part I: Regular Papers, vol. 56, Nov. 2009.
[63] B. Kim, J. Choi, D. Kang, and D. Kim, “A multi-mode envelope tracking power
amplifier for software defined radio transmitters,” IEEE International Microwave
Workshop Series on RF Front-ends for Software Defined and Cognitive Radio
Solutions, Aveiro: 2010.
[64] J.S. Hwa, J. Moon-Suk, K.-T. Kang, and K.J. Hyun, “Multiple Output Power Mode
Amplifier,” US Patent No.: 7,554,392 B2, vol. 2009.
[65] J. Kim, D. Lee, S. Jung, and Y. Kwon, “High efficiency power amplifier with multiple
power modes,” US Patent No.: 6,900,692 B2, 2005.
[66] E.T. Spears, J.D. Jorgenson, V.E. Steel, and K.T. Vu, “Portable integrated switching
power amplifier,” US Patent No.: 6,356,150 B1, 2002.
[67] R. Sweeney, “Practical Magic,” IEEE Microwave Magazin, vol. 9, 2008, pp. 73-82.
[68] Y.-sub Lee, M.-woo Lee, and Y.-ha Jeong, “Highly Linear and Efficient Doherty
Amplifier Employing Power Tracking Bias Supply Scheme for WCDMA
Applications,” IEEE Radio and Wireless symposium, Orlando: 2008.
[69] Y.-sub Lee, M.-woo Lee, S.-ho Kam, and Y.-ha Jeong, “Highly Linear and Efficient
Asymmetrical Doherty Power Amplifiers with Adaptively Bias-controlled
Predistortion Drivers,” IEEE International Microwave Symposium, Boston: 2009.
[70] T.R. Apel, “Switched Doherty PAs for 3G,” IEEE International Microwave
Symposium Workshop, Atlanta: 2008.
Biboliography
85
[71] T.R. Apel, “Switched Distributed Power Amplifier,” US Patent No.:2007/0176677 A1,
2007.
[72] B. Sogl, W. Thomann, J.-erik Mueller, W. Bakalski, A.L. Scholtz, and A. Campeon,
“A Multi-mode Power Ampli er for Enhanced PAE in Back-off Operation with Load
Insensitive Architecture,” Radio and Wireless Symposium, San Diego: 2009.
[73] A. Scuderi, C. Santagati, M. Vaiana, and M. Paparo, “31.8 Balanced SiGe PA Module
for Multi-Band and Multi-Mode Cellular-Phone Applications,” International Solid-
State Circuits Conference, San Francisco: 2008.
[74] S.W. Chang and A. Wang, “High efficiency load insensitive power amplifier,” US
Patent No.: 7,486,134 B2, 2009.
[75] Y. Wang, K.I. Pedersen, P.E. Mogensen, and T.B. Sorensen, “Carrier load balancing
methods with bursty traffic for LTE-Advanced systems,” 2009 IEEE 20th
International Symposium on Personal, Indoor and Mobile Radio Communications,
Tokyo: Ieee, 2009.
[76] W. Wang, Z. Zhang, and A. Huang, “Spectrum Aggregation : Overview and
Challenges,” Network Protocols and Algorithms ISSN 1943-3581, vol. 2, 2010, pp.
184-196.
[77] E. Seidel, “Initial thoughts on LTE Advanced for 3GPP Release 10,” LTE World
Summit, Berlin: 2009.
[78] J. Sachs, “Flexible Spectrum Usage - How LTE can meet Future Capacity Demands,”
33. Treffen der VDE/ITG-Fachgruppe 5.2.4, Stuttgart: .
[79] Y. Ayasli, R. L. Mozzi, J. L. Vorhaus, L. D. Reynolds, and R. A. Pucel, “A monolithic
GaAs 1-13 GHz traveling-wave amplifier,” IEEE transactions on Microwave Theory
and Techniques , vol. 30, 1982, pp. 976-981 .
[80] K.B. Niclas and R. Pereira, “On Theory and Performance of Solid-State Microwave
Distributed Amplifiers,” IEEE transaction on microwave theory and techniques, vol.
31, 1983, pp. 447-456.
[81] S.N. Prasad, E. Nordman, K. Hohenwarter, and C. Becker, “MESFET Distributed
Amplifier Design Guidelines,” IEEE Transactions on Microwave Theory And
Techniques, vol. M, 1984, pp. 268-275.
[82] P.H. Ladbrooke, “Large-Signal Criteria for the Design of GaAs FET Distributed
Power Amplifiers,” IEEE Transactions on Electron Devices, 1985, pp. 1745-1748.
[83] J.B. Cole, “Design technique for high power, high efficiency, broadband distributed
amplifiers,” IET Electronics Letters, 1989, pp. 941-944.
[84] K.B. Niclas, R.R. Pereira, and A.P. Chang, “On Power Distribution Additive
Amplifiers,” IEEE Transactions On Microwave Theory And Techniques, 1990, pp.
1692-1700.
Biboliography
86
[85] C. Paoloni, “Design of High Performance Power Distributed Amplifier Using Lange
Couplers,” International Microwave Symposium Digest, 1994, pp. 281-284.
[86] E.L. Ginztont, S. Member, W.R. Hewlettt, J.H. Jasbergt, and J.D. Noett, “Distributed
Amplification *,” Institute of Radio Engineers, 1948, pp. 956-969.
[87] A. Anakabe, J.-M. Collantes, J. Portilla, J. Jugo, A. Mallet, L. Lapierre, and J.-P.
Fraysse, “Analysis and elimination of parametric oscillations in monolithic power
amplifiers,” IEEE International Microwave Symposium, Seattle: Ieee, 2002, pp. 2181-
2184.
[88] K. Narendra, J.M. Collantes, C. Paoloni, and E. Limiti, “Parametric oscillations in
distributed power amplifiers,” IET Electronics Letters, vol. 45, 2009, p. 1325.
[89] J. Jugo, J. Portilla, A. Anakabe, A. Suarez, and J.M. Collantes, “Closed-loop stability
analysis of microwave amplifiers,” IET Electronics Letters, vol. 37, 1996, pp. 226-228.
[90] a Suarez and D.B. Rutledge, “Bifurcation analysis of stabilization circuits in an L-
band LDMOS 60-W power amplifier,” IEEE Microwave and Wireless Components
Letters, vol. 15, Oct. 2005, pp. 712-714.
[91] H. Liu and W. Wang, “Stability analysis of microwave amplifiers in TWA,”
Mechantronics (ISSN: 1007-080x), vol. 16, 2010, pp. 34-37.
[92] W. Wang, G. Fischer, L. van den Oever, C. Korden, and R. Weigel, “Distributed
Amplifier with Multiple Power Modes for Linear Mobile Phone Application,” German
Microwave Conference, Darmstadt: 2011.
[93] A. Sanada, C. Caloz, and T. Itoh, “Characteristics of the Composite Right/Left-Handed
Transmission Lines,” IEEE Microwave and Wireless Components Letters, vol. 14,
2004, pp. 68-70.
[94] I.-hsiang Lin, M.D. Vincentis, C. Caloz, and T. Itoh, “Arbitrary Dual-Band
Components Using Composite Right/Left-Handed Transmission Lines,” IEEE
Transactions On Microwave Theory And Techniques, vol. 52, 2004, pp. 1142-1149.
[95] M. Durán-sindreu, F. Aznar, A. Vélez, J. Bonache, and F. Martín, “New Composite
Right/Left Handed Transmission Lines based on Electrically Small Open Resonators,”
IEEE International Microwave Symposium Digest, 2009, pp. 45-48.
[96] Y. Horii, “A Super-Compact Balanced Multi-Layered CRLH Transmission Line With
Wideband LH Properties For Microwave Phase Engineerings,” IEEE International
Microwave Symposium, Boston: 2009.
[97] Z. Yu, H. Li, and H. Sai-ling, “A tunable dual-broad-band branch-line coupler utilizing
composite right/left-handed transmission lines,” Journal of Zhejiang University
SCIENCE (ISSN 1009-3095), 2005, pp. 483-486.
Biboliography
87
[98] A. Dupuy, K.M.K.H. Leong, and T. Itoh, “Class-F Power Amplifier Using a Multi-
Frequency Composite Right/Left-Handed Transmission Line Harmonic Tuner,”
International Microwave Symposium Digest, vol. 00, 2005, pp. 0-3.
[99] T. Wong, Fundamentals of Distributed Amplification, Artech House, 1993.
[100] W. Mueller, “UMTS Multiband Architectures:,” International Wireless Industry
Consortium Workshop on Multi-band, Multi-mode Handsets, San Francisco: 2008.
[101] W. Wang, G. Fischer, L. van den Oever, C. Korden, and R. Weigel, “Linear Tapered
Diplexing Distributed Power Amplifier for Mobile Phone Application,” IEEE
International Microwave Symposium, Baltimore: 2011.
[102] W. Wang and G. Fischer, “A Triplexing amplifier based on CRLH structures
incorporating active elements,” German Microwave Conference, Munich: 2009.
[103] P.M. Jupp, R.M.R. Ltd, H. So, E. Engineering, T. Place, and L. Wc, “Application of
Derivative Superposition to low IM3 Distortion IF Amplifiers,” Electrical Engineering,
2002.
Author’s publications
88
Author’s publications
2011 W. Wang, G. Fischer, L. van den Oever, C. Korden, R. Weigel.
“Linear Tapered Diplexing Distributed Power Amplifier for
Mobile Phone Application,” IEEE International Microwave
Symposium, Baltimore: 2011.
2011 W. Wang, G. Fischer, L. van den Oever, C. Korden, R. Weigel.
„Distributed Amplifier with Multiple Power Modes for Linear
Mobile Phone Application,” German Microwave Conference,
Darmstadt: 2011.
2010. H. Liu, W. Wang. “Stability analysis of microwave amplifiers
in TWA,” Mechatronics (ISSN: 1007-080x):2010.
2010. W. Wang, L. Van den Oever, E. Spits, C. Korden, G. Fischer, R.
Weigel. “A novel dynamic bias circuit for simultaneous
improvement of linearity and efficiency for mobile handset PA,”
Gerotron EEEfCOM, Ulm: 2010.
2009. W. Wang, G. Fischer. “A Triplexing amplifier based on CRLH
structures incorporating active elements,” German Microwave
Conference, Munich:2009.
2006. A. Poloczek, W. Wang, J. Driesen, I. Regolin, W. Prost. F.J.
Tegude. “Concept and Development of a New MOBILE-Gate
with All Optical Input,” German Microwave Conference,
Karlsruhe: 2006.