digital design: principles and practices

Digital Design:Principles and Practices

Chapter 6Combinational Logic Design Practices

Introduction

• If you are contemplating a career in digital design, it is recommended that you study the examples at least for Verilog or VHDL.

• A practical combinational circuit may have dozens of inputs and outputs and could require millions of terms to describe as an SOP expression, and billions of rows to describe in a truth table.

• A complex circuit or system is conceived as a collection of smaller subsystems, each of which has a much simpler description.

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Introduction (cont’d)

• Basic combinational building blocks discussed in this chapter: Decoders Encoders Three-State Devices Multiplexers (MUX) XORs Comparators Adders & Subtractors Multipliers

3

6.4 Decoders(including 6.4.1 – 6.4.4)

Decoder

• A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different.

• The input code generally has fewer bits than the output code, and there is a one-to-one mapping from input code words into output code words.

• In a one-to-one mapping, each input code word produces a different output code word.

• The most common decoder circuit is an n-to-2n decoder or binary decoder.

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A 2-to-4 (Binary) Decoder

6

Table 6-4

Figure 6-32

A 2-to-4 (Binary) Decoder – Verilog Structural-style Verilog Module

7

Table V6-20 Structural-style Verilog module for the decoder in Figure 6-32.

Decoder Circuit Structure

8

A 3-to-8 Binary Decoder for Gray Code

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A Mechanical Encoding DiskUsing a 3-bit Gray Code

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A 3-to-8 Binary Decoder for Gray Code

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Decoder• Truth table for a 4-bit (4-to-16) Decoder with Active-LOW outputs

LogicLogicDiagramDiagram

Decoder

• 4-bit decoder

Binary inputs

Active-low outputs

TruthTruthTableTable

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BCD-to-Decimal Decoder

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LogicLogicDiagramDiagram

BCD-to-7-Segment Decoder

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TruthTruthTableTable

BCD-to-7-Segment Decoder

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7-Segment Display

LED (Light –Emitting Diode)17

74x138 – Logic Symbol• 3-to-8 decoder• All of the output pins are active low.

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74x138 – Truth Table

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74x138 - Logic Diagram

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74x138 – Different Logic Symbols

21

Casc

adin

g Bi

nary

Dec

oder

5-to

-32

Dec

oder

Usi

ng 7

4x13

8s

22

74x138-like 3-to-8 Binary DecoderBehavior-Style Verilog Module

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74x138 – Logic Symbol• 3-to-8 decoder• All of the output pins are active low.

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6.5 Encoders(including 6.5.1 & 6.5.2)

Encoder

• An encoder is a combinational logic circuit that essentially performs a “reverse” decoder function.

• An encoder’s input code normally has more bits than its output code, whereas a decoder’s output code normally has more bits than its input code.

• Probably the simplest encoder to build is a 2n-to-n encoder or binary encoder.

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8-to-3 (Binary) Encoder

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Y0 = I1 + I3 + I5 + I7Y1 = I2 + I3 + I6 + I7Y2 = I4 + I5 + I6 + I7

8-to-3 (Binary) Encoder- Truth Table

I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

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A Request Encoder

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Priority Encoder

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• Input I7 has the highest priority.• The IDLE output is asserted if no

inputs are asserted.

Decimal-to-BCD Encoder

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• A3 = 8 + 9• A2 = 4 + 5 + 6 + 7• A1 = 2 + 3 + 6 + 7• A0 = 1 + 3 + 5 + 7 + 9 32


Basic logic diagram of a decimal-to-BCD encoder

• A3 = 8 + 9• A2 = 4 + 5 + 6 + 7• A1 = 2 + 3 + 6 + 7• A0 = 1 + 3 + 5 + 7 + 9

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8-to-3 Encoder

74x148 – Logic Symbol

• 8-input priority encoder• All inputs and outputs are active low.

• EI_L : enable input• GS_L : group select (got something)• EO_L : enable output (used for

cascading). EO_L is asserted if EI_L is asserted but no request input is asserted.

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74x148 – Truth Table

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74x148-like 8-input Priority Encoder Behavior-Style Verilog Module

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6.6 Three-State Devices(including 6.6.1)

Three-State Devices

• Three states: 0, 1, or Hi-Z Hi-Z: High Impedance

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Tristate Inverter

Implementation of an Tristate Inverter

40

Eight Sources Sharing a Three-State Party Line

41

74x541: Octal Three-State Buffer

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74x541-like Three-State Device Behavior-Style Verilog Module

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6.7 Multiplexers(including 6.7.1)

Multiplexer (MUX)

• A multiplexer is a digital switch – it connects data from one of n sources to its output.

• Figure 6-57(a) n sources of data each source is b bits wide b output bits usually, 2s = n enable signal (EN)

• A Multiplexer is often calleda MUX for short.

45Figure 6-57 (a)

Multiplexer (MUX)

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75x151: 8-input 1-bit MUX

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48


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74x157 2-input 4-bit MUX

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4-input 8-bit MUXDataflow-Style Verilog Module

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4-input 8-bit MUXBehavioral-Style Verilog Module

52

6.8 Exclusive-OR Gates andParity Circuits

(including 6.8.1, 6.8.2, and 6.8.3)

XOR

• An Exclusive-OR (XOR) gate is a 2-input gate whose output is 1 if exactly one of its inputs is 1.

• Stated another way, an XOR gate produces a 1 output if its inputs are different.

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XNOR

• An Exclusive NOR (XNOR) or Equivalence gate is just the opposite to the XOR – it produces a 1 output if its inputs are the same.

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XOR

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XOR and XNOR

• Any two signals (inputs or output) of an XOR or XNOR gate may be complemented without changing the resulting logic function.

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Error Detection & Correction Codes

• The Parity Method For error detection

• The Hamming Code For error detection and correction

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The Parity Method• An even parity bit makes the total number of 1s even.• An odd parity bit makes the total number of 1s odd.

P: the parity bit

59

The Parity Method- Detecting an Error

• A parity bit provides for the detection of a single bit error (or any odd number of errors, which is very unlikely) but cannot check for two errors in one group.

• For instance, let’s assume that we wish to transmit the BCD code 0101. The total code transmitted, including the parity bit, is

0 0 1 0 1↑ BCD Parity bit

0 0 0 0 1↑

Bit error

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Parity Circuits

• Odd-parity circuit Its output is 1 if an odd number of its inputs are 1.

• Even-parity circuit Its output is 1 if an even number of its inputs are 1.

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Parity Circuits

62

74x280: 9-bit Parity Generator• 74x280 can be used to

indicate whether an even or odd number of inputs are 1.

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3-input XOR DeviceDataflow-Style Verilog Module

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9-Input Parity CheckerBehavioral-Style Verilog Module

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6.9 Comparators(including 6.9.1)

Comparator• A circuit that compares two binary words and indicates

whether they are equal is called a comparator.

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Comparator

• Comparators can also be built using Exclusive-NOR (XNOR) gates, sometimes called Equivalence gates.

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OR Functions

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4 levels of gate delay at the transistor levelLarger circuit

2 levels of gate delay at the transistor levelSmaller circuit

6.10 Adders, Subtractors, and ALUs (including 6.10.1, 6.10.2, and 6.10.6)

Basic Adders

• Half Adder• Full Adder

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Half Adder

0 + 0 = 00 + 0 = 0

0 + 1 = 10 + 1 = 1

1 + 0 = 11 + 0 = 1

1 + 1 = 101 + 1 = 10

Zero plus zero equals zeroZero plus zero equals zero

Zero plus one equals oneZero plus one equals one

One plus zero equals oneOne plus zero equals one

One plus one equals zero with a carry of oneOne plus one equals zero with a carry of one

Simple Binary Addition

• The half-adder accepts two binary digits on its inputs and produces two binary digits on its output, a sum bit and a carry bit.

Half Adder

Binary Addition and Subtraction

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Full Adder

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Full Adder

4-Bit Ripple (Carry) Adder

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4-Bit Ripple (Carry) Adder

8-Bit (Signed and Unsigned) AdderVerilog Module

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ALU – 74x382

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What We Have Learned

• Decoders• Encoders• Three-State Devices• Multiplexers (MUX)• XOR and Parity Circuits• Comparators• Adders• ALUs

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Universal Gates

• NAND Gate• NOR Gate

Universal Gates - NAND

• One NAND Gate as an Inverter


• Two NAND Gates as an AND Gate


• Three NAND Gates as an OR Gate


• Four NAND Gates as a NOR Gate

Universal Gates - NOR

• One NOR Gate as an Inverter


• Two NOR Gates as an OR Gate


• Three NOR Gates as an AND Gate


• Four NOR Gates as a NAND Gate

digital design: principles and practices

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