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ECE 274 - Digital LogicLecture 8

Lecture 8Parallel Load RegisterShift RegistersMultifunction Registers

Multifunction Register Design Process

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Digital DesignDatapath Components: Processor: Controller + Datapath

Data Inputs

Data Outputs

Control Outputs

Control Inputs

Controller Datapath

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Digital DesignDatapath Components: Registers

Additional Desired Functionality:Ability to choose between previous and new valueLoad all bits at the same time

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Digital DesignDatapath Components: Parallel Load Register

4-bit Parallel Load RegisterAbility to choose between previous and new valueLoad all bits at the same time

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Digital DesignDatapath Components: Parallel Load Register Example

Basic parallel load register example.

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Digital DesignDatapath Components: Parallel Load Register Example

Basic register example: (a) timing diagram, and (b) the contents of each register.

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Digital DesignDatapath Components: Design Example: Weight Sampler

Weight Sampler:Functional Description:

Display Weight of objects placed on scaleDisplay “Present weight”Display “Saved weight” stored upon Save button being pressed

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Digital DesignDatapath Components: Design Example: Weight Sampler

Weight sampler implemented using a 4-bit parallel load register.

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Digital DesignSequential Logic Design – Controllers: Design ExampleCircuit Description: Temperature History StorageFunctional Description:

Design a system that records the outside temperature every hoursand displays the last three recorded temperatures.

Inputs:c: clock signalx4..0: 5-bit temperature reading

Outputs:a4..0, b4..0, c4..0: 5-bit temperature readings to be displayed

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Digital DesignDatapath Components

Internal design of the TemperatureHistoryStorage component, using parallel load registers.

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Digital DesignDatapath Components: Design Example: Above Mirror Display

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User Input

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Digital DesignDatapath Components: Electronic Checkerboard

CircuitCircuit

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An electronic checkerboard: Eight 8-bit registers (R7 through R0) can be used to drive the 64 LEDs, using one register per column, and detail of how one

register connects to a column’s LEDs.16


Timing diagram indicating an input sequence that can be used to initialize

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Checkerboard after loading registers for initial checker positions.

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Digital DesignDatapath Components: Computer Components: Shift Registers

Shift Register: Register that can move contents left/right

Right shift example: (a) sample contents before and after a right shift, and (b) bit-by-bit view of the shift.

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Digital DesignDatapath Components: Computer Components: Shift Registers

Shift register: (a) implementation, (b) paths when shr=1, and (c) block symbol.

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Digital DesignDatapath Components: Computer Components: Rotator

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Digital DesignDatapath Components: Not really a quiz, but it is a CHALLENGE!!

Design a 4-bit shift register with a shift-in input that will allow you to shift left by 0-3 positions on one clock cycle.

Clearly indicate the following:InputsOutputsImplementation

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If you implement this diagram using shift registers, by how many input wires will we need? A) 1 B) 6 C) 8

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Digital DesignDatapath Components: Computer Components: Multifunction Registers

Operation Table

4-bit register with multiple operations:parallel loadshift right

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4-bit register with multiple operations:Parallel loadShift rightShift left

Operation table of a 4-bit register with parallel load, shift left, and shift right operations.

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Operation table of a 4-bit register with separate control inputs for parallel load, shift left, and shift right.

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A small combinational circuit maps the control inputs ld, shr, and shl to the muxselect inputs s1 and s0.

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Truth tables describing operations of a register with left/right shift and parallel load along with the mapping of the register control inputs to the internal 4x1 mux select lines: (a)

complete operation table defining the mapping of ld, shr, and shl to s1 and s0, and (b) a compact version of the operation table.

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Four-step process for designing a multifunction register.

Create a truth table that maps external control lines to the internal mux select lines, with appropriate priorities, and then design the logic to achieve that mapping

Map control lines

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For each operation, connect the corresponding mux data input to the appropriate external input or flip-flop output (possibly passing through some logic) to achieve the desired operation.

Connect muxinputs

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Create an operation table defining the desired operation for each possible value of the mux select lines.

Create muxoperation table

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Count the number of operations (don’t forget the maintain present value operation!) and add in front of each flip-flop a mux with at least that number of inputs.

Determine muxsize

1.

DescriptionStep

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Digital DesignDatapath Components: Using Multifunction Register Design Process

Functional Requirements:Register with the following operations

LoadShift leftSynchronous clearSynchronous set

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Digital DesignDatapath Components: Using Multifunction Design Process

Step 1: Determine Mux SizeRegister with the following operations

LoadShift leftSynchronous clearSynchronous setDon’t forget Hold Present Value

Need a mux with at least 5 inputs: 8x1 mux

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Step 2: Create Mux Operation TableAssign operations to mux inputs

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Step 3: Connect Mux Inputs

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Step 4: Map Control Lines

s2 = clr’*sets1 = clr + clr’*set’*ld’*shls0 = clr + clr’*set’*ld

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Step 4: Map Control Lines

clr’*set=>clr + clr’*set’*ld’*shl=>

clr + clr’*set’*ld=>

clr, set, ld, shl

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