digital design 2e copyright © 2010 frank vahid 1 how to capture desired behavior as fsm list states...

Digital Design 2eCopyright © 2010 Frank Vahid

1

How To Capture Desired Behavior as FSM

• List states– Give meaningful names, show initial state– Optionally add some transitions if they help

• Create transitions– For each state, define all possible transitions leaving that state.

• Refine the FSM– Execute the FSM mentally and make any needed improvements.


2

FSM Capture Example: Code Detector• Unlock door (u=1) only

when buttons pressed in sequence: – start, then red, blue,

green, red

• Input from each button: s, r, g, b– Also, a indicates that

some colored button pressed

• Capture as FSM– List states

• Some transitions included

Start

RedGreen

Blue

s

rg

ba

Doorlock

u

Codedetector

a

ab ag arRed1

u=0

Blue

u=0

Green

u=0

Red2

u=1

Inputs: s,r,g,b,aOutputs: u

Wait

s'u=0 s

Wait for start button

ar

Start

u=0

Wait for first colored b uttona

1


3

FSM Capture Example: Code Detector• Capture as FSM

– List states– Create transitions

Start

RedGreen

Blue

s

rg

ba

Doorlock

u

Codedetectora

Wait

Start

Red1 Red2GreenBlue

s'

a'

ar'

ab ag ar

u=0

u=0 ar

u=0 s

u=0 u=0 u=1


a


4

FSM Capture Example: Code Detector• Capture as FSM

– List states– Create transitions

• Repeat for remaining states

– Refine FSM• Mentally execute• Works for normal

sequence• Check unusual cases• All colored buttons

pressed– Door opens!– Change conditions:

other buttons NOT pressed also

Start

RedGreen

Blue

s

rg

ba

Doorlock

u

Codedetectora

Wait

Start

Red1 Red2GreenBlue

s'

a'

ar' ab' ag' ar'

a'

ab ag ar

a' a'u=0

u=0 ar

u=0 s

u=0 u=0 u=1



5

FSM Capture Example: Code DetectorStart

RedGreen

Blue

s

rg

ba

Doorlock

u

Codedetectora

Wait

Start

Red1 Red2GreenBlue

s'

a' a(rb

'g')'

a(br

'g')'

a'

abr'g' agr'b' arb'g'

a' a'u=0

u=0arb'g'

u=0 s

u=0 u=0 u=1


a(gr

'b')'

a(rb

'g')'


6

Controller Design• Converting FSM to sequential circuit

– Circuit called controller

– Standard controller architecture• State register stores encoding of

current state• Combinational logic computes outputs

and next state from inputs and current state

• Rising clock edge takes controller to next state

3.4

Combinationallogic

Sm

m

N

OI

clk

FSMinputs

FSMoutputs

m-bitstate register

Controller

General form

a


7

Controller Design ProcessStep Description

Step 1:Capturebehavior

Capture the FSM

Create an FSM that describes the desired behavior of the controller.

2A: Set uparchitecture

Use state register of appropriate width and combinational logic. The logic’s inputs are the state register bits and the FSM inputs; outputs are next state bits and the FSM outputs.

2B: Encodethe states

Assign unique binary number (encoding) to each state. Usually use fewest bits, assign encoding to each state by counting up in binary.Step 2:

Convertto circuit 2C: Fill in

the truth table

Translate FSM to truth table for combinational logic such that the logic will generate the outputs and next state signals for the given FSM. Ordering the inputs with state bits first makes the correspondence between the table and the FSM clear.

2D: Implement combinational logic

Implement the combinational logic using any method.


8

Controller Example: Button Press Synchronizer

• Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button was actually pressed

cycle1 cycle2 cycle3 cycle4clk

Inputs:

Outputs:

bi

bo

Button press synchronizer

controller

bi bo


9

Controller Example: Button Press Synchronizer (cont)

A

B

C

s100001111

s000110011

bi01010101

Inputs

n100010100

n001000000

bo00110000

OutputsCombinational logic

unused

Step 2C: Fill in truth table

a

Step 1: Capture FSM

A B C

bo=1bo=0 bo=0bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

Step 2B: Encode states

00 01 10

bo=1bo=0 bo=0bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

Step 2D: Implement combinational logic

clkState register

bo

bi

s1 s0

n1

n0

Combinational logic

n1 = s1’s0bi + s1s0bin0 = s1’s0’bibo = s1’s0bi’ + s1’s0bi = s1s0

Step 2A: Set up architectureCombinational

logic

n0s1 s0

n1

bobi

clk State register

FSM

inpu

ts

FSM

ou

tputs


10

Common Mistakes when Capturing FSMs

• Non-exclusive transitions

a

bab=11 –

next state?

a

a’b

a

what ifab=00?

a

a’b

a’b’

a’b

a

• Incomplete transitions


11

Verifying Correct Transition Properties• Can verify using Boolean algebra

– Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0 proves pair can never simultaneously be true

– One condition true: OR of all conditions of transitions leaving a state) should equal 1 proves at least one condition must be true

– Examplea

a’b

a + a’b= a*(1+b) + a’b= a + ab + a’b= a + (a+a’)b= a + bFails! Might not be 1 (i.e., a=0, b=0)

a

a * a’b= (a * a’) * b= 0 * b= 0OK!

Answer:


12

Verifying transition properties• Recall code detector FSM

– We “fixed” a problem with the transition conditions

– Do the transitions obey the two required transition properties?

• Consider transitions of state Start, and the “only one true” property

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0s

u=0 u=0 u=1

a

ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) = (a*a’)r = (a’*a)*(r’+b+g) = (a*a)*r*(r’+b+g) = 0*r = 0*(r’+b+g) = a*r*(r’+b+g) = 0 = 0 = arr’+arb+arg

= 0 + arb+arg = arb + arg

= ar(b+g)

Fails! Means that two of Start’s transitions could be true

a

A: ar should be arb’g’(likewise for ab, ag, ar)


13

Introduction– Capture Comb. behavior: Equations, truth tables

– Convert to circuit: AND + OR + NOT Comb. Logic

– Capture sequential behavior: FSMs

– Convert to circuit: Register + Comb. logic Controller

– Datapath components, simple datapaths

– Capture behavior: High-level state machine

– Convert to circuit: Controller + Datapath Processor

– Known as “RTL” (register-transfer level) design

Note: Slides with animation are denoted with a small red "a" near the animated items

Transistor level

Logic level

Register-transfer

level (RTL)

Levels of digital design abstraction

Hig

her

leve

ls

Processors:• Programmable

(microprocessor)• Custom

5.1


14

High-Level State Machines (HLSMs)• Some behaviors too complex for

equations, truth tables, or FSMs• Ex: Soda dispenser

– c: bit input, 1 when coin deposited– a: 8-bit input having value of

deposited coin– s: 8-bit input having cost of a soda– d: bit output, processor sets to 1

when total value of deposited coins equals or exceeds cost of a soda

• FSM can’t represent…– 8-bit input/output– Storage of current total– Addition (e.g., 25 + 10)

as

cd

Sodadispenserprocessor

25

1 025

1

1

500

0

0

0

tot: 25tot: 50

a

as

cd

Sodadispenserprocessor

5.2


15

HLSMs• High-level state machine

(HLSM) extends FSM with:– Multi-bit input/output– Local storage– Arithmetic operations

Inputs: c (bit),a (8 bits), s (8 bits)Outputs: d (bit) // '1' dispenses sodaLocal storage: tot (8 bits)

Wait

Disp

Init

d:='0'tot:=0 c’*(tot<s)’

c'(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

8 8

as

c

dSoda

dispenserprocessor

• Conventions– Numbers:

• Single-bit: '0' (single quotes)• Integer: 0 (no quotes)• Multi-bit: “0000” (double quotes)

– == for equal, := for assignment

– Multi-bit outputs must be registered via local storage

– // precedes a comment

a

Add


16

Ex: Cycles-High Counter• P = total number (in binary) of cycles that m is 1• Capture behavior as HLSM

– Preg required (multibit outputs must be registered)• Use to hold count P

mCountHigh

clk

32

S_Clr

S_Wtm'

S_Incm

mm'

Preg := 0

Preg := Preg + 1

// Clear Preg to 0s

// Wait for m == '1'

// Increment Preg

CountHigh Inputs: m (bit)Outputs: P (32 bits)Local storage: Preg

(c)

S_Clr

Preg := 0// Clear Preg to 0s


(a)

?

S_Clr

S_Wtm'

m

Preg := 0// Clear Preg to 0s

// Wait for m == '1'


(b)?

a

Note: Could have designed directly using an up-counter. But, that methodology is ad hoc, and won't work for more complex examples, like the next one. a

Preg


17

Example: Laser-Based Distance Measurer

• Laser-based distance measurement – pulse laser, measure time T to sense reflection– Laser light travels at speed of light, 3*108 m/sec

– Distance is thus D = (T sec * 3*108 m/sec) / 2

Object ofinterest

D

2D = T sec * 3*108 m/sec

sensor

laser

T (in seconds)

a


18


• Inputs/outputs– B: bit input, from button, to begin measurement– L: bit output, activates laser– S: bit input, senses laser reflection– D: 16-bit output, to display computed distance

sensor

laser

T (in seconds)

Laser-baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor


19


• Declare inputs, outputs, and local storage– Dreg required for multi-bit output

• Create initial state, name it S0– Initialize laser to off (L:='0')– Initialize displayed distance to 0 (Dreg:=0)

Laser-based

distancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

a

Inputs: B (bit), S (bit)Outputs: L (bit), D (16 bits)Local storage: Dreg(16)

S0 ?

L := '0' // laser offDreg := 0 // distance is 0

DistanceMeasurer

(required)

(first state usually initializes the system)

Recall: '0' means single bit, 0 means integer


20


• Add another state, S1, that waits for a button press– B' – stay in S1, keep waiting– B – go to a new state S2

Q: What should S2 do? A: Turn on the lasera

Laser-based

distancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

S0

L := '0'Dreg := 0

S1 ?

B' // button not pressed

B// buttonpressed

S0

DistanceMeasurer ...


21


• Add a state S2 that turns on the laser (L:='1')• Then turn off laser (L:='0') in a state S3

Q: What do next? A: Start timer, wait to sense reflectiona

Laser-based

distancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

DistanceMeasurer ...

S0 S1

L := '0'Dreg := 0

S2

L := '1'// laser on

S3

L := '0'// laser off

B'

B


22


• Stay in S3 until sense reflection (S)• To measure time, count cycles while in S3

– To count, declare local storage Dctr– Initialize Dctr to 0 in S1. In S2 would have been O.K. too.

• Don't forget to initialize local storage—common mistake

– Increment Dctr each cycle in S3

Laser-baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

a

S0 S1 S2 S3

L := '0'Dreg := 0

L := '1' L := '0'Dctr := Dctr + 1// count cycles

Dctr := 0// reset cycle

count

B' S' // no reflection

B

S // reflection?

Inputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)Local storage: Dreg, Dctr (16 bits)

DistanceMeasurer


23


• Once reflection detected (S), go to new state S4– Calculate distance

– Assuming clock frequency is 3x108, Dctr holds number of meters, so Dreg:=Dctr/2

• After S4, go back to S1 to wait for button again

a

S0 S1 S2 S3

L := '0'Dreg := 0

L := '1' L := '0'Dctr := Dctr+1

Dreg := Dctr/2// calculate D

Dctr := 0

B' S'

B SS4

Inputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)DistanceMeasurerLocal storage: Dreg, Dctr (16 bits)

Laser-based

distancemeasurer

16

from button

to displayS

L

D

Bto laser

from sensor


24

RTL Design Process• Capture behavior• Convert to circuit

– Need target architecture– Datapath capable of HLSM's

data operations– Controller to control datapath

5.3

External dataoutputs

Externalcontrol inputs

Controller

...

Externalcontrol

outputs

...Datapath

...

DPcontrolinputs

DPcontroloutputs

...

...

...

External datainputs


25

Ctrl/DP Example for Earlier Cycles-High Counter

(a)

First clear Preg to 0s

Then increment Preg for eachclock cycle that m is 1

P

Pregm

CountHigh

(b)

S_Clr

S_Wtm'

S_Incm

mm'

Preg := 0

Preg := Preg + 1

//Clear Preg to 0s

//Wait for m=='1'

//Increment Preg

CountHigh Inputs: m (bit)Outputs: P (32 bits)LocStr: Preg (32 bits)

PregQ

Ildclr

A B

Sadd1

P

000...00001

?Preg_clr

Preg_ld

m

DP

CountHigh

(c)

32

32

S_Clr

S_Wtm'

S_Incm

mm'

Preg_clr = 1Preg_ld = 0



(d)

//Preg := 0

//Wait for m=1

//Preg:=Preg+1

Controller

CountHigh

P

PregQ

Ildclr

A B

Sadd1

000...00001

Preg_clr

Preg_ld

DP

m

32

32

We created this HLSM earlier

Create DP

Connect with controller

Derive controller

a

a

a


26

RTL Design Process


27

Example: Soda Dispenser from Earlier• Quick overview example.

More details of each step to come.


Wait

Disp

Init

d:='0'tot:=0 c’*(tot<s)’

c'(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Step 1

Step 2A

8

8

8

s

8

a

Datapath

tot_ldtot_clr

tot_lt_s

ldclr

tot

8-bit<

8-bitadder

tot_lt_s

tot_clr

tot_ld

Controller Datapath

s

c

d

a8 8

Step 2B

a

a

Add


28

Example: Soda Dispenser• More details of each step to come.


Wait

Disp

Init

d:='0'tot:=0 c’*(tot<s)’

c'(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Step 1

tot_lt_s

tot_clr

tot_ld

Controller Datapath

s

c

d

a8 8

Step 2B

Step 2C

Inputs: c, tot_lt_s (bit)Outputs: d, tot_ld, tot_clr (bit)

Wait

Disp

Init

d=0tot_clr=1 c'*tot_lt_s’

ctot_lt_s

d=1

c

tot_ld=1

c

d

tot_ld

tot_clr

tot_lt_s

Controller

Add

Add


29

Example: Soda Dispenser• Quick overview example.

More details of each step to come.

Step 2C

Inputs: c, tot_lt_s (bit)Outputs: d, tot_ld, tot_clr (bit)

Wait

Disp

Init

d=0tot_clr=1

ctot_lt_s’ctot_lt_s

d=1

c

tot_ld=1

c

d

tot_ld

tot_clr

tot_lt_s

Controller

Add

d

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

1

1

1

1

0

0

0

0

0

0

n0

1

1

1

1

1

1

0

0

1

0

n1

0

0

0

0

1

0

1

1

0

0

0

1

0

1

0

1

0

1

0

0

c

0

0

1

1

0

0

1

1

0

0

s1

0

0

0

0

0

0

0

0

1

1

s0

0

0

0

0

1

1

1

1

0

1

tot_

lt_s

tot_

ld

tot_

clr

Init

Wa

itA

dd

Dis

p

Use controller design process to complete the design

a

digital design 2e copyright © 2010 frank vahid 1 how to capture desired behavior as fsm list states...

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