digital circuits & fundamentals of microprocessor

Nagpur Institute of Technology, Nagpur

Department of Computer Science & Engineering Question Bank with Solutions

Digital Circuits & Fundamentals of Micro Processor

(III Sem-CSE) Compiled By

Ms. Shital Tiwaskar Email: [email protected]

Question Bank : DCFM III Sem CSE


Q.1) Perform the following conversions.

I] (110101.011) binary = (?) decimal Solutions: = 4321012345 21212120212021202121 −−−− ×+×+×+×+×+×+×+×+×+× Ans: ( )decimal4375.53

a] ( ) ( )DO ?7

2273.155.2

=⎟⎟⎠

⎞⎜⎜⎝

⎛×

Solutions: (15.73) octal = 2101 83878581 −− ×+×+×+×

= (13.92136) decimal

(22) octal = 01 8282 ×+× = (18) decimal

(7) octal = 087 × = (7) decimal

(2.5)octal = ( )10 8582 −×+× =(2.653)decimal

Ans: decimal

⎟⎟⎠

⎞⎜⎜⎝

⎛×

653.2

71892136.13

b] ( )( ) DHDCA (?)2110 =÷

Solutions: (110)H = ( )012 160161161 ×+×+×

= (272) decimal (2A) H = ( )01 16162 ×+× A

= (42)D (DC)H = ( )01 1616 ×+× CD

= (220)D Ans: ( ) ( )[ ]decimal

22042272 ×



IV] (243.62) D = (?) octal Solutions:

Ans: ( )O4753.363

c] ( ) ( )H?25.9310 10=

Solutions:

Decimal no × Base (8) = Quotient

result

0.25 × 16 = 4.0 Ans: ( )HE 4.245

VI] ( ) ( )HO ?45.273 =

Solutions: ( ) ( ) ( )HBO ==

(273.45) = (0 10 11 1011 . 1001 01)

Ans: ( )HBB 94.0

d] (10110111) gray = (?)B

Solutions:

Decimal no ÷ Base (8) = Quotient Remainder

243 ÷ 8 = 30 3 30 ÷ 8 = 3 6 3 ÷ 8 = 0 3

Decimal no ÷ Base (8) = Quotient

Remainder

9310 ÷ 16 = 581 14 581 ÷ 16 = 36 5 36 ÷ 16 = 2 4 2 ÷ 16 = 0 2



1 0 1 1 0 1 1 1

1 0 1 0 0 1 0 1 Ans: ( )B10100101

e) i] BCD Additions: ( ) ( )DD 9.7432.256 +

Solutions: 0 0 1 0 0 1 0 1 0 1 1 0 . 0 0 1 0

0 1 1 1 0 1 0 0 0 0 1 1 . 1 0 0 1

1 0 0 1 1 0 0 1 1 0 0 1 . 1 0 1 1 (invalid BCD)

0 0 0 0 0 0 0 0 0 0 0 0 . 0 1 1 0

1 0 0 1 1 0 0 1 1 0 1 0 . 0 0 0 1 (invalid BCD)

0 0 0 0 0 0 0 0 0 1 1 0 . 0 0 0 0

1 0 0 1 1 0 1 0 0 0 0 0 . 0 0 0 1 (invalid BCD)

0 0 0 0 0 1 1 0 0 0 0 0 . 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0 0 . 0 0 0 1 (invalid BCD)

0 1 1 0 0 0 0 0 0 0 0 0 . 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 1 (Valid BCD)

Ans: ( )1.10001

Decimal no × Base (8) = Quotient

result 0.62 × 8 = 4.96 0.96 × 8 = 7.68 0.68 × 8 = 5.44 0.44 × 8 = 3.52



f] BCD Subtraction

(76.53)D – (59.27)D

Solutions: 0 1 1 1 0 1 1 0 . 0 1 0 1 0 0 1 1

0 1 0 1 1 0 0 1 . 0 0 1 0 0 1 1 1

0 0 0 1 1 1 0 1 . 0 0 1 0 1 1 0 0 (invalid BCD)

0 0 0 0 0 1 1 0 . 0 0 0 0 0 1 1 0

0 0 0 1 0 1 1 1 . 0 0 1 0 0 1 1 0 (valid BCD)

Ans: ( )decimal26.17

g] (253) D – (315) D Solutions:

(253)D + (315)D (?)D (253)D = (128 + 64 + 32 + 16 + 8 + 4 + 1)

=(11111101)B

(315)D= 256 + 32 + 16 + 8 + 2 +1

=(100111011)B

(+253) (+315)

1’s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 0 )

+ 1

2’s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 1 )B

= (-315)D

(+253)D + (-315)D

=

0 0 1 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1

0 0 1 1 1 1 1 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0



Verification:- (z)=

1’s Compliment =

+ 1

h] Excess 3 Code Additions i] (956.2) D + (873.4)D

(?)D Solutions:

1 1 0 0 1 0 0 0 1 0 0 1 . 1 0 1 0

1 0 1 1 1 0 1 0 0 1 1 0 . 0 1 1 1

1 0 0 0 0 0 1 0 1 1 1 1 . 1 1 0 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 . 0 0 1 1

0 1 0 0 1 0 1 1 1 1 0 1 . 1 1 0 0 1 0 0 1

1 8 2 . 9 6

i] Excess 3 code Subtractions (47.59)D - (28.38)D

(?)D Solutions: 0111 1010 . 1000 1100

0101 1011 . 0110 1011

0001 1111 . 0010 0001

0011 0011 . 0011 0011

0000 0000 . 1111 0100

1 1 1 1 0 0 0 0 1 0

0 0 0 0 1 1 1 1 0 1

0 0 0 0 1 1 1 1 1 0



Q.2) a] Why NAND gate and NOR gates are called universal gates? Answer: all the logical ckt. are made by using basic 3 logic gates OR, AND, NOT gates, by using only NAND gate . We can design these 3 basic gates OR, AND, NOT gates. Hence any logical ckt. can be completely by using only NAND gate. So NAND gate is called UNIVERSAL gate. Similarly, OR, AND, NOT gate can be designed by using only NOR gats, so any logical ckt. can be completely designed by using only NOR gates. Hence NOR gate is also universal gate.

(a) NAND gate as universal gate: 1] Not gate using NAND gate.

Input AAAY == . NOT gate is obtained by shorting by both the input of NAND gate as shown in fig.

2] AND gate using NAND gate:

AND gate is opposite of NAND gate. So, AND gate is Obtained by Connecting NOT at the output of NAND gate as shown in fig.

3] OR gate using NAND gate:

The output of NOR gate is BABABAY .=+=+= [de-morgan’s 1st thermo then]………….. (1) The logical ckt. og eg.(1) can be obtained by using NAND gate. OR, AND, NOT gate are designed by using only NAND gate. So, NAND gate is Universal.

(a) NOR gate as universal gate: 1] NOT gate using NOR gate:

i/p AAAY =+= NOT gate is obtained from NOR gate by shorting both inputs as shown in fig.

2] OR gate using NOR gate:

OR gate is opposite of NOR gate. So, gate is obtained by connecting NOT gate at the output of NOR gate as shown in Fig. 3] AND gate using NOR gate:



The output of 2 input AND gate is BABAY +== . [De- morgans 2nd theorem]…………..(2) The logical ckt. of eg.(2) can be obtained by using NOR gate as shown in fig. Q.2) b] Prove that:

( )[ ] ( )[ ]( )[ ] ( )[ ]

( ) ( )

...

1.1...

....

.....

...

SHRBA

BABAABBA

BABABABA

BABABASHL

BABABABA

=+=

+=+++=

+++=

++=

+=++

2)

( ) ( )[ ]

[ ]SHR

NGPLUSANYTHIAAXYZXYZZY

XXZYXYZXYZ

XYZZXYXYZZYXSHL

XYZZXYXYZZYX

..111

111

..

1

==∴=

=+∴=+∴+=

+++=

+++=

=+++

Q.2 ) c] State principal of duality. Answer: Principal of duality is used for writing dual equations or for designing dual ckt. for a given local equations, replace each term on L.H.S. and R.H.S. by the corresponding dual terms. The equations obtained will be dual equation of the given equations. Similarly, if any logical ckt. is given then replace each gate by corresponding dual gate. The logical ckt.obtained will be dual of the given ckt. In dual logical ckt. the output will be dual of each other. The different dual terms and dual gates are given in the table below, 0 1

OR gate AND gate

+ .

NOR gate NAND gate

X-OR gate X-NOR gate



(+) (.)

De-morgans 1st theorem Demorgans 2nd theorem

Product term(.) Sum term (+)

SOP equations POS equations

Q.2) d] Prove that De-morgans theorem.

Answer: DEMORGANS FIRST THEROM:

The logical equations of De-morgans 1st theorem for two input is, BABAY .=+= ……..(1)

Similarly for 3 inputs is, CBACBAY ..=++= ……………(2)

STATEMENT: De-morgans first theorem state that complement of ORing will be equal to the ANDing of complements. PROOF: De-morgans first theorem can be proved by using truth table.

Truth table: Inputs A B (A+B) ( )BA +

(L.H.S)

BA . (R.H.S) A B

0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0

As L.H.S. =R.H.S. of equations (1) hence 1st theorem is proved that. The logical Ckt. of L.H.S. and R.H.S. is shown in fig. below.

= BAY += BABA .=+ NOR gate L.H.S = Bubbled input AND gate R.H.S DE-MORGANS SECOND THEROM:

The logical equations of De-morgans 2nd theorem for two input is, BABAY +== . ……..(3)

Similarly for 3 inputs is, CBACBAY ++== .. ……..(4)

STATEMENT: De-morgans second theorem state that complement of ANDing will be equal to the ORing of complements. PROOF: De-morgans second theorem can be proved by using truth table.

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is designedto design lo

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d using k maogical ckt. F

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ce for obtain

ill be of 6

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Design for Y4 A BC BC CB BC CB A

A BAY =4 + AC

Design for Y3 A BC BC CB BC CB A A CBABCAY +=3

Design for Y2 A BC BC CB BC CB A A CBY =2

Design for Y1 A BC BC CB BC CB A A 01=Y

Design for Y0 A BC BC CB BC CB A A CY =0

0

m0

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m1

0

m3

0

m2 1

m4

1

m5

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m7

0

m6

0 mo

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1 m3

0 m4

0 m5

1 m6

0 m7

0 m6

0 mo

0 m1

0 m3

1 m4

0 m5

0 m6

0 m7

1 m6

0 mo

0 m1

0 m3

0 m4

0 m5

0 m6

0 m7

0 m6

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1 m1

1 m3

0 m4

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1 m6

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The i/p w

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A

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INPUT

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CB

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0 0

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1 1

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m6

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nverter Wh

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D

D

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PUT

1 G0

0

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1

0

0

1

1

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0 m3 m1

m7 m

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Design for G0 A BC A

A

Design for G1 A BC A

A

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onvert 3 Bi

the o/p gray

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1

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A=

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PUT GRAY G2 G1 G

0 0 00 0 10 1 10 1 01 1 01 1 11 0 11 0 0

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A

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BC

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1 m3 0

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1 m7

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INARY NUM B1 B0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

CB

CB

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de into equ

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uivalent 3 b

ABCBC +

bit binary n

numbers.



Q.3 d] Design a NAND gate ckt. To detect illegal or invalid BCD number applied at the input.

Solutions: if 4 bit number ABCD applied at the input is valid BCD(0000 to 1001)then output Y should be zero. If input ABCD is invalid BCD (1010 to 1111) then output should be 1. Truth Table:

Valid BCD

Invalid BCD

Design k-map : AB CD CD DC CD DC

AB

BA

AB

BA

ABACY +=

Inputs Output Symbol of Output A B C D Y

0 0 0 0 0 m0 0 0 0 1 0 m1 0 0 1 0 0 m2 0 0 1 1 0 m3 0 1 0 0 0 m4 0 1 0 1 0 m5 0 1 1 0 0 m6 0 1 1 1 0 m7 1 0 0 0 0 m8 1 0 0 1 0 m9 1 0 1 0 1 m10 1 0 1 1 1 m11 1 1 0 0 1 m12 1 1 0 1 1 m13 1 1 1 0 1 m14 1 1 1 1 1 m15

0 mo

0 m1

0 m3

0 m2

0 m4

0 m5

0 m7

0 m6

1 m12

1 m13

1 m15

1 m14

0 m8

0 m9

1 m11

1 m10

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0 1 2 3 4 5 6 7 8 9

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ich convert

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BCD A B

0 00 00 00 00 10 10 10 11 01 0

0 m3

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1 m7

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X m11

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t 4 bit BCD

, BCD num

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D

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D Input B C D0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1

2

6

4

0

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input num

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X- Y3 Y

0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1

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mber into co

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Design k-map for Y2: AB CD CD DC CD DC AB

BA

AB

BA CBDBCDBY ++=2

Design k-map for Y1: AB CD CD DC CD DC

AB

BA

AB

BA CDCDY +=1


AB

BA

AB

DY =0 BA

0 m0

1 m1

1 m3

1 m2

1 m4

0 m5

0 m7

0 m6

m12

X m13

X m15

X m14

0 m8

1 m9

X m11

X m10

1 m0

0 m1

1 m3

0 m2

1 m4

0 m5

1 m7

0 m6

X m12

X m13

X m15

X m14

1 m8

0 m9

X m11

X m10

1 m0

0 m1

0 m3

1 m2

1 m4

0 m5

0 m7

1 m6

X m12

X m13

X m15

X m14

1 m8

0 m9

X m11

X m10

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F] Design Nut. ution:

A0000000011

0 TO m15=X

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NAND gate

Input BCDnumber

A B C 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0

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Y2 Y1 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0

mber applied

output

Y0 1 0 1 0 1 0 1 0 1 0

d at the




AB

BA

AB

ABCY =3 BA


AB

BA

AB

CBCBY +=2 BA Design k-map for Y1: AB CD CD DC CD DC

AB

BA

AB

BA CY =1 Design k-map for Y0: AB CD CD DC CD DC AB

BA

AB

BA DY =0

1 m0

1 m1

0 m3

0 m2

0 m4

0 m5

0 m7

0 m6

X m12

X m13

X m15

X m14

0 m8

0 m9

X m11

X m10

0 m0

0 m1

1 m3

1 m2

1 m4

1 m5

0 m7

0 m6

X m12

X m13

X m15

X m14

0 m8

0 m9

X m11

X m10

0 m0

0 m1

1 m3

1 m2

0 m4

0 m5

1 m7

1 m6

X m12

X m13

X m15

X m14

0 m8

0 m9

X m11

X m10

1 m0

0 m1

0 m3

1 m2

1 m4

0 m5

0 m7

1 m6

X m12

X m13

X m15

X m14

1 m8

0 m9

X m11

X m10

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Q.3 Solu

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G] Design utions:

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NAND gate

CD C

1 m0 m0

m4 m1

m12 m0

m8 m

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e ckt. For t

DC CD

1 m1

X m3

1 m5

X m7

0 m13

X m15

1 m9

X m11

CSE

the function

D DC 0

m2 0

m6

5 0

m14

0

m10

n f= ∑m(0

CABF =

0,1,5,9,12 )+

ABCCD ++

+ d(3,7,11,1

DADB +

15)

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For

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h] Design N

the functio

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ap for functgn k-map: AB CD

AB

BA

AB

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NAND gate

on f’.

functions “fcares will retions f is,

CD C

X m0 1

m4 X

m12 X

m8

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e ckt. For t

f” is opposiemain uncha

DC CD

0 m1 m1

m5 m1

m13 m0

m9 m

CSE

he function

ite of “f’”. Hanged. Henc

D DC 1

m3 0

m20

m7 1

m60

m15 1

m141

m11 1

m10

n f= ∑m(1,

Hence logicce f’= (3,4,

Bf =

2

6

4

0

,2,7,9,15 ) +

c zero of fun5,6,10,11,1

ACBDB ++

+ d(0,8,12)

nction. “f w3,14) + d(0

CDBCBA +

design NAN

will be logic,8,12)

ND ckt.

c input in

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i] Design a

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a multiplier

maximum ve of output r.

in A1 A (A) (B)

0 00 00 00 00 10 10 10 11 01 01 01 01 11 11 11 1

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r ckt. which

value of inpresult will b

nput 0 B1 B0 ) (C) (D)

0 0 0 0 0 1 0 1 0 0 1 1

0 0 0 1 1 0 1 1

0 0 0 0 0 1 0 1 0 0 1 1

0 0 0 1 1 0 1 1

CSE

h will mult

put 2 bit numbe (A1A0)*

Decimal

(A1A0)

0 *0 *0 *0 *1 *1 *1 *1 *2 *2 *2 *2 *3 *3 *3 *3 *

iply 2 num

mber will b(B1B0)=3*

result

*(B1B0)

0 = 0 1 = 0 2 = 0 3 = 0 0 = 0 1 = 1 2 = 2 3 = 3 0 = 0 1 = 2 2 = 4 3 = 6 0 = 0 1 = 3 2 = 6 3 = 9

ber A1A0*

e A1A0 = (3=9=(1001)

Binary resY3 Y2 Y1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 1 1 0 0

B1B0

(11)B =(3)D)B. So we h

sult 1Y0

0 m0 0 m1 0 m2 0 m3 0 m4 1 m5 0 m6 1 m7 0 m8 0 m9 0 m10 0 m11 0 m12 1 m13 0 m14 1 m15

D=B1B0. Hehave to desi

ence the gn the ckt



Design k-map for Y3:

AB CD CD DC CD DC AB

BA

AB

ABCDY =3 BA



BA

AB

CBADACY +=2 BA



BA

AB

BCADBCDCADBAY +++=1 BA

Design k-map for Y3: AB CD CD DC CD DC AB

BA

AB

0 m0

0 m1

0 m3

0 m2

0 m4

0 m5

0 m7

0 m6

0 m12

0 m13

1 m15

0 m14

0 m8

0 m9

0 m11

0 m10

0 m0

0 m1

0 m3

0 m2

0 m4

0 m5

0 m7

0 m6

0 m12

0 m13

0 m15

1 m14

0 m8

0 m9

1 m11

1 m10

0 m0

0 m1

0 m3

0 m2

0 m4

0 m5

1 m7

1 m6

0 m12

1 m13

0 m15

1 m14

0 m8

1 m9

1 m11

0 m10

0 m0

0 m1

0 m3

0 m2

0 m4

1 m5

1 m7

0 m6

0 m12

1 m13

1 m15

0 m14

0 m8

0 m9

0 m11

0 m10

Que

Nagp

Logi

Q.4)

Soluoutp

(((

DES

The com

Usin

Desig

estion Ban

pur Institute o

BA

ical Ckt:

) a] Design

utions: Comput result.

(a) One bit (b) One bit (c) One bit

SIGN OF SI

truth tableparator is

ng two inpu

gn k-map for .A B

nk : DCFM

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BDY =3

and explai

mparator is

for A < B for A > B for A = B

INGLE BIT

e showing tgiven below

uts K-map ,

r (A < B) B

0

M III Sem

gy, Nagpur

in of two bi

a device w

T COMPAR

two single bw,

2 i/p nu

A

0 0 1 1

, we have to

B

1

co

CSE

it compara

which will c

RATOR

bit number

umber

B

0 1 0 1

o design th

One bit omparator

tor.

compare th

A < A > A=B

r A and B a

O

A < B

0 1 0 0

hree differe

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B B

B

and the corr

Output

A = B A

1 0 0 1

nt ckt. For

o input num

responding

A > B

0 0 1 0

r 3 bit outp

mber and g

g output of

ut.

ives 3 bit

Que

Nagp

Desig

Desig

Logi

Q.4

SoluLetsIf thapplcondA<B

So, (A=B

So, (A>B

So, (Two

estion Ban

pur Institute o

A

A (A <

gn k-map for .A B A

A

gn k-map for .A B A

A

ical Ckt:

b] Design a

utions: Two first numb

he first two ied first on

ditions for tB:-

(A1<B1)(A<B) = (A

B:- (A1=B1)

(A=B) = (AB:-

(A1>B1)(A>B) = (A

o bit compar

nk : DCFM

of Technolog

) BAB =<

r (A = B) B

r (A > B) B

and explain

o bit comparer A=A1 A0bit number e bit compa

three bit out

)OR [(A1=BA1<B1) + [(A

)AND (A0=A1=B1). (A0

)OR [(A1=BA1>B1) + [(Arator using

0

1

0

0

1

One b

compara

M III Sem

gy, Nagpur

B

(A

B

(A

n of two bit

rator is used0 and seconis A=A1 A

arator and Ltput of com

B1) AND (AA1=B1). (A

=B0) 0=B0)………

B1) AND (AA1=B1). (Aone bit com

0

0

1

0

0

it ator

CSE

) ABB +==

) BAB =>

t comparat

d to comparnd number B0 and the se

LSB’s A0,Bmparator are

A0<B0)] A0<B0)]……

………… (2)

A0>B0)] A0>B0)]……mparator is o

A1 < B1

AB+

or.

re two numbB=B1B0. econd bit nu0 are appliegiven below

…………… (

)

…………. (3obtaining fr

bers of two

umber B=Bed to secondw.

(1)

) rom equatio

O

com

bits each.

1 B0,then thd one bit co

ns 1,2,3 an

One bit mparator

he MSB’s Aomparator. T

d it is show

A0 <

A1,B1are The

wn in below,

B0

,

Que

Nagp

Desig

estion Ban

pur Institute o

A1

B1

gn k-map for AB CD

AB

BA

AB

BA

nk : DCFM

of Technolog

r (A < B) D CD

A1 (A)

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 m0 0

m4 0

m12 0

m8

M III Sem

gy, Nagpur

DC

2 i/p nA0 (B) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

1 m1 0

m5 0

m13 m0

m9 m

CSE

A1=B1

A1>B1

CD

number B1 (C)

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

1 m3 m1

m7 m0

m15 m1

m11 m

A0 B0

DC

A <(

B0 (D)

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 m2 1

m6 0

m14 0

m10

0

0

CAB +=< )

OuA<B A

0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

CDBDAB +

tput =B A>B

1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 1 0

A0 =

A0 >

D

B

B0

B0



Design k-map for (A=B)


BA

AB

DCBAABCDDCBAABCDBA +++== )( BA

Design k-map for (A > B) AB CD CD DC CD DC

AB

BA

AB

DABCDBCABA ++=> )( BA

Logical Ckt:

1 m0

0 m1

0 m3

0 m2

0 m4

1 m5

0 m7

0 m6

0 m12

0 m13

1 m15

0 m14

0 m8

0 m9

0 m11

1 m10

0 m0

0 m1

0 m3

0 m2

1 m4

0 m5

0 m7

0 m6

1 m12

1 m13

0 m15

1 m14

1 m8

1 m9

0 m11

0 m10

Que

Nagp

Q.5]

Solutbit da

((

(1)thgate Add

Parit Parity

(a) E

even will b1] If rema2] If

estion Ban

pur Institute o

what is a pa

tions: In ”n” ata is odd no.(a) If the pari(b) If the parihe truth table sis given belowall the input b

A 0 0 0 0 1 1 1 1

ty generator

y generator is(a

(b

Even parity g

Even pariparity genera

be of 9 bits (Dthe parity of

ain even. the parity of

nk : DCFM

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arity generato

bits data, the then it is callity of input daity of input dashowing 3 bitw. bit’s and writ

Inpu

s used to genea)Even parity

b)Odd parity

generator:

ty generator iator. The pariDp and D7 to 8 bit input nu

8 bit input da

M III Sem

gy, Nagpur

or? Explain t

count of numled odd parityata of X-OR gata of X-OR gt input numbe

te the sum neg

ut number B 0 0 1 1 0 0 1 1

erate “n” bits y generator

y generator

is used to genity generator gD0) .The par

umber D7 to D

ata (D7 to D0)

CSE

the diagram

mber of one’s y data.X-OR ggate is alwaysgate is odd ther X-OR gate,

glecting the c

C 0 1 0 1 0 1 0 1

no. of a parti

nerate even pagenerates onerity of this 9 bD0 is already

) odd then pa

even and od

bit is called agate is used tos zero. en output of X, then parity o

arry for 3 I/P

X-ORO

01101001

icular parity. T

arity number. e parity bit Dpbits output wieven parity b

rity bit Dp=1

dd parity gen

as parity. If tho detect the p

X_OR gate isof input data a

X-or gate.

R gate O/P

0 1 1 0 1 0 0 1

There are two

The 8 bit nump. So, the outpill be always ebit output will

. So parity of

nerator.

he count of nuparity of “n” b

s always zero.and the corres

Parity

EOOEOEEO

o types of par

mber D7 to Dput number oeven. l be always ev

f 9 bits output

umber of oncbits data.

. sponding outp

y of output I/P

Even Odd Odd Even Odd Even Even Odd

rity generator

D0 is applied aof even parity

ven output da

t data will bec

e bit in “n”

put of X-OR

.

at the i/p of generator

ata will

come even.

Que

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(b)O

Odd

gener

D7 to

rema

becom

Q.6]

Solut

into f

(1)R

(2)D

(3)TT

(4) E

(5)CM

chann

estion Ban

pur Institute o

Odd parity ge

parity genera

rator. The par

o D0). The pa

(1) If the pain odd.

(2) If the pme odd.

Explain clas

tions: Depen

following typ

TL [resistan

The logic

TL [diode tr

The main

TL [transisto

The logic

ECL [emitter

The logic

MOSEFET (

The logic

nel and one “

nk : DCFM

of Technolog

enerator:

ator is used to

rity genaerato

arity of this 9

parity of inpu

parity of 8 bit

ssification of

nding upon the

pes.

ce transistor

gates of RTL

ransistor logi

components

or transistor

gates of TTL

r couple logic

gates of ECL

(complement

gates of CMO

“n” channel M

M III Sem

gy, Nagpur

generate odd

or generates o

bits output w

ut number D7

t input numbe

f logic familie

e main compo

r logic] family

L family are m

ic] family:

of DTL fami

logic] family

L family are o

c] family:

L family are m

tary MOSEF

OSFET logic

MOSFET.

CSE

d parity numb

one parity bit

will be always

7 to D0 is alre

er D7 to D0 is

es and prope

onents which

y:

made by using

ly gates are d

y:

obtained from

made emitter c

FET) logic:

c family are m

ber. The 8 bit

Dp. Hence th

odd.

ady odd then

s even then p

rties of logic

are used to fa

g resistance an

diodes and tra

m logic gates o

coupled trans

made by using

number D7 to

he output parit

parity bit Dp

arity bit Dp=

families.

fabricate logic

nd transistor

ansistors.

of DTL family

sistor as main

g complement

o D0 is applie

ty generator w

p=0, So, the p

1. So the pari

c gate. Logic g

as main comp

y by replacing

n components.

tary pair of M

ed at the inpu

will be of 9 b

parity of 9 bit’

ity of 9 bits ou

gates families

ponents.

g diodes with

.

MOSFET i.e.,

ut odd parity

its. (Dp and

’s output will

utput will

s are divided

h transistors.

one P

Que

Nagp

Prop

The t

propa

meas

obtai

The p

logic

For b

logic

(td) a

vice

The m

is mo

The m

FAN

estion Ban

pur Institute o

perties or cha

(1)PROP

I/P

time differenc

agation delay

sured between

ined (b).

(2)POWE

power that is

c gate is better

(3)PROD

better logic ga

c gates Td is s

and power dis

versa.

(4) FAN I

maximum nu

ore than logic

(5) FAN O

maximum nu

N OUT is more

nk : DCFM

of Technolog

aracteristics

POGATION D

P A

ce between th

y time: if prop

n the instant a

ER DISSIPA

obtained in o

r and vice ver

DUCT OF TD

ates the value

small and Pd i

ssipation(Pd)i

IN

mber of o/p o

c gates is bette

OUT

mber of input

e than logic g

M III Sem

gy, Nagpur

of logic fami

DELAY TIM

O/P

he install at w

pagation time

at which 50%

ATION (PD):

one gate is cal

rsa.

D OR PD

e of propagatio

is large and v

is obtained. T

of gates which

er and vice ve

ts of other ga

gates is better

CSE

ilies

ME [TD OR T

P Y

which i/p is app

is less then lo

of the i/p sig

lled ad power

on delay time

vice versa. So

The logic fami

h can be conn

ersa.

ates which can

and vice vers

TP]:

plied and the

ogic gates is f

gnal is applied

r dissipation p

e as well as po

for selecting

ily in which t

nected to a sin

n be connecte

sa.

installed at w

fast and vice v

d (a) and the i

per gate. If po

ower dissipat

logic gates, t

this products (

ngle i/p of one

ed to output of

which o/p is o

versa the prop

instant at whi

ower dissipati

ion should be

the product of

(td * pd) is m

e gate is calle

f one gate is c

obtained is cal

pagation dela

ch 50% of the

on per gate is

e small be. Bu

f propagation

minimum is th

ed as FAN IN

called as FAN

lled as

ay time is

e o/p signals

s less then

ut in some

n delay time

e family and

N. if FAN IN

N OUT. If

Que

Nagp

In log

super

volta

marg

Q. 9]

SolutB are

((

The lDesig

estion Ban

pur Institute o

(6) NOIS

gic gates, the

rimposed on o

age which can

gin.

] a] Explain h

tions: a logice applies ti the

(a) One bit fo(b) One bit fo

logical ckt. ofgn for Sum(S

A B

A

A

0

1

nk : DCFM

of Technolog

E MARGIN

gates input a

o/p voltage of

n be superpose

half adder C

c ckt. Which e input of Ha

or sum (S) andor carry gener

f half adder cS):

B B 0

m0 1

1 m2

0

M III Sem

gy, Nagpur

and output sig

f logic gates t

ed on o/p bec

Ckt.

performs addft Adder. HA

d rated (Co).

an be designe

B

S

InpA 0 0 1 1

m1

m3

CSE

gnals are in th

then the value

cause of which

ditions of onlyA performs the

The Truth T

ed using K-M

BABAS +=

ut (A + B) B 0 1 0 1

he form of vol

e of o/p voltag

h the o/p logi

y two binary be addition (A+

Table of half

Map:

SumS0110

ltage which is

ge will chang

ic remains un

bits is called a+B and gives A B

Co

f adder:

m CarC0001

Half Add

(A+B)

s denoted by l

ge. The maxim

changed is ca

as half adder.2 bit o/p resu

B

S

rry o

0 0 0 1

der

)

logic 1. If noi

mum value of

alled ad noise

. The two binult.

ise voltage is

f noise

e voltage

ary bit A and

d



Design for Carry (Co): A B B B

A

A

ABCo =

Logical Circuit A B

BABAS +=

ABCo = Q. 9] b] Explain Full Adder Ckt.

Solutions: when we perform additions of two multibit number then we have to perfume additions of 3 bits. A logical ckt. Which is used to perform additions of 3 binary bits is called as full adder. The 3 binary bits A, B, C in applied of the i/p of Full adder. So, gives 2 bit output result.

(1) One bit for sum(A + B + Cin) (2) One bit for carry out(Co.) A B

Cin

Co S

The truth able for full adder ckt. Inputs (A + B + Cin) Sum Carry

A B Cin So Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Design K Map For Full Adder Ckt.

0 m0

0 m1

0 m2

1 m3

Full Adder (A +B + Cin)



Half Subtractor (AB)

Design for Sum(S):

A BC CB CB BC CB

A

A

ABCBCACBACBAS +++= Design for Sum(S):

A BC CB CB BC CB

A

A

BCABACCo ++= The logical ckt of full adder

Q. 9] c] Explain Half Subtractor Ckt. Solutions: A logic ckt. Which performs Subtractions of only two binary bits is called as half Subtractor. The two binary bit (A – B). Is called as Half Subtractor A B

(a) One bit for Difference (D) and (b) One bit for Borrow Required to perfume the subtraction

(A-B) i.e., borrow out (Bo). The truth table of half Subtractor:

Bo D

The logical ckt. of half Subtractor can be designed using K-Map:

0 m0

1 m1

0 m3

1 m2

1 m4

0 m5

1 m7

0 m6

0 m0

0 m1

1 m3

0 m2

0 m4

1 m5

1 m7

1 m6

Input (A - B) Difference Borrow A B D Bo 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0



Design for Difference (D): A B B B

A

A

BABAD +=

Design for Borrow (Bo): A B B B

A

A

BACo =

A A B

BABAD +=

BABo =

Q. 9] d] Explain Full Subtractor Ckt.

Solutions: when we perform Subtractions of two multibit number then we have to perfume Subtractions of 3 bits. A logical ckt. Which is used to perform Subtractions of 3 binary bits is called as full Subtractor. The 3 binary bits A, B, C in applied of the i/p of Full Subtracto. So, gives 2 bit output result.

(1) One bit for Difference(A - B - Cin) (2) One bit for Borrow out(Bo.) A B

Cin The truth able for full Subtracto ckt. Bo D

Inputs (A - B - Cin) Difference Borrow A B Cin D Bo 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0

0 m0

1 m1

1 m2

0 m3

0 m0

1 m1

0 m2

0 m3

Full Subtractor (A B Cin)

Que

Nagp

DesigDesig

Desig

Q. 10Solut

estion Ban

pur Institute o

1 1

gn K Map Fogn for Sum(S

A BC

A

gn for Borro

A BC

A

Logical C A

0] Explain intions:

A The blocknumber w If A3 A2 below,

0

1

0

0

Fu

nk : DCFM

of Technolog

1 0 1 1

or Full Adder S):

C CB

ow(Bo):

C CB

Ckt. of Full Su B

n parallel bin

A3 B3

C3 S3

k diagram of 4without carry

A1 A0 and B

0 m0

1

1 m4

0

0 m0

0 m4

ull Adder 3

M III Sem

gy, Nagpur

0 1

Ckt.

CB

CB

ubtractor CS

nary adder.

A2

C2

4 bits parallel

B3 B2 B1 B0 a

m1 0

m5 1

1 m1

0 m5

Full A2

CSE

0 1

BC

BC

B2

2 S2

l binary adder

are two 4 bit

m31

m7 0

1 m3

1 m7

Adder 2

CB

D =

CB

A1

C1

r is shown in

number then

m2

m6

1 m2

0 m6

Full Add1

CBACBA +=

CABo =

B1

S1

figure; it is u

parallel binar

Differen

Borrow

der

A

ABCAC ++

BCBAC ++

A0 B0

C0 S

sed to perform

ry adder perfo

ce

Full Adder 0

ABC

A

0

S0

m additions o

orms the addi

of two 4 bit

itions as givenn



Carry generated

1st number

2nd number

Result FA3 FA2 FA1 FA0

The 4 bit parallel binary adder performs the additions of two 4 bit number and given 5 bit result of additions. To performs additions of two C1 bit number with carry. We have to replace half adder HA0 by Full adder FA0. Q.11] explain parallel binary subtractor. Solutions: A3 B3 A2 B2 A1 B1 A0 B0 B3 D3 B2 D2 B1 D1 B0 Do The block diagram of 4 bits parallel binary Subtractor is shown in figure; it is used to perform subtractions of two 4 bit numbers. If A3 A2 A1 A0 and B3 B2 B1 B0 are two 4 bit number then parallel binary Subtractor performs the Subtractions as given below,

FA3 FA2 FA1 FA0 1st number

2nd number

Borrow Required Result B’3 If the last borrow B’3=1 then it indicates that the result is –ve represented in 2’s compliment from. If the last borrow B’3=0 then it indicates that result is either zero or +ve. This 4 bit parallel binary subtractor performs subtractions of two 4 bit number without borrows. To performs subtractions of two 4 bit numbers with borrow, we have to replace half subtractor HDo by full Subtractor FSo.

C2 C1 CO

A3

B3

A2

B2

A1

B1

A0

BO

C3 S3 S2 S1 S0

A3

B3

A2

B2

A1

B1

A0

BO

B’2 B’1 B’0

D3 D2 D1 D0

Full Subtractor

0

Full Subtractor

1

Full Subtractor

2

Full Subtractor

3

Que

Nagp

Q. 12

Solut

The lOper

(

(

If logvalue

Q. 13

Solut

estion Ban

pur Institute o

2] design and

tions: B

logical ckt of rations: (1) B3 B2 B1

B = B. Henc theY3 Y2 Y1

(2) If control1 (+) B =Hence the

Y3 Y2 Y1That is; o

gic 1 is addede i.e. (-B3 B2

3] Design and

tions: A3 B3 I

A3

C3

Full Ad

3

nk : DCFM

of Technolog

d explain 1’s

B3

Y3

f 4 bit controll

1 Bo is 4 bit n

e 4 bit output1 Yo = B3 Bl input “I” isB e 4 bit outpu

1 Yo = BB 23output = 1’s cd to this 1’s co B1 Bo)

d explain pa

3

Y3

C2

S3

B3 dder

M III Sem

gy, Nagpur

compliment

B2

Y2

led inverter is

number appl

t will be 2 B1 Bo i.e.,

s made 1, the

ut will be,

BoB12 compliment ompliment the

rallel arithm

A2 B

A2

C2 S2

BFull Adde

2

CSE

t ckt or contr

B1

Y1

s shown in fig

lied at the inp

output = inpen in X-OR g

of input. en we will ge

metic unit or e

B2

Y2

C1

2

B2 er

rolled inverto

Bo

Y0

g.

put .if contro

put. gate,

et 2’s complim

element.

A1

A1

C1 S1

B1 Full Adder

1

ors.

I Cont

ol input “I” i

ment of B3 B2

B1

Y1

Co

C

Fu

rol Input

is made zero

2 B1 Bo and

Ao

Ao

Co So

Bo ull Adder

0

then in X-O

it will represe

Bo

o Yo

I/O

R gate; 0 (+)

ent its –ve

I/O

Control I/P

)



The bloc diagram of 4 bit parallel arithmetic unit is shown in fig. it can additions as well as subtractions using 2’s compliment method. OPERATIONS: (1)Additions operations: The two 4 bit binary numbers A3 A2 A1 Ao and B3 B2 B1 Bo are applied at the i/p and control input is made zero. So output of X-OR gate will be Y3 Y2 Y1 Yo = B3 B2 B1 Bo. Hence 4 bit parallel binary adder performs the following additions. Carry generated

1st number

2nd number

Controlled i/p

Result FA3 FA2 FA1 FAo (2)Subtraction operations: To perfoms the subtraction A3 A2 A1 Ao minus (-) B3 B2 B1 Bo the two number applied at the i/p and control i/p “I” is made. So, output of X-OR gate will be 1’s compliment of the input that is;

Y3 Y2 Y1 Yo = BoBBB 123 Hence the 4 bit parallel binary adder performs the following additions. Carry generated

1st number

2nd number (2’s compliment) Controlled i/p

Result FA3 FA2 FA1 FAo If the last carry C3 is neglected then we will get 4 bit result of subtractions i.e., S3, S2, S1, So. Q.14] Design and explain BCD ADDER or 8421 ADDER or SINGLE DIGIT DECIMAL ADDER. Solutions: the block diagram of 4 bit or single adder is shown in fig.(1) OPERATIONS: (1) If A3 A2 A1 Ao and B3 B2 B1 Bo are two 4 bit BCD number, then using FA’s. FAo to FA3. These two BCD

number are added with carry (Cin). To performs additions without carry Cin is made zero. The additions of BCD number with carry is perfomed as given below,

C2 C1 CO A3

B3

A2

B2

A1

B1

Ao

Bo

0 C3 S3 S2 S1 S0

C2 C1 CO

A3

B3

A2

B2

A1

B1

Ao

Bo

0 C3 S3 S2 S1 S0

Que

Nagp

Cou(Car

(2) T

If 4 LLSBY= (This (3) U Carr4 LS

Num

Corr

estion Ban

pur Institute o

ut rry Out)

The logical ck

23ss

23ss

23ss

23ss

23ss

LSB’s of resu’s of result S3S3 S2 S1 S0)logical ckt. O

Using HAo, H

ry generated SB’S of Resul

mber 0YY0 (6

rect BCD res

nk : DCFM

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kt to detect 4

sos1 sos1

ult S3 S2 S1 S3 S2 S1 So . t) + (C3)………Of eq. (1) can

HA1,FA4 ,(0

lt

6)

sult

0 m0

0 m4

1 m12

0 m8

M III Sem

gy, Nagpur

A

LSB’s of res

sos1

So is greater ththe logical ckt……….(1) be designed

Y Y 0)numb

0 m1

0

0 m5

0

1 m13

1

0 m9

1

CSE

A3 B3

C3 S

C’3

sult S3 S2 S1

sos1 s

han 9 (invalidt. To check th

using AND-O

er is added to

m30

m70

m151

m111

HA1

C’2

S3

Y

Z3

Full Adder 3

Full Adder 3

A2 B

S3 C2

Z3 C

So for invalid

sos1

Y =

d BCD)OR lahese two cond

OR gate or NA

o the 4 LSB’s

m2

m6

m14

m10

FA4

C’1

S2

Y

HA

S1

Y

Z2 Z1

FAdd

FAdd

B2 A1

S2 C

C’2 Z2

d BCD can de

13.32 ssss=

ast carry C3=1ditions is obta

AND-NAND

of result S3 S

Ao

1

Y

S0

0

1 Z0

Full der 2

Full der 2

1 B1

C1 S1

Y

C’1 Z1

esigning usin

1then we havained using th

D gate.

S2 S1 So, as

Full Adder 1

Full Adder 1

Ao Bo

1 Co

1

g K-map as g

e to add 6(01he equations.

given below.

FulAdd

o

So

Zo

given below.

10)to the 4

ll der



If 4 LSB’s of result is greater than, 9 or last carry C3=1 then Y= 1. So, 0 Y Y 0=0 1 1 0=6. Hence 6 is added to the 4 LSB’s of result S3 S2 S1 S0 and the final result obtained Z3 Z2 Z1 Z0 is correct BCD result, the last carry out will be equal to “Y”.

Q.15] Obtain using MUX the logical ckt. For the SOP eq. ABCCABAY ++= Solutions: the standard form of given eq. is;

ABCCABCBACBACBAY ++++= ………………… (1) The given SOP equations can be expressed. F=∑ m (2, 3, 4, 6, 7)………………….. (2)

+ve D0

D1

D2

D3 8 to 1

D4 MUX Output Y

D5

D6

D7

0 ve A B C

Control Inputs

Q. 15) B] using 8 to 1 MUX implement the eq. CAABDCABY ++= . Assume ABD as control inputs.

Solutions:

BCACABDCABABCDDCABCDABY +++++=

DBCADBCADCABDCABDCABABCDDCABCDABY +++++++= (0 0 1 1, 0 0 1 0 , 1 1 1 1 , 1 1 0 1 , 1 1 0 0 , 1 0 0 1 , 1 0 0 0 )

INPUTS OUTPUT

SYMBOL OF

RELATION OF

A B D C Y O/P Y & C

0 0 0 0 0 m0 Y=0=Do 0 0 0 1 0 m1

0 0 1 0 1 m2 Y=1=D1 0 0 1 1 1 m3

0 1 0 0 0 m4 Y=0=D2 0 1 0 1 0 m5



0 1 1 0 0 m6 Y=0=D3 0 1 1 1 0 m7

1 0 0 0 1 m8 Y=1=D4 1 0 0 1 1 m9

1 0 1 0 0 m10 Y=0=D5 1 0 1 1 0 m11

1 1 0 0 1 m12 Y=1=D6 1 1 0 1 1 m13

1 1 1 0 0 m14 Y=B=D7 1 1 1 1 1 m15

+ 5ve

Do

D1

D2

D3 8 TO 1

D4 MUX

D5

D6

D7

0 ve C A B D

Que

Nagp

Q.15Solut

((

Q. 15

SolutAs oucorreNAN

estion Ban

pur Institute o

5) E] Obtain tions:

(1) We have t(2) One IC of

C

5) f] impleme

tions: utput DE-Mesponding ou

ND gate ckt.

nk : DCFM

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8 to 1 MUX

to use 2 Ic’s of 2 to 1 MUX

B

ent the funct

UX is low levutput of De=

Di

M III Sem

gy, Nagpur

Using 4 to 1

of 4 to 1 MUXX.

Do

D1 4

D2

D3

D4

D5 4 T

D6 M

D7

tions ∑=f

vel active, heMUX will be

D

CSE

MUX.

X.

4 TO 1

MUX

TO 1

MUX

)7,5,2,1(m u

ence in De-Me connected t

1 TO 8

DEMUX

Y1

Y2

sing 1:8 DE-

MUX , insteadto NAND gat

Y0

Y1

Y4

Y5

Y6

Y7

Y1 Y2

-MUX having

d of AND gatte instead of

1 2:12 MUX

A

g low level ac

te NAND gatOR gate, tha

Output Y

ctive output.

te is used. So at is we get N

O

.

the NAND-

Output F

Que

Nagp

Q.15

Solut

For sSo wFor c

Q.16

Soluthave In them1 =So.mSo w

estion Ban

pur Institute o

5) G] Design

tions: Full ad

sum m1 = m2we have to concarry out m3 =

D

6) A] implem

tions: as outpto connect N

e given functi= m2 = m4 = mm0 = m3 = m5we have to cor

nk : DCFM

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Full Adder u

dder will perfo

2 = m4 = m7=nnect Y1, Y2,= m5 = m6 =

Di

ent the funct

put of decodeNAND hate.

ion; m6 = 0

5 = m7 = 1 rrect the o/p’s

M III Sem

gy, Nagpur

using DE-Mu

forms addition

Inpu A + B

0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

=1 , Y4, Y7 outpm7 = 1. So, w

A B

tion ∏=f

r’s low level

s Y0, Y3, Y5,

1 TO 8

De‐Mux

CSE

ultiplexer.

n of 3 bit bina

ut B + C Su

0 1 0 1 0 1 0 1

put of De-Muxwe have to co

C

)6,4,2,1(m u

active, hence

Y7 of decod

Yo

Y1

Y2

x Y3

Y4

Y5

Y6

Y7

ary bits as giv

Outpuum(S) Ca

0 1 1 0 1 0 0 1

x. onnect Y3, Y5

sing decoder

e the decoder

der to NAND

ven in the trut

ut arry (Co)

0 0 0 1 0 1 1 1

5, Y6, Y7 out

r having low

consist of NA

gate.

th table.

m0 m1 m2 m3 m4 m5 m6 m7

tput of De-Mu

S

C

level active o

AND gates. S

ux.

um

arry

output.

o, instead of OOR gate we

Que

Nagp

Q.16

Solut

estion Ban

pur Institute o

6) B] design f

tions: Truth Ta

Input Di

nk : DCFM

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full Subtracto

able

De

M III Sem

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Input Di

or using deco

Input A - B - 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

Yo

Y1

3 to 8 Y2

ecoder Y3

Y4

Y5

Y6

Y7

CSE

oder.

C Diffe0 1 0 1 0 1 0 1

D

o

1

2

3

4

5

6

7

Outpuerence(D)

0 1 1 0 1 0 0 1

Yo

Y1

3 to 8 Y2

Decoder Y3

Y4

Y5

Y6

Y7

ut Borrow (Bo)

0 1 1 1 0 0 0 1

o

1

2

3

4

5

6

7

)

m0 m1 m2 m3 m4 m5 m6 m7

Borrow

Difference

output f

e



Q. 18) A] Explain BCD to 7 Segment Decode.

Solutions: (a) Segment display:

7 segment display consist of LED’s “a to g” in the form of segment . these 7 segments are physically arranged like decimal digit 8. There is one circular LED for a decimal point (dp).these 8 LED’s are connected either in common cathode configuration (Fig 2)or in common anode configuration (fig3) in fig(2) by giving logic 1/0 to the anode. LED can be made on/off resp. similarly in fig (3) by giving logic 0/1 to the cathode LED can be made on/off resp. a a b ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐ c f b 0 ve (Common cathode connection) Fig(2) e c +5 ve d (Common anode connection) Fig(3)

(b) Design of BCD to 7 segment decode: When 4 bit no is applied to the input of decoder then decoder will give corresponding will give corresponding 7 bit output Ya to Yg, if these 7 bits are applied to the 7 Led’s a to g of 7 segment display then the decimal digit corresponding to the BCD input is displayed on 7 segment display. If 7 segment display is connected in common cathode configuration then to make the LED on/off , decode will give logic input to the anode it LED. Ya

A Yb

B BCD Yc

C to Yd

D 7 segment Ye

Decoder Yf

Yg

(Physical structure) (7 segment display in common cathode configuration)



The truth table showing BCD input and the required output of decoder for displaying equivalent decimal digit to given below.

Input Equation Decimal Digit

7 segment output A B C D

Ya Yb Yc Yd Ye Yf Yg

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 1 0 1 1 0 0 0 0

0 0 1 0 2 1 1 0 1 1 0 1

0 0 1 1 3 1 1 1 1 0 0 1

0 1 0 0 4 0 1 1 0 0 1 1

0 1 0 1 5 1 0 1 1 0 1 1

0 1 1 0 6 1 0 1 1 1 1 1

0 1 1 1 7 1 1 1 0 0 0 0

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 1 1 0 1 1 The logical ckt. Of decoder can be designed using K-Map,DRAW 4 INPUT K- MAP AB CD CD DC CD DC

AB

BA

AB

BA As inputs BCD, So, m10 to m15=X (Don’t care); Design for Ya AB CD CD DC CD DC

AB

BA

AB

BDBDCAYa +++= BA

m0

m1

m3 m2

m4

m5

m7 m6

m12

m13

m15 m14

m8

m9

m11 m10

1 0 1 1

0 1 1 1

X X X X

1 1 X X



Design K-Map Yb AB CD CD DC CD DC

AB

BA

AB

BCDCDYb ++= BA Design K-Map for Yc:


BA

AB

BA

BDCYc ++= Design K-Map for Yd:


BA

AB

BA BDDCBCBADCYd ++++=

1 1 1 1

1 0 1 0

X X X X

1 X X X

1 1 1 0

1 1 1 1

X X X X

1 1 X X

1 0 1 1

0 1 0 1

X X X X

1 1 X X



Design for Ye: AB CD CD DC CD DC

AB

BA

AB

DCBDYe += BA

Design for Yf: AB CD CD DC CD DC

AB

BA

AB

BA DBCDCBAYf +++=

Design for Yg: AB CD CD DC CD DC

AB

BA

AB

BA CBDCDBAYg +++=

1 0 0 1

0 0 0 1

X X X X

1 0 X X

1 0 0 0

1 1 0 1

X X X X

1 1 X X

0 0 1 1

1 1 0 1

X X X X

1 1 1 X

Que

Nagp

Q.18

Solu

Whenthesedisplequiv

estion Ban

pur Institute o

8) b] Expla

utions:

A

B

C

D

n 4 bit binarye 7 bits are aplayed on 7 segvalent hexade

nk : DCFM

of Technolog

ain binary t

A

B

C

D

(Phy

y no. is appliepplied to the agment displayecimal digit is

M III Sem

gy, Nagpur

to 7 segmen

BCD

to

7 segment

Decoder

ysical structu

ed of the inputanode of 7 LEy .the table shs given below

CSE

nt decoder.

Ya

Yb

Yc

Yd

Ye

Yf

Yg

re)

t of decoder, ED’s “a to g” thowing 4 bit bw.

c

then decoder then the hexabinary input a

(7 segm com

will gate corradecimal digitand the requir

ment display immon cathode

responding 7 t correspondined output of d

in e configuration

bits output Yng to the binadecoder for d

n)

Ya to Yg. If ary input is isplaying



Input Equation Decimal Digit

7 segment output A B C D

Ya Yb Yc Yd Ye Yf Yg

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 1 0 1 1 0 0 0 0

0 0 1 0 2 1 1 0 1 1 0 1

0 0 1 1 3 1 1 1 1 0 0 1

0 1 0 0 4 0 1 1 0 0 1 1

0 1 0 1 5 1 0 1 1 0 1 1

0 1 1 0 6 1 0 1 1 1 1 1

0 1 1 1 7 1 1 1 0 0 0 0

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 1 1 0 1 1

1 0 1 0 10(A) 1 1 1 0 1 1 1

1 0 1 1 11(B) 0 0 1 1 1 1 1

1 1 0 0 12(C) 1 0 0 1 1 1 1

1 1 0 1 13(D) 0 1 1 1 1 0 1

1 1 1 0 14(E) 1 0 0 1 1 1 1

1 1 1 1 15(F) 1 0 0 0 1 1 1

Design for Ya AB CD CD DC CD DC

AB

BA

AB

BDABADABCCABDYa +++++= BA

1 0 1 1

0 1 1 1

1 0 1 1

1 1 0 1



Design K-Map Yb AB CD CD DC CD DC

AB

BA

AB

DCABDCDAACDABYb ++++= BA Design K-Map for Yc:


BA

AB

DCBABADACAYc ++++= BA Design K-Map for Yd


BA

AB

DCADBCCDBDCBCABCDYd +++++= BA

1 1 1 1

1 0 1 0

0 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 1 0 0

1 1 1 1

1 0 1 1

0 1 0 1

1 1 0 1

1 1 1 0



Design for Ye AB CD CD DC CD DC

AB

BA

AB

DCACABBDYe +++= BA

Design for Yf AB CD CD DC CD DC

AB

BA

AB

BA

DBCBABABACDYf ++++=

Design for Yg AB CD CD DC CD DC

AB

BA

AB

BA

CBAADBADCCBYg ++++=

1 0 0 1

0 0 0 1

1 1 1 1

1 0 1 1

1 0 0 0

1 1 0 1

1 0 1 1

1 1 1 1

0 0 1 1

1 1 0 1

0 1 1 1

1 1 1 1



Logical Ckt.



Q.23) Conversions:

Solutions: Excitations Table of different Flip Flop.

Previous O/P

Qn Next Required O/P

Qn+1 Inputs to Flip/ Flop

J K S R D T 0 0 0 X 0 X 0 0 0 1 1 X 1 0 1 1 1 0 X 1 0 1 0 1 1 1 X 0 X 0 1 0

1) Convert J-K Flip Flop into S-R Flip Flops. Solutions:

Flip Flop available=> J-K Flip Flop. Flip Flop => S-R Flip Flop.

Inputs Next Required O/P Qn+1

Inputs to Flip/ Flop Available S R Qn J K 0 0 0 0 0 X 0 0 1 1 X 0 0 1 0 0 0 X 0 1 1 0 X 1 1 0 0 1 1 X 1 0 1 1 X 0 1 1 0 X X X 1 1 1 X X X

Truth table Excitation Table Design for J

Pr S RQn RQ QR RQ QR S S

SJ =

Clr

0 X X 0

1 X X X

J Q

K Q



Design for K S RQn RQ QR RQ QR S S

RK =

2) Convert S-R Flip Flop into J-K Flip Flops. Solutions:

Flip Flop available=> S-R Flip Flop. Flip Flop => J-K Flip Flop.


Inputs to Flip/ Flop Available J K Qn S R 0 0 0 0 0 X 0 0 1 1 X 0 0 1 0 0 0 X 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 X 0 1 1 0 1 1 0 1 1 1 0 0 1

Truth table Excitation Table Design for S

J KQn KQ QK KQ QK

J

J

JQS =

Design for K J KQn KQ QK KQ QK J J

KQR =

X 0 1 X

X 0 X X

0 X 0 0

1 X 0 1

X 0 1 X

0 0 1 0



Logical Circuit

3) Convert S-R Flip Flop into D Flip Flops. Solutions:

Flip Flop available=> S-R Flip Flop. Flip Flop => J-K Flip Flop.


Inputs to Flip/ Flop Available D Qn S R 0 0 0 0 X 0 1 0 0 1 1 0 1 1 0 1 1 1 X 0

Excitation table Design for S

D Q Q Q

D D

DS =

Design for R

D Q Q Q

D D

DR =

0 0

1 X

X 1

0 0



Logical Ckt.

4) Convert T Flip Flop into S-R Flip Flops. Solutions:

Flip Flop available=> T Flip Flop. Flip Flop Required => S-R Flip Flop.


Inputs to Flip Flop Available

S R Qn T 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 X 1 1 1 0 X

Truth table Excitation Table Design for T S RQn RQ QR RQ QR

S S

QSRQT +=

0 0 1 0

1 0 X X



5) Convert T Flip Flop into D Flip Flops. Solutions:

Flip Flop available=> D Flip Flop. Flip Flop Required => T Flip Flop.



D Qn T 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0

Design for T

D Q Q Q

D

D

QDQDT +=

0 1

1 0



Logical Circuit.

6) Convert D Flip Flop into J-K Flip Flops. Solutions: Flip Flop available=> D Flip Flop.

Flip Flop Required => J-K Flip Flop.



J K Qn D 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1

Truth table excitation table Design for D J KQn KQ QK KQ QK

J

J QD =

0 1 1 0

0 1 1 0



Logical Circuit:

7) Convert D Flip Flop into T Flip Flops. Solutions: Flip Flop available=> D Flip Flop.

Flip Flop Required => T Flip Flop.



T Qn D 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0

Design for D

T Q Q Q T

T

QTQTD += Logical Circuit

0 1

1 0



Q. 24) Explain various types of shift register. Solutions:

“n bits are read together then it is called parallel output.” So, depending upon the type of input and output, shift register are divides into following types. A) SERIAL INPUT SERIAL OUTPUT (SISO) SHIFT REGISTER.

B) SERIAL INPUT PARALLEL OUTPUT (SIPO) SHIFT REGISTER.

C) PARALLEL INPUT SERIAL OUTPUT (PISO) SHIFT REGISTER.

D) PARALLEL INPUT PARALLEL OUTPUT (PIPO) SHIFT REGISTER.

A) SERIAL INPUT SERIAL OUTPUT (SISO) SHIFT REGISTER:

Serial I/P Serial O/P

The logical ckt. Of 4 bits SISO shift register using D-type flip flop is shown in Fig. (1) and using S-R/ J-K Flip Flop is shown in fig. (2). Operations:

(1) Initially Clr =0 So, Q3 Q2 Q1 Q0=0 0 0 0. During the operations Clr =1. (2) If ABCD=1011 is 4 bit number to br stored in 4 bit register , then initially MSB A=1 is applied at serial input Do.

After +ve edge of point clk cycle , as Do=1 . So, Qo become⊥ . (3) As Qo=1, so, D1=1. Hence after +ve edge if 2nd clk cycle Q1=1 and so on. (4) Finally after 4 clk cycles. 4 bit number ABCD=1011 is stored in the 4 flip flops i.e., Q3 Q2 Q1 Q0=1011 (5) As input binary bit applied as well as output binary bt read is serial hence it is called SISO shift register.

B) SERIAL INPUT PARALLEL OUTPUT (SIPO) SHIFT REGISTER:

Q3

Serial I/P Q2

Q1 Parallel O/P

Qo

The logical ckt. of 4 bit serial input parallel O/P shift register is shown in fig.(1). Operations:

(1) Initially Clr=0 So, Q3 Q2 Q1 Q0=0 0 0 0. During the operations Clr=1. (2) If ABCD=1011 is 4 bit number to br stored in 4 bit register , then initially MSB A=1 is applied at serial input Do.

So, Do = A = 1. Hence after +ve edge of 1st clk cycle, Q0 = A= 1.

4 bit SISO

Shift

Register

4 bit SIPO

Shift

Register



(3) As Qo =A= 1, So, D1= A=1and the next bit B=0 is applied at serial input Do. Hence sfter +ve edge of 2nd clk cycle, Q1 = A= 1 and Qo =B= 0. In this way the binary bit goes on shifting from one flip flop to another towards right and finally in 4 clk cycles, the 4 bit number is stored I the register i.e., Q3 Q2 Q1 Qo = A B C D = 1 0 1 1.

(4) All these 4 bits are read together in parallel. As input is serial and output is parallel, so, it is called SIPO shift register.

C) PARALLEL INPUT SERIAL OUTPUT (PISO) SHIFT REGISTER.

Do

Parallel I/P D1 Serial I/P

D2

D3

The logical ckt. Of 4 bit PISO shift register is shown in fig.(1).

Operations:

(1) Initially Clr=0 . So, Q3 Q2 Q1 Qo= 0 0 0 0, during the operation clr=1.

(2) If ABCD is 4 bit number to be stored then these 4 bits are applied to the corresponding 4 parallel input pins x and

control signal I is made zero(0). When I=0 the And gates number ”0” are enabled, AND gates number 1 are

disables. So, the inputs ABCD are applied through gates 0, 2 ti the inputs of flip flop i.e., D3 D2 D1 Do= A B C

D, at the positive edge if 1st clk cycle, all these 4 bits are stored in the 4 flip flop i.e., Q3 Q2 Q1 Qo= A B C D.

(3) As output is serial hence for obtaining serial output at Q3, we have to performs shift operations. the control input I

is made 1. So, AND gates number 0 are disabled, And gats number 1 are enabled. Hence the output of one flip

flop gets connected to the input of next flip flop through gates 1, @ i.e., D3=q2. D2=Q1, D1= Q0. At +ve edge of

each clk cycle the binary data goes on shifting from one flip flop to another towards right and we get serial output

at Q3.

D) PARALLEL INPUT PARALLEL OUTPUT (PIPO) SHIFT REGISTER.

D1

D2

D3

D4

DESCRIPTIONS:

(1) INITIALLY Clr=0. So, Q3, Q2, Q1,Qo=0 0 0 0. During the operation Clr=1.

4 bit PISO

Shift

Register

4 bit PIPO

Shift

Register



(2) If ABCD is 4 bit number to be stored then initially MSB A is applied at serial input.D3. At the +ve edge of 1st clk

cycle ,as input D3=A, So Q3=A.

(3) As D3=A. So,input D2=A and at the +ve edge of 2nd clk cycle Q2=A and so on. Hence the binary bit goes on

shifting from 1 flip flop to another towards left i.e., Q3= Q2, Q1 and Qo. And Q1, Q0. Hence it is called shift

register.

Q. 25) a] Design MOD 8 Synchronous Counter.

Solutions: MOD 8 counters will count 8 numbers from 0 to 7. (7) decimal = (111)binary i.e.

Maximum 8 bit binary number. So, we have to design 8 flip flop counter. Given synchronous counter.

Clk input Output Clk input Output

Q2 Q1 Qo Q2 Q1 Qo 1st 0 0 0 6th 1 0 1 2nd 0 0 1 7th 1 1 0 3rd 0 1 0 8th 1 1 1 4th 0 1 1 9th 0 0 0 5th 1 0 0



e] Design a counter for the following sequence. 0 5 7 4 6 Solutions: (7) decimal = (111) binary

Previous flip flop output (n)

Next required output (n+1) Input to flip flop

Q2n Q1n Qon Q2(n+1) Q1(n+1) Qo(n+1) J2 K2 J1 K1 Jo Ko 0 0 0 1 0 1 1 X 0 X 1 X m0 1 0 1 1 1 1 X 0 1 X X 0 m5 1 1 1 1 0 0 X 0 X 1 X 1 m7 1 0 0 1 1 0 X 0 1 X 0 X m4 1 1 0 0 0 0 X 1 X 1 0 X m6

Design for J2 2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

12 =J

Design for K2 2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

oQQK 12 = Design for J1 2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

21 QJ =

1 X X X

X X X X

X X X X

0 0 0 1

0 X X X

1 1 X X

Que

Nagp

Desi

1=KDesi

Jo =Desi

Ko =

estion Ban

pur Institute o

ign for K1 2Q QQ1

2Q

2Q

1=

ign for J0 2Q Q1

2Q

2Q

2Q= ign for Ko 2Q Q1

2Q

2Q

1Q=

nk : DCFM

of Technolog

Qo oQQ 1

Qo1 oQQ 1

Qo1 oQQ 1

X

X

1

0

X X

X

M III Sem

gy, Nagpur

01QQ Q

01QQ

01QQ

X

X

X

X

X X

0 1

CSE

01Q Q

01QQ

01QQ Q

X X

1 1

X X

X 0

X

X

01Q

01QQ

01QQ

X

1

X

0



Q.25) g] Design lock free or lock out counter to count in the following sequence. 0 5 2 4 6 Solutions: in lock free counter or lock out counter if due to any error the counter enters into any unused state (1, 3, 7) then in the next clk cycle the output of counter should charge from unused state to the used state. 1 0 5 2 Unused state 3

7 4 6 TRANSITION TABLE



Q2n Q1n Qon Q2(n+1) Q1(n+1) Qo(n+1) J2 K2 J1 K1 Jo Ko 0 0 0 1 0 1 1 X 0 X 1 X 0 1 0 1 0 1 0 X 1 1 X X 1 5 0 1 0 1 1 0 1 X X 0 0 X 2 1 1 0 1 0 0 X 0 X 1 0 X 6 1 0 0 0 0 0 X 1 0 X 0 X 4 0 0 1 0 0 0 0 X 0 X X 1 1 0 1 1 0 0 0 0 X X 1 X 1 3 1 1 1 0 0 0 X 1 X 1 X 1 7

Design for J2

2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

02 QJ = Design for K2


2Q

2Q

QoQK += 12

1 0 0 1

X X X X

X X X X

1 1 1 0



Design for J1


2Q

2Q



2Q

2Q

QoQK += 21 Design for Jo


2Q

2Q

12QQJO =

Design for Ko 2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

1=Ko

0 0 X X

0 1 X X

X X 1 0

X X 1 1

1 X X 0

0 X X 0

X 1 1 X

X 1 1 X

Que

Nagp

h] De

If the Solut

estion Ban

pur Institute o

esign MOD 6 2

6

e counter cen

tions:

Previous outpu

Q2n Q10 11 10 01 01 01 10 00 1

nk : DCFM

of Technolog

6 lock free co

nters into un

2

6

flip flop ut (n) 1n Qon Q1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 1

M III Sem

gy, Nagpur

ounter for th7

4

nused state th

7

4

Next requi

Q2(n+1) Q1 0 1 1 1 0 1 1

CSE

he following s1

5

hen the next o

ired output (

Q1(n+1) Q1 0 0 0 1 1 0 0

sequence.

output shoul

1

5

n+1)

o(n+1) J21 11 X1 10 X0 X0 X1 11 1

ld be 5

0

3

Inpu

2 K2 JX X

X 1 XX

X 0 X 0 X 0 X

X X X

ut to flip flop

J1 K1 X 0 X 1 0 X 0 X 1 X X 0 0 X X 1

p

Jo Ko 1 X X 0 X 0 X 1 0 X 1 X 1 X X 0

2 7 1 5 4 6 0 3



Design for J2 2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

12 =J

Design for K2


2Q

2Q

012 QQK = Design for K1


2Q

2Q

01 QK =

Design for J1


2Q

2Q

QoQJ 21 =

X 1 1 X

X 1 1 X

X X X X

0 0 1 0

X X 1 0

X X 1 0

0 0 X X

1 0 X X

Que

Nagp

Desi

Jo = Desi

Ko =

estion Ban

pur Institute o

ign for Jo 2Q Q1

2Q

2Q

12 QQ +=

ign for Ko 2Q QQ1

2Q

2Q

12QQ=

nk : DCFM

of Technolog

Qo1 oQQ 1

Qo oQQ 1

1

0

X

X

M III Sem

gy, Nagpur

01QQ

01QQ Q

X

X

0

1

CSE

01QQ Q

01QQ Q

X

X

0

0

01QQ

01QQ

1

1

X

X



i] Design 3 bit gray code counter. Solutions: The sequence of 3 bit gray code number is,

0 1 3 2

4 5 7 6

Previous flip flop

output (n) Next required output (n+1) Input to flip flop

Q2n Q1n Qon Q2(n+1) Q1(n+1) Qo(n+1) J2 K2 J1 K1 Jo Ko 0 0 0 0 0 1 0 X 0 X 1 X 0 0 0 1 0 1 1 0 X 1 X X 0 1 0 1 1 0 1 0 0 X X 0 X 1 3 0 1 0 1 1 0 1 X X 0 0 X 2 1 1 0 1 1 1 X 0 X 0 1 X 6 1 1 1 1 0 1 X 0 X 1 X 0 7 1 0 1 1 0 0 X 0 0 X X 1 5 1 0 0 0 0 0 X 1 0 X 0 X 4

Design for J2


2Q

2Q

QoQJ 12 =

INPUT OUTPUT A B C G2 G1 G0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0

0 0 0 1

X X X X



Design for K2 2Q QoQ1 oQQ 1 01QQ 01QQ 01QQ

2Q

2Q

QoQK 12 = Design for J1


2Q

2Q

QoQJ 21=

Design for K1


2Q

2Q

QoQK 21 =

Design for Jo


2Q

2Q

1212 QQQQJo +=

X X X X

1 0 0 0

0 1 X X

0 0 X X

X X 0 0

X X 1 0

1 X X 0

0 X X 1

Que

Nagp

Desi

Ko =

k] DeSolut

estion Ban

pur Institute o

ign for Ko 2Q QQ1

2Q

2Q

212 QQQ +=

esign Ex-3 cotions:

nk : DCFM

of Technolog

Qo oQQ 1

12Q

ode counter.

X

X

A 0 0 0 0 0 0 0 0 1 1

M III Sem

gy, Nagpur

01QQ Q

0

1

INPUT B 0 0 0 0 1 1 1 1 0 0

CSE

01QQ Q

1

0

C D0 00 11 01 10 00 11 01 10 00 1

01QQ

X

X

Y3 0 0 0 0 0 0 1 1 1 1

OUTPUT (Y2 0 1 1 1 1 0 0 0 0 1

(Ex-3 code) Y1 1 0 0 1 1 0 0 1 1 0

Y0 1 0 1 0 1 0 1 0 1 0



Example: (7)ex-3 = (10) decimal= (1010)binary



Q3n Q2n Q1n Qon Q3(n+1) Q2(n+1) Q1(n+1) Qo(n+1) J3 K3 J2 K2 J1 K1 Jo Ko

0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1 3

0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X 4

0 1 0 1 0 1 1 0 0 X X 0 1 X X 1 5 0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X 6 0 1 1 1 0 0 0 0 1 X X 1 X 1 X 1 7 0 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X 8 1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1 9 1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X 10 1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1 11 1 1 0 0 0 0 1 1 X 1 X 0 1 X 1 X 12

Design for J3

23QQ QoQ1 oQQ 1 01QQ 01QQ 01QQ

23QQ

23QQ

23QQ 23 QQ

0123 QQQJ = Design for K3


23QQ

23QQ

23QQ 23 QQ

23 QK =

X X 0 X

0 0 1 0

X X X X

X X X X

X X X X

X X X X

1 X X X

0 0 0 0



Design for J2 23QQ QoQ1 oQQ 1 01QQ 01QQ 01QQ

23QQ

23QQ

23QQ 23 QQ

012 QQJ = Design for K2


23QQ

23QQ

23QQ 23 QQ

012 QQK = Design for J1


23QQ

23QQ

23QQ 23 QQ

2301 QQQJ +=

X X 1 X

X X X X

X X X X

0 0 1 0

X X X X

0 0 1 0

0 X X X

X X X X

X X X X

0 1 X X

1 X X X

0 1 X X



Design for K1 23QQ QoQ1 oQQ 1 01QQ 01QQ 01QQ

23QQ

23QQ

23QQ 23 QQ

01 QK = Design for Jo


23QQ

23QQ 23QQ 23 QQ

1=Jo Design for Ko


23QQ

23QQ

23QQ 23 QQ

1=Ko

X X 1 X

X X 1 0

X X X X

X X 1 0

X X X X

1 X X 1

1 X X X

1 X X 1

X X 1 X

X 1 1 X

X X X X

X 1 1 X

Que

Nagp

i] De

Solut

estion Ban

pur Institute o

esign5 4 -2 -1

tions:

nk : DCFM

of Technolog

code conver

5

Decimal

0

1

2

3

4

5

6

7

8

9

M III Sem

gy, Nagpur

rters.

5 4 -2 -1 code

l digits

CSE

e converters

5

0

0

0

0

0

1

1

1

1

1

is used for d

C

4

0

1

1

1

1

0

1

1

1

1

decimal digits

Code

-2

0

1

1

0

0

0

1

1

0

0

s as given be

-1

0

1

0

1

0

0

1

0

1

0

elow.

1

0

1

0

1

0

0

1

0

1

0





Q3n Q2n Q1n Qon Q3(n+1) Q2(n+1) Q1(n+1) Qo(n+1) J3 K3 J2 K2 J1 K1 Jo Ko 0 0 0 0 0 1 1 1 0 X 1 X 1 X 1 X 0 1 1 1 0 1 1 0 0 X X 0 X 0 X 1 0 1 1 0 0 1 0 1 0 X X 0 X 1 1 X 0 1 0 1 0 1 0 0 0 X X 0 0 X X 1 0 1 0 0 1 0 0 0 1 X X 1 0 X 0 X 1 0 0 0 1 1 1 1 X 0 1 X 1 X 1 1 1 1 1 1 1 1 1 0 X 0 0 X X 0 1 X 1 1 1 0 1 1 0 1 X 0 X 0 X 1 X 1 1 1 0 1 1 1 0 0 X 0 X 0 0 X X X 1 1 0 0 0 0 0 0 X 1 X 1 0 X 0 1


23QQ

23QQ

23QQ 23 QQ

QoQQJ 123= Design for K3


23QQ

23QQ

23QQ 23 QQ

QoQQK 123 =

0 X X X

1 0 0 0

X X X X

X X X X

X X X X

X X X X

1 0 0 0

0 X X X




23QQ

23QQ 23QQ 23 QQ



23QQ

23QQ

23QQ 23 QQ

QoQK 12 = Design for J1


23QQ

23QQ

23QQ 23 QQ

21 QJ =

1 X X X

X X X X

X X 0 X

1 X X X

X X X X

1 0 0 0

1 0 X X

X X X X

1 X X X

0 0 X X

0 0 X X

1 X X X



Design for K1


23QQ

23QQ

23QQ 23 QQ

QoK =1 Design for Jo


23QQ

23QQ 23QQ 23 QQ

012 QQQJo += Design for Ko


23QQ

23QQ

23QQ 23 QQ

1=Ko (+5v)

X X X X

X X 0 1

X X 0 1

X X X X

1 X X X

0 X X 1

0 X X 1

1 X X X

X X X X

X 1 1 X

X 1 1 X

X X X X

Que

Nagp

m] D

Solut

coun

If I =

Desi

Jo =

estion Ban

pur Institute o

Design MOD

tions: For up

nter and the co

= 1 then count

Up

cou

Dow

Cou

ign for J1 I Q1

I

I

IQoQoI +=

nk : DCFM

of Technolog

3 UP-DOWN

0

p-down counte

ounting seque

ter will operat

Control i

I 0

0

unter 0 1

wn 1

unter 1

Qo1 oQQ 1

1

0

M III Sem

gy, Nagpur

N counter to

3

er one additio

ence will be 0

tes as down c

input

01QQ

0

1

CSE

count the fo

onal control in

0,3,1.

counter and th

Previous flip flop

output (n)Q1n Q0n

0 0

1 1

0 1

0 1

1 1

0 0

01QQ

X

X

ollowing sequ

1

nput I will be

he counting se

)

Next routpu

n Q1(n+1)

1

0

0

1

0

0

01QQ

X

X

uence.

used. If I = 0

equence will b

required ut (n+1)

Q0(n+1)

1

1

0

1

0

1

0 then counter

be 1,3,0.

Input to

J1 K1

1 1

X X

0 X

X X

1 1

X X

r will operate

o flip flop

Jo Ko

1 X

X 0

X 1

X 0

X 1

1 X

es as up down

n

Que

Nagp

Desi

1K

Desi

0J

Desi

0K =

estion Ban

pur Institute o

ign for K1 I Q1

I

I

1=

ign for J0 I Q1

I

I

1=

ign for K0 I Q1

I

I

11 IQQI +=

nk : DCFM

of Technolog

Qo1 oQQ 1

Qo1 oQQ 1

Qo1 oQQ 1

1

X

1

1

X

X

M III Sem

gy, Nagpur

01QQ

01QQ

01QQ

X

X

X

X

1

0

CSE

01QQ

01QQ

01QQ

X

1

X

X

0

1

01QQ

01QQ

01QQ

X

X

X

X

X

X



n] Design 3 bit synchronous UP-DOWN counter. Solutions:

Transition table:

Control input Previous flip flop output (n)

Next required output (n+1)

Input to flip flop

I Q2n Q1n Q0n Q2(n+

1) Q1(n+

1) Q0(n+

1) J2 K2 J1 K1 Jo Ko

0 0 0 0 0 0 1 0 X 0 X 1 X Up 0 0 0 1 0 1 0 0 X 1 X X 1 Counter 0 0 1 0 0 1 1 0 X X 0 1 X

0 0 1 1 1 0 0 1 X X 1 X 1 0 1 0 0 1 0 1 X 0 0 X 1 X 0 1 0 1 1 1 0 X 0 1 X X 1 0 1 1 0 1 1 1 X 0 X 0 1 X 0 1 1 1 0 0 0 X 1 X 1 X 1 1 1 1 1 1 1 0 X 0 0 X 1 X 1 1 1 0 1 0 1 X 0 1 X X 1

Down 1 1 0 1 1 0 0 X 0 X 0 1 X Counter 1 1 0 0 0 1 1 X 1 X 1 X 1

1 0 1 1 0 1 0 0 X 0 X 1 X 1 0 1 0 0 0 1 0 X 1 X X 1 1 0 0 1 0 0 0 0 X X 0 1 X 1 0 0 0 1 1 1 1 X X 1 X 1


23QQ

23QQ

23QQ 23 QQ

1=Ko (+5v)

0 0 1 0 X X X X

X X X X

1 0 0 0

Jo = Ko = (+5V) = (LOGIC 1)




23QQ

23QQ

23QQ 23 QQ

1=Ko (+5v)

Design for J1


23QQ

23QQ

23QQ

23 QQ 03031 QQQQJ +=


23QQ

23QQ

23QQ

23 QQ 03031 QQQQK +=

X X X X

0 0 1 0

1 0 0 0

X X X X

0 1 X X 0 1 X X

1 0 X X

1 0 X X

X X 1 0 X X 1 0

X X 0 X

X X 0 1

Que

Nagp

Ack

We MicrQueon th

estion Ban

pur Institute o

knowledge

are thankfroprocessorestions, answhe material

Referen

• D

• D

• D

• D

• F

• 8

• 8

nk : DCFM

of Technolog

ement:

ful to all thrs” that are wers and recited from vces:

Digital Design

Digital logic an

Digital Circuit

Digital Circuit

undamentals

bit microproc

bit microproc

M III Sem

gy, Nagpur

he authors cited during

elated informvarious cont

3rd edition by

d Computer D

& Design – R

& Design - A

Of Digital Ele

cessor & contr

cessor – Gaon

CSE

of Text Bg the compmation are ctributions fro

M. Morris Ma

Design by M.

R.P. Jain

A. P. Godse

ectronics – A.

roller – V. J. V

nkar

Books of Spilation of thcollectively om the auth

ano,

Morris Mano,

. Anand Kuma

Vibhute

ubject: “Dighis Questioncompiled a

hors and onl

ar

gital Circuitn Bank to pnd presenteline sources

ts & Fundaprovide to thed in single s.

amentals ohe students form based

of s. d

digital circuits & fundamentals of microprocessor

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